JPS63143588A - Non-synchronous writing/reading apparatus - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a device that performs asynchronous and continuous reading and writing to a storage device. The present invention relates to an asynchronous write/read device suitable for writing/reading that is impossible.

[Conventional technology]

Conventionally, a device in which two controllers asynchronously read and write to a storage device was disclosed in Japanese Patent Application Laid-Open No. 1986-
As described in Japanese Patent No. 247290, writing and reading of two controllers operating asynchronously was realized by applying a wait to one controller. The operation of the prior art will be explained using FIGS. 2 to 4.

FIG. 2 is a block diagram of an example of a display circuit of a personal computer, and the MPU writes data into the display memory 59 in order to rewrite display data. Further, in order to display on a CRT, a CRT controller (hereinafter referred to as CRTC) is a device that writes to and reads from the display memory 59.

51 is an MPU that writes and reads data to be displayed in the display memory 59; 52 is an MPU address; and 52 is an MPU data. 54 is CRTC, 55
, 56 are display address and display timing signals output from the CRTC. 57 is MPU address 52
58 is a memory address output from the multiplexer 57,
59 is a display memory that stores display data, ω is display parallel data read out from the display memory, and 66 is
A parallel-to-serial converter 67 is a parallel-to-serial converter that converts the display parallel data 60 into parallel data, and 68 is a CRT display device (hereinafter referred to as CRT) that displays the display serial data 67 as visible information. ). 69 is a display memory access signal indicating that the MPU 51 writes or reads from the display memory 59; 70 is a l't/W signal indicating whether the access to the display memory 59 is writing or reading;
High indicates read, low indicates write. 61 is
A ready controller that applies a WAIT operation to the MPU 51, 62 a write signal that instructs writing to the display memory 59, 63 a buffer enable signal, 7
2 is a buffer direction instruction signal, 71 is a ready signal, 64 is a buffer, and 65 is memory data.

FIG. 3 is a schematic diagram showing the relationship between the total display screen area sent to the CRT 68 and the display area, and FIG. 4 is a timing chart showing the WAIT operation of the ready controller 61 for the MPU 51.

In FIG. 2, the CRT C54 outputs a display address 55 and a display timing signal 56 in order to display the display data stored in the display memory 59 on the CRT 68. The display address 55 sequentially reads the display memory 59 +,
ff is an address for protruding, and the display timing signal 56 is high during the display period and low during the retrace period in the total display area of FIG. Display data to be displayed during the display period is stored in the display memory 59, which is sequentially read out from the top left of the screen and sent to the CFL T 68, where it is displayed as visible information on the CRT 68. This operation will be explained in detail below. During the display period, the CRTC 54 sequentially transfers display data from the upper left of the screen to the display memory 59.
The display address 55 is output so that it can be read more easily. The multiplexer 57 selects the display address 55 when the display timing signal 56 is high, and the selected display address 55 is given as a memory address to the display memory 59, and the display memory 59 reads the address indicated by the memory address box. The contents are output as display parallel data ω. The display parallel data (a) is converted into display serial data 67 by a parallel-to-serial converter and provided to the CRT 68. C
The RT 68 displays this display serial data as visual information. As a result of the above, the display period shown in FIG.
A read operation to the display memory 59 is performed using the display address 55 output from the TC 54.

Next, access to the display memory 59 during the flyback period shown in FIG. 2 will be explained.

During the retrace period, there is no need to display visible information on the CRT 68, so when the display timing signal 56 is low, the parallel-to-serial converter 66 outputs all the display serial data 67 in the 60-'' state.Next, the multiplexer 57 selects the MPU address 52 when the display timing signal 56 is 10-'' and supplies it to the display memory 59 as memory data Z58. As a result, ・MPU during the Fu line period
Reading and writing operations to the display memory 59 of 51 become possible. However, MPU 51 and CRT C5
4 operates asynchronously, it is conceivable that an access request from the MPU 51 to the display memory 59 occurs not only during the retrace period but also during the display period. In such a case, access to the display memory 59 is realized by applying WAIT to the MPU 51.

This W A I T operation will be explained below using FIG. 4.

As shown in FIG. 4, the display timing signal 56 is "4 high".
At point a, when a request to access the display memory 59 of the MPU 51 is issued, the display memory access signal 69 becomes 60-''.At this time, the ready controller 61 requests display memory access because the display timing signal 56 is "high". When the signal 69 becomes "low", the ready signal 71 is set to 10-" and the MPU 51 is placed in the WAIT state. The ready controller 61 has a display timing signal 54 of 60-”
Keep the ready signal 71 in the 60-'' state until point b, where
At this point b, the ready signal 71 is set to "high". As a result, the wAxT state of the MPU 51 is released and the MPU 5
1 restarts the previous display memory access, and the display memory access signal 69 becomes "high" at the 0 point when the access ends. In this way, the M
Access to the display memory 59 of the P U 51 is performed by the MPU
This is achieved by waiting until the retrace period when 51 can be accessed.

[Problem that the invention seeks to solve]

The above conventional technology is effective when the WAIT operation is possible for at least one of the two controllers that read and write to the memories of the set, and if both controllers are unable to perform the WAIT operation WAI is not considered for one set of memory.
It is impossible to realize a device in which two controllers that cannot write and read data asynchronously.

The object of the present invention is to continuously write non-WAIT,
The purpose of the present invention is to realize asynchronous write/read of continuous WAIT-incapable reading.

[Means for solving problems]

The above purpose is to divide the write cycle into two, one for writing to memory and the other for reading from memory, so that the memory is read continuously in the write cycle, and whether or not to import the read data. To determine and import the data, count up the read address, read the next data at the next memory read, and
If the reading address is not to be read, the read address is left as is, and the next time the memory is read, the same data as the previous one is read. An asynchronous control means is provided, and a capture means is provided which reads out from the memory according to the instructions of the asynchronous control means.
Writing is achieved by performing asynchronous reading with respect to this capturing means.

[Effect]

The asynchronous control means determines whether the data captured by the read cycle asynchronous to the write cycle has been read from the capture means.

If the data has been read, it takes in the data that has just been read from the memory and outputs a read counter clock so as to count up the read address. or,
If the captured data is not exceeded by the capturing means, the counter clock is not output. The capture means captures data read from the memory in accordance with a counter clock output from the asynchronous control means.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 5 to 9. FIG. 1 is a block diagram of an asynchronous read/write device using the present invention, where l is a dot clock, 2 is serial data, and 23 is a leading data clock. 3
is a writing means (corresponding to MPU 51 in FIG. 2) that takes in serial data 2 and assigns an address;
5 and 6 are input data output from the writing means,
In the write address, 4 is a character clock obtained by dividing dot clock 1 by four. 7 is a reading means (second
(corresponding to the CRTC in the figure), 8 is a reading address output from the reading means. 11 is a data direction control means for controlling the direction of the data bus, 12 is a memory data bus, and 13 is a memory. When the character clock is "high", the data direction control means 11 writes the contents of the write data bus 5 to the memory. Memory data bus 12 as data
is output to the memory 13 via the character clock 4.
When the character clock 4 is "high", the contents of the memory data bus 12 read from the memory 13 are output to the memory read data bus 14. 9 is an address switching means, 10 is a memory address bus, and when the character clock 4 is "high", it is written. When the address bus is 6.60-'', the read address bus 8 is selected and connected to the memory address 1o. 15 is a memory data latch means, 16 is a latch data bus, 17 is a capture means, 18 is a capture data bus, 19 is an asynchronous read means, 24 is an asynchronous read data bus, and 20 is a read clock. 21 is an asynchronous control means, 22
is the read counter clock. FIG. 5 is a timing diagram illustrating the operation of the writing means 3, FIG. 6 is a timing diagram illustrating write and read cycles, and FIG. 7 is a timing diagram illustrating asynchronous write and read operations. FIG. 8 is a circuit diagram of one implementation example of the asynchronous control means 21.

In FIG. 1, the writing means 3 extracts 8 bits at a time from the serial data 2 at the position where the leading data clock n is "high" from the input dot clock 1, serial data 2, and leading data clock phantom. Addresses are sequentially assigned to the data starting from φ, the data is output as write data to the write data bus 5, and the address is output as a write address to the write address bus 6.The above operation will be explained using FIG. Serial data 2 is shifted by one equation using the dot clock to create shift data from shift 1 data to shift 7 data.Furthermore, character clock 4 is created by dividing dot clock 1 by 4 using the first data clock 4 as a reference. , at the falling edge, latches serial data 2, shift 1 data to shift "7" data. By this, 8-bit write data is created from serial data 2 at the position where the first data clock command is "1 high". can do. Also, as a write address, the value is changed to 1-1" by "high" of the first clock data n.
By setting 0 and counting up at the falling edge of the character clock 4, it is possible to assign an address of "φ" to 8-bit write data including the leading data.

6 as shown in FIG.
The address switching means 9
connects the read address bus 8 to the memory address bus 10 when the character clock 4 is 10-'', connects the write address 6 to the memory address 10 when the character clock 4 is 4 high, and connects the data direction control means 11.
is to pass the contents of the memory data 12 to the memory data bus 14 when the character clock 4 is 10", and to pass the contents of the write data bus 5 to the memory data bus 12 when the character clock 4 is 6" high. to control. As a result, the memory 13 performs a read operation when the character clock 4 is "low" and performs a write operation when it is "high". As a result of the above, the serial data 2 taken into the writing means 3 is divided into 8 bits each.
The first data is sequentially addressed from "φ" and written to the memory 13 when the character clock 4 is "6" high.

Since this write operation is performed at the cycle of write data, writing is performed without any problem in terms of timing. Next, a read operation that is asynchronous with writing, that is, the operation of the read means 7 and the asynchronous control means 21 will be explained with reference to FIG. As mentioned above, reading is performed during the 10-9 period of character clock 4, which is the write cycle. In other words, character clock 4 is "
When the memory address bus 10 is connected to the read address bus 8 and is stored at the read address position from the memory 13 to the memory data bus 12, the memory address bus 10 is connected to the read address bus 8 and reads the data stored at the read address position from the memory 13 to the memory data bus 12. The IJ11-read data is passed to the read data bus 14.The memory data latch means 15 latches the data on the memory read data bus 14 at the rising edge of the character after clock 4 and outputs it to the latch data bus 16. As shown, it is assumed that the contents of 'Rφ'' are now read from the memory 13 and the contents are latched into the memory data latch means 15.

At point 'a', which is immediately before the next read period, the asynchronous control means 21 performs the following operation.
7 has latched the data of 'R-1' read in the read period before reading 'Rφ'. At point a, the asynchronous control means 21 determines whether or not the data on the fetched data bus 18 during the "R-1" period has been latched by the asynchronous read means 19 by the application of the read clock. The down edge point f'' is ahead of the point a'', and the data on the "R-1" capture data bus 18 is asynchronous read data.Therefore, the asynchronous control means 21 outputs a read count clock 22. As a result, the data "Rφ" on the latch data bus 16 is latched by the capture means 17, and the data on the capture data bus 18 becomes 'R.
φ". Also, by the read count clock 22,
The counter of the reading means 7 is counted up, and the address on the reading address bus 8 changes from 'Rφ' to R1''.
becomes. As a result, in the next read period of point a'',
Memory address 10 becomes 'R1''.The same operation is performed at point b'' below, and since point 'g' is ahead of point 'b', the asynchronous control means 21 outputs the read count clock 22. Then, the address on the read address bus 8 is set to R2'', and the data on the fetch data bus 18 is set to 'R1'. Next, at point 'C', point h' of the falling edge of the read clock 20 is not yet present;
It is slower than point C'. Therefore, the asynchronous control means 2
1, the read counter clock 22 is not output, so the contents of the read address bus 8 remain at R2'' and the contents of the fetch data bus 18 also remain at 'R1'. As a result, even if point 'h', which is carried from point 'C', comes, the data 'R1' is correctly latched onto the asynchronous fetch data bus 24. Further, in the read period after the CN point, the address on the memory address bus 1o becomes R2'', which is the same as in the previous read period, and the contents of R2'' are also read from the memory 13. Next, at point d'', read clock 2
It is determined that the lh1 point of the falling edge of 0 comes before the d' point, and the asynchronous control means 21 outputs the read count clock 22.

By repeating the above operations, as shown in FIG. 7, even if the memory 13 is accessed according to the write timing, the data on the asynchronous read data bus 24 is not accessed by the operation of the asynchronous control means 21. As can be seen, reading can be performed asynchronously with writing without any excess or deficiency of data.

FIG. 8 shows an example of realizing the asynchronous control means 21, and as can be seen from FIG. 8, it can be realized with a very simple configuration.

〔Effect of the invention〕

According to the present invention, at a writing timing with a fast cycle,
Asynchronous writing and reading is possible by controlling reading and writing to memory, reading from memory at a faster cycle than the cycle required for reading, and determining whether the read data is valid or invalid. realized. Furthermore, this control circuit can be realized with a very simple configuration. Further, the present invention can be used in a video interface device that converts display data for a CRT display to a liquid crystal display whose period is different from that of a CRT display.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an asynchronous writing/reading device using the present invention, FIG. 2 is a block diagram of an example of a display circuit of a personal computer, FIG. 3 is a schematic diagram showing a display area of display data 67, and FIG. The figure is a timing diagram showing the operation of the ready controller 61. FIG. 5 is a timing diagram showing the operation of the writing means 7, FIG. 6 is a timing diagram showing the period of reading and writing to the memory 13, FIG. 7 is a timing diagram explaining the operation of asynchronous reading, and FIG. 2 is a circuit diagram of one implementation example of the asynchronous control means 21. FIG. 1...Dot clock 2...Serial data 3
...Writing means n...Start data clock 4...Character clock 5...Write data bus 6...Write address bus 7...Reading means 8...Read address bus 9...Address Switching means 10...Memory at 1/bus 11...Data direction control means 12...Memory data bus 13...Memory 14.
...Memory read data bus 15...Memory data latch means 16...Latch data bus 17...Accepting means 18...Accepting data bus 19...Asynchronous reading means 20...Reading clock 24...・Asynchronous read data bus 21...Asynchronous control means 22...Read counter clock eyebrow 2 mouth 3 times Q -1/+
Ly54= concave

Claims (1)

[Claims] 1. Memory means; a first address supply means for supplying a write address signal to the memory means according to a first clock signal; and a second address supply means for supplying a read address signal to the memory means.
address supplying means connected to the memory, the first address supplying means, and the second address supplying means, and switching the write address signal and the read address signal according to the first clock signal to supply the memory. address switching means for supplying data to the memory; a first holding means for holding data read from the memory; and a first holding means for capturing and outputting data output from the first holding means in accordance with a capture control signal. 2 holding means; and the data outputted from the second holding means is transferred to the first holding means.
a third holding means for capturing in response to a second clock signal that is asynchronous with the clock signal of the write address; and a third holding means that compares the first clock signal and the second clock signal; When the timing at which switching to the read address signal is performed is before the timing at which the second clock signal takes in data from the second holding means to the third holding means, the second clock signal An asynchronous read/write device characterized by comprising control means for supplying the capture control signal to the holding means and supplying a signal for changing the read address to the second address supply means.