JP3043379B2 - Display control device and display control method - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a display control device and a display control method,
More specifically, the present invention relates to a display control device and a display control method for a display device including a display element capable of holding a display state updated by application of an electric field, for example, using a ferroelectric liquid crystal as an operation medium for display update. .

[Related Art] In general, a display device is used as an information display means for performing a visual expression function of information in an information processing system or the like, and a CRT display device is widely known as such a display device. .

In the display control of the CRT display device, the writing operation of the system side CPU to the video memory as the display data buffer of the CRT side and the reading and display operations of the display data from the video memory by the CRT controller of the CRT side are independent of each other. Executed.

In the case of CRT display control as described above, the operation of writing display data to a video memory for changing display information and the operation of reading and displaying display data from the video memory are independent of each other. The system-side program does not need to consider display timing and the like at all, and has an advantage that desired display data can be written at an arbitrary timing.

On the other hand, a CRT, in particular, requires a certain length of the display screen in the thickness direction, and therefore has a large overall volume, making it difficult to reduce the size of the entire display device. This also impairs the degree of freedom in using the information processing system using such a CRT as a display, that is, the degree of freedom in installation location, portability, and the like.

As a supplement to this point, a liquid crystal display (hereinafter, referred to as LCD) can be used. That is, according to the LCD,
The whole display device can be reduced in size (especially thinner). Among such LCDs, there is a display (hereinafter, referred to as FLCD: FLC display) using a liquid crystal cell of the above-described ferroelectric liquid crystal (hereinafter, referred to as FLC: Ferroelectric Liquid Crystal). The problem is that the liquid crystal cell has a display state preserving property with respect to application of an electric field. That is, in the FLCD, the liquid crystal cell is sufficiently thin, and the molecules of the elongated FLC in the FLCD are oriented in the first stable state or the second stable state depending on the direction of application of the electric field, and the electric field is removed. However, the respective alignment states are maintained. Due to such bistability of FLC molecules, FLCD has memory properties. Details of such FLC and FLCD are described, for example, in Japanese Patent Application No. 62-76357.

As a result, when driving an FLCD, unlike a CRT or other liquid crystal display, there is time margin in the cycle of continuous refresh driving of the display screen, and separately from the continuous refresh driving. In addition, it becomes possible to perform partial rewrite driving for updating the display state of only the portion corresponding to the change on the display screen.

[Problems to be Solved by the Invention] Therefore, if an appropriate and timely partial rewriting drive can be performed in the FLCD, the advantage of the FLCD will be further increased.

In addition, such a display device of an information processing system
The ability to use FLCDs compatible with CRTs would increase the flexibility and value of the system.

From the above viewpoint, it is possible to consider a display control mode in which the predetermined partial rewriting is prioritized over the partial rewriting of other display information. A display example of this is a display of cursor movement, and this display needs to change its display state in real time (perceptually) according to the operation of the mouse or the like by the operator.

If such a display is defined as an event, a configuration in which partial rewriting for the event is performed in accordance with the priority order among a plurality of events is described in, for example, Japanese Patent Application Laid-Open No. 2-93 by the present applicant.
No. 491. However, in the display control of this configuration, the information processing system provides the display device with information for identifying this processing at the time of partial rewriting relating to the event. For this reason, the control program of the information processing system using such a display device is described above.
This is significantly different from a control program for an information processing system using a CRT as a display device. As a result, FL
It becomes difficult to configure an information processing system compatible with CD and CRT.

On the other hand, when an FLCD is used as a display device of an information processing system while having compatibility with a CRT, an essential problem arises in its configuration. That is, the CPU on the system side only transfers the display data and the address for the display update to the display device side. Therefore, there arises a problem of how to determine the partial rewriting relating to the event from other partial rewriting, and a problem of how to prioritize the partial rewriting relating to the event as a result of the determination.

The present invention has been made in view of the above problems,
Certain events can be caught easily and reliably, and can be displayed prior to other partial rewriting displays.In addition, compatibility with the CRT can be maintained without significantly changing the software on the information processing system side. It is an object of the present invention to provide an FLCD display control device having the same.

By the way, recently, in order to reduce the load on the CPU placed in the system, signal data is
Rather than displaying by accessing the CPU's video memory, rather than providing such data generating circuitry and a compositing circuit for synthesizing the contents of the video memory, the CPU merely provides an indication of the display location of such data. Such a system is emerging. This is called a so-called hard cursor, and utilizes the fact that the data of the cursor itself is fixed. That is, if the cursor movement display is regarded as an event, the CPU only needs to change the display position information for such an event.

However, since an FLCD as a display device has an element having a memory property, it is desired to take a measure suitable for the characteristic and utilizing the characteristic. In other words, FLCD as a graphic event, especially when moving and displaying a hard cursor
It is desired that the control of is appropriately performed.

Therefore, a main object of the present invention is to ensure that the cursor at the old position is erased and the cursor is displayed at the new position reliably and efficiently when the cursor is moved and displayed.

[Means for Solving the Problems] For this purpose, the present invention provides a display device capable of updating a display state of a display element according to a display change according to a display change request from the outside (in the following embodiments, an FLCD26). Display control device (FLCD interface)
27) a display data storage means (video memory 41) for storing display data corresponding to each of the display elements; a cursor data storage means (cursor RAM 211) for storing cursor display data; Height storage means (size register 125) for storing the height (h) of data; first position storage means (current line register 131) for storing the cursor position before movement; and cursor position after movement. Second position storage means (difference register 121, movement direction register 123), and cursor display data before movement and a cursor after movement based on the cursor position before movement, the cursor position after movement, and the height. Overlap determining means (comparison control circuit 129) for determining whether or not display lines on which display data is displayed overlap; and a data indicating the cursor position before the movement. A size determining means (comparison control circuit 129) for determining the size of the data (Y2) indicating the cursor position after the movement (Y1) and the cursor position after the movement; When the size determination means determines that the data indicating the cursor position after the movement is large,
When a request is made to read out display data corresponding to (Y2−Y1 + h) display lines from the cursor position before the movement, and when the magnitude determination means determines that the data indicating the cursor position before the movement is large, Read request means (line address counter 133, request control circuit 137) for requesting read of display data corresponding to (Y1-Y2 + h) display lines from the cursor position after the movement, based on the request of the read control means When transferring each of the read display data, combining means (sub-scanning comparison circuit) for combining the cursor display data with the display data based on the cursor position information after the movement and the height.
207, a main scanning counter 209, and a logic synthesis circuit 213).

Further, the present invention is a display control method of a display device capable of updating a display state of a display element according to a display change in accordance with a display change request from the outside, wherein a display corresponding to each of the display elements is performed. Display data storage means for storing data; storing a cursor position before movement; storing a cursor position after movement; based on the cursor position before movement, the cursor position after movement, and the height of cursor display data. It is determined whether or not display lines on which the cursor display data before the movement and the cursor display data after the movement are displayed overlap with each other. If it is determined that the display lines overlap with each other, data indicating the cursor position before the movement ( Y1) and the data (Y2) indicating the cursor position after the movement are judged to be larger or smaller, and the judgment indicates that the data indicating the cursor position after the movement is larger. Read out the display data corresponding to the (Y2-Y1 + h) display lines from the cursor position before the movement, and if it is determined that the data indicating the cursor position before the movement is large, Display data storage means for requesting readout of display data corresponding to (Y1-Y2 + h) display lines from a subsequent cursor position, and storing display data corresponding to each of the display elements based on the request; And reading the display data from the display data, and combining the cursor display data with the display data based on the moved cursor position information and the height.

[Operation] In the above configuration, it is determined based on the cursor position before the movement, the cursor position after the movement, and the cursor height h whether or not the display lines for displaying the cursor display data before and after the movement overlap. In addition, when the magnitude of the data Y1 and Y2 indicating the cursor position before and after the movement is determined, and it is determined that they overlap, when it is determined that Y2 is greater than Y1, the cursor position from the cursor position before the movement is determined. Request readout of display data corresponding to (Y2-Y1 + h) display lines,
When it is determined that Y1 is larger than Y2, the display data corresponding to (Y1−Y2 + h) display lines is requested to be read from the cursor position after the movement, thereby transferring the corresponding display data. Is performed, and the cursor display data is combined with the display data based on the cursor position information and the cursor height after the movement. Therefore, when the cursor display lines overlap before and after movement, the number of overlapping lines is subtracted from the 2 × h line without performing the processing for the cursor height (h line) for both the new and old positions of the cursor. It suffices to perform processing for a number of lines.

Examples Hereinafter, the present invention will be described in detail with reference to the drawings.

(System Configuration) FIG. 1 is a block diagram of an entire information processing system incorporating a display control device according to an embodiment of the present invention.

In the figure, reference numeral 11 denotes a CP that controls the entire information processing system.
U and 12 are system buses consisting of an address bus, control bus, and data bus, and 13 is for storing programs,
The main memory 14 is used as a work area. A direct memory access controller (DMA) 14 transfers data between the memory and I / O devices without the intervention of the CPU 11.
AC), 15 is L for Ethernet (by XEROX)
LAN interface with AN (Local Area Network) 16, I / O device 17 for connecting I / O devices consisting of ROM, SRAM, RS232C specification interface, etc., 18 is hard disk device, 19 is floppy disk device, Reference numeral 20 denotes a disk interface for a hard disk device 18 or a floppy disk device 19, 21 denotes a high-resolution printer such as a laser beam printer or an ink jet printer, 22
Is a printer interface for the printer 21, 23 is a keyboard for inputting characters and other characters such as numbers, and 24 is a mouse as a pointing device, 25
Interface for keyboard 23 and mouse 24, 26
Is an FLCD (FLC display) which can be constructed using a display disclosed by the present applicant in Japanese Patent Application Laid-Open No. 63-243993 and the like, and 27 is an FLCD interface for the FLCD 26.

(Display control device) FIG. 2 shows an FLCD as an embodiment of the display control device of the present invention.
5 is a block diagram illustrating a configuration example of an interface 27. FIG.

In the figure, 31 is an address bus driver, 32 is a control bus driver, and 33, 43, and 44 are data bus drivers. Address data from the CPU 11 is supplied from the address bus driver 31 to one of the input units of the memory controller 40 and the address selector 35, and is selectively supplied to the FIFO memory 36 or 37 by switching the first switch S1. Stored. That is, these memories 36 and 37 (hereinafter referred to as FIFO (A) and
The FIFO (B) is a FIFO (First In First Out) memory for reading data in the order of writing, and the address data written in these memories 36 and 37 is selected by switching the second switch S2. Is read out.

The address data read from the memory 36 or 37, the address data from the address counter 38 described later, and the address data from the partial rewrite request circuit 100 described later are selectively addressed by switching the selector 50. The other input of the selector 35 is provided. The address counter 38 generates address data for line-sequentially refreshing the entire screen, and the generation timing of the address data is controlled by a synchronization control circuit 39. The synchronization control circuit 39 is provided with a switch control signal S for the switches S1 and S2 and the selector 50.
1 (A /), S2 (A /), a select control signal SLCT, and a data transfer request signal to the memory controller 40 described later are also generated. Further, the partial rewrite request circuit 100 and the synchronization control circuit 39 exchange a request signal REQ requesting a partial rewrite and an acknowledgment signal ACK when an event occurs (in this example, when the cursor is moved).

The control signal from the CPU 11 is given from the control bus driver 32 to the memory controller 40, and the memory controller 40 includes a sampling counter 34,
A control signal for the address selector 35 and a control signal for the video memory 41 described later are generated. Sampling counter
The 34 performs a counting operation based on the step signal from the memory controller 40, and generates a control signal C of the synchronization control circuit 39. The address selector 35 is a memory controller
Based on the control signal from 40, the address selector 35
Select one of the two address data supplied to the input section and supplies it to the video memory 41.

The video memory 41 stores display data,
It is composed of a dual-port DRAM (dynamic RAM), and writes and reads out display data via the data bus driver 33. The display data written in the video memory 41 is supplied to the image data synthesizing circuit 200 via the driver receiver 42, where the image data is appropriately synthesized, transferred to the FLCD 26, and displayed.

In addition, the driver receiver 42 supplies a synchronization signal from the FLCD 26 to the synchronization control circuit 39. The FLCD 26 incorporates a temperature sensor 26a that detects the temperature of the FLC.

Further, setting data described later from the CPU 11 is provided to the synchronization control circuit 39 via the data bus driver 43. Further, the output signal of the temperature sensor 26a is
Is transferred to the CPU 11 via.

47 is engaged with the data bus on the system bus 12 to provide the partial rewrite request circuit 100 with position information and the like of image data such as a cursor to be combined with the data in the video memory 41 (hereinafter referred to as combining data). A bus driver 48 for setting is a receiver for receiving the rewrite line address output from the partial rewrite request circuit 100 and guiding it to the selector 50.

An FLCD interface body in a broken line indicated by reference numeral 300,
The circuit unit indicated by reference numeral 400 including the partial rewrite request circuit 100 and the image data synthesizing circuit 200 may be configured integrally, but may be configured separately and the circuit unit 400 is mounted on the FLCD interface main body 300. Can be possible. That is, the circuit unit 400 may be an external circuit for the FLCD interface main body 300. In this case, for example, when the FLCD interface main body 300 is applied to a system corresponding to the so-called hard cursor function, the circuit unit 400 is suitable for mounting. . In other words, even in a system in which the CPU 11 does not access the video memory 41 when displaying or moving the data for synthesis such as a cursor, such as a system supporting a hard cursor function, such an event is detected and the part can be detected accurately and quickly. Rewriting is activated, and image composition can be realized.

FIG. 3 shows a configuration example of a partial rewrite request circuit 100 corresponding to a hard cursor according to the present embodiment.

Here, reference numerals 101 and 102 denote position registers (referred to as position registers I and II, respectively) for storing the old position or the new position of the cursor, and latch values alternately with respect to the setting from the CPU 11. That is, when displaying or moving the cursor, one stores the old position and the other stores the new position. Reference numeral 105 denotes a cursor size register for storing the size of a cursor to be displayed, and the size is set by the CPU 11. When displaying or moving the cursor, the CPU 11 sets the new position of the cursor in the position register I or II and sets its size in the cursor size register 105, but it is not necessary to set the size unless the size is changed. Good.

107 is a request control circuit, which is a position register I or II.
When the new position of the cursor is set in the register, the contents of the position register II or I storing the old position are loaded into the request address counter 109, and the synchronous control circuit 39 sends a partial rewrite request signal REQ for updating the cursor. Is sent. Then, the acknowledge signal ACK is sent from the synchronization control circuit 39.
Is supplied to the request address counter 109, the request address counter 109 sequentially counts up the line address at the old position by the cursor size (the number of lines) set in the cursor size register 105, The value is sent to the selector 50 side. This is because the FLC has a memory property, so that the cursor at the old position is immediately deleted before updating the cursor, as described later. Specifically, the video memory at that position is deleted.
This is a group of line addresses used to redisplay only the data in 41.

After that, the request control circuit 107 loads the value of the position register storing the new position into the counter 109, transmits the signal REQ, and responds to the input of the signal ACK.
For the new position. The line address group output at this time is used for displaying a cursor at the destination.

Each time a new cursor position is set from the CPU 11, the above operation is repeated to move (update) the cursor.
Is performed. In order to alternately set a new position in the position register I or II and alternately load the counter 109, for example, a toggle-operated switch may be inserted in an appropriate part.

FIG. 4 shows a configuration example of an image data synthesis circuit 200 corresponding to a hard cursor according to the present embodiment.

Here, reference numeral 201 denotes a position register in which the new position of the cursor updated by the CPU 11 is set, and reference numeral 205 denotes a cursor size register in which the cursor size is set.

FIG. 5 is an explanatory diagram of data stored in these registers. As shown in the figure, the upper left end on the display screen is set as the origin (0, 0), and the relative distance (X, Y) from that point is stored as the cursor position in the position register 201. On the other hand, the width w and the height h are set in the cursor size register 205.

Although the contents of the position registers 101 and 102 and the cursor size register 105 in the partial rewrite request circuit 100 shown in FIG. 3 may be the same as the position register 201 and the cursor size register 205, respectively, the partial rewrite request circuit 100 in FIG. Since it is sufficient to output a line address, only the data (Y and h) in the sub-scanning direction V may be set in the position registers 101 and 102 and the cursor size register 105. Also, the fourth
The contents of the cursor size register 205 in the figure may be changed only when the cursor size is changed, as described above.

In FIG. 4, ID and AD are an identification signal and an address / data signal transmitted from the video memory 41 of the FLCD interface main body 300, respectively. To explain these signals with reference to FIG. 6, the FLCD interface main body 300 outputs a data group of one main scanning line (H direction line in FIG. 5) in response to the horizontal synchronization signal HSYNC from the FLCD 26. This data group is a data group (“data 1”, “data 2”,...) From the left end pixel to the right end pixel in the one main scanning line. A line address of the line is added to the head of this data group, and the data group is transmitted as an address / data signal AD. On the other hand, in order to identify that the head of the signal AD is an address, "1", "data 1", "data 2",.
Is output at the time of output of the identification signal ID which becomes "0".

Referring again to FIG. 4, reference numeral 207 denotes a sub-scanning comparison circuit. The sub-scanning comparison circuit 207 calculates the value of the registers 201 and 205
It is determined whether or not the image data transmitted from the FLCD interface main body 300 is included in the line where the cursor is to be displayed, based on the line address at the head of the image data group. That is, it is determined whether or not the line address to be currently displayed is between Y and Y + h (see FIG. 5). Then, when it is determined that there is a time between them, a coincidence signal is sent to the main scanning counter 209.

The main scanning counter 209 counts the number of pixels in the main scanning direction based on the coincidence signal, and determines the current value based on the X value set in the position register 201 and the w value set in the cursor size register 205. It is determined whether or not the pixel is in the range of X to X + w. If the cursor display data is within the range, a corresponding position of the cursor RAM in which the cursor display data is expanded is designated, the data at that position is read out, and a synthesis instruction is given to the logic synthesis circuit 213.

In the logic synthesizing circuit 213, when the synthesizing instruction signal is not given from the main scanning counter 209, the address / data signal AD from the FLCD interface main body 300 is directly used for the FLCD2.
Output to 6 and if there is a compositing instruction, cursor RAM
The data read from 211 is subjected to a logical operation to output data synthesized.

The following operations are performed by the configuration shown in FIGS.

That is, the current position (X, Y) of the cursor is set in one of the position registers 101 and 102 in the partial rewrite request circuit 100 and the position register 201 in the image data synthesizing circuit 200, and based on the data held in the registers 201 and 205. A cursor appears. Therefore, even if the line on which the cursor is displayed is accessed by a refresh cycle and a partial rewrite cycle, which will be described later, the cursor is displayed at that position on that line, and the cursor is not erased by the access.

On the other hand, when the cursor is moved, ((X, Y) →
(X ', Y')), the data at the new position is set in the other of the registers 101 and 102 and also in the register 201.
First, the line addresses for the "h" lines are output from the old position "Y", and the corresponding line addresses and data in the video memory 41 are correspondingly output to the image data synthesizing circuit.
Output to 200. At this time, the register 201 in the circuit 200
Is already updated, the data is displayed on the FLCD 26 as it is without being synthesized. Therefore, the cursor display is erased from the line where the cursor was previously displayed. Thereafter, in response to the output of the line address for the “h” line from the new position “Y”, the data of the line is registered in the registers 201 and 205.
The cursor data is synthesized according to the content of (1), and the cursor is displayed at the new position (X ', Y').

(Operation Example) In the above configuration, when the CPU 11 changes display data in the video memory 41, an address signal of the video memory 41 corresponding to rewriting of desired data is transmitted to the memory controller 40 via the address bus driver 31. Given
Here, the memory access request signal of the CPU 11 and the synchronization control circuit 3
Arbitration with the data transfer request signal from 9 is performed. Then, when the CPU access side obtains the right, the memory controller 40 instructs the address selector 35 to
Switching is performed so that an address accessed by the CPU 11 is selected as an address to be given to the memory 41. At the same time, a control signal for the video memory 41 is generated from the memory controller 40, and data is read and written via the data bus driver 33. At this time, the CPU access address is stored in the FIFO (A) 36 or the FIFO (B) 37 via the switch S1, and is used for transferring display data described later. As described above, the display data access method viewed from the CPU 11 is the same as the conventional C
This is no different from the system using RT as a display.

When data is read from the video memory 41 and transferred to the FLCD 26, the synchronization control circuit 39 sends the data to the memory controller.
Data transfer request to 40, video memory
Address counter 38 or FI as address for 41
The FO side address is selected by the address selector 35, and a control signal for data transfer is generated from the memory controller 40, so that the data of the corresponding address is transferred from the memory cell to the shift register, and the control signal of the serial port is used. Output to the driver 42.

In the synchronization control circuit 39, the horizontal synchronization signal HSYN
Based on C, a timing is generated to alternately generate a cycle in which the screen is entirely refreshed line by line in units of a plurality of lines and a partial rewrite cycle in which the line accessed by the CPU 11 is rewritten. here,
The full refresh cycle is to sequentially rewrite downward from the top line (top line) on the display screen, and to the bottom line, return to the top line again and repeat rewriting. Things. The access line rewrite cycle is for rewriting a line accessed by the CPU 11 within a predetermined time immediately before the cycle.

As described above, in this example, basically, the operation of sequentially refreshing the entire screen of the FLC display 26 and the operation of rewriting the line accessed by the CPU 11 to change the display content are time-divisionally performed. However, when an instruction to move the cursor is given, the cursor display is updated quickly using the latter operation period.

First, a basic operation of the present example in which the refresh operation and the line rewriting operation are alternately performed in a time sharing manner without performing the cursor movement display will be described with reference to FIG. Here, the refresh cycle is set in units of 4 lines.
An example in which an access line rewrite cycle is performed in units of three lines will be described.

In FIG. 7, REF / ▲ ▼ is a timing at which a full refresh cycle and a rewrite cycle of the access line are alternately generated. When “1”, the full refresh cycle is performed, and when “0”, the access line is rewritten. Indicates a rewrite cycle. Further, T _a time of the entire surface of the refresh cycle, T _b represents the time of rewriting cycles access lines. In this example, T _a : T _b
= 4: 3, but an optimal value can be selected depending on the required refresh rate and the like. That is, it is possible to increase the refresh rate by increasing the ratio of T _a, it is possible to improve the responsiveness of the partial changes by increasing the proportion of T _b. This aspect will be described later.

To explain the states of the FIFO (A) 36 and the FIFO (B) 37, when the switch S1 is connected to the FIFO (A) 36 side (state
A / = 1), the address of the line accessed by the CPU 11 is F
It is sampled and stored in the IFO (A) 36. On the other hand, when the switch S1 is connected to the FIFO (B) 37 side (A / =
0), line address accessed by CPU11 is FIFO
(B) Stored in 37. Switch S2 is FIFO (A)
When connected to the 36 side (A / = 1), the address stored in the FIFO (A) 36 is output, and the switch S2 switches the FIFO (B) 37
Side (A / = 0), the address stored in the FIFO (B) 37 is output.

When one refresh of the entire screen is completed and the FLCD 26 outputs the vertical synchronizing signal VSYNC or when the carry occurs in the address counter 38, the address counter 38 is cleared and the line output in the next full refresh cycle is Returning to the 0th line, the synchronization control circuit 39
"1", "2",
Counts up sequentially to “3”. During this period, when the addresses of the lines L1, L2, L3 are accessed by the CPU 11, the switch S1 is connected to the FIFO (A) 36, so that L1, L2, L3
Is stored here, and then switch S2 is set to FIFO
(A) At the time of connection to 36, the addresses of L1, L2, L3 are output from here, and L1, L2, L3 are selected as output lines.
Here, the switching signal of the selector 50 is given by the signal SLCT from the synchronization control circuit 39, and is switched to the FIFO (A) and FIFO (B) sides as the output line address in the line access cycle.

At this time, since the switch S1 is connected to the FIFO (B) 37 side, the access address is stored in the FIFO (B) 37 side. In the refresh cycle, the selector 50
Is switched to the address counter 38 side, and the refresh operation is performed from the line following the previous cycle. In FIG. 7, the lines "4", "5", "6", and "7", which are the continuation of the previous cycle, are output after the line L3 is output. In the same manner as above, the above operation is repeated, but the reason for preparing two FIFOs is to consistently and efficiently perform sampling of an address accessed by memory on one side and outputting the sampled address on the other side at the same time. To do that. That is, during the address sampling period, the other FI
From the start of the output of the FO access line to the end of the full refresh cycle.After the end of the full refresh cycle, the rewrite cycle of the access line that outputs the address sampled in the immediately preceding sampling period is started, and at the same time, the address of the other FIFO is read. The sampling period will be started.

As described above, in the basic operation of this embodiment, the refresh cycle and the line rewriting cycle are alternately repeated. In FIG. 7, the repetition cycle is set to 7 lines as one unit, and T _a : T
_b = 4: has been described as 3, in this example further type of data being environmental conditions and displays such as temperature, or even T _a and the refresh rate or the like which is required according to the difference of the display device material FLCD T The ratio with _b can be changed.
That, T _a (corresponding to the line number M within one refresh cycle. That is T _a = M × (period of HSYNC)) ratio of can be improved refresh rate if the large, for example, low temperature or the like FLC device A good display state can be obtained even when the response is low or when displaying an image image. Conversely, corresponding to the line number N in the ratio (in one partial rewrite cycle T _b. That is T _b = N × (HSYN
If the period of C) is increased, the responsiveness of the partial display change can be increased, and it is possible to cope with a case where the refresh rate does not need to be high, such as at a high temperature or when displaying characters such as characters. Become.

Further, in the present embodiment, the number of lines in the repetition period can also be set, so that the refresh cycle and the rate of partial rewriting can be changed more finely, and more fine optimization can be achieved. For example, if it is necessary to give priority to the refresh rate, or if you want to give it priority, set the number of lines in the repetition cycle to 40.
If T _a : T _b = 4: 1, the entire surface can be refreshed for 32 lines and the access lines can be rewritten for 8 lines. If partial rewriting can be prioritized or prioritized, the number of lines in the repetition cycle is set to 10 and T _a : T _b
Assuming that 3: 2, the access line can be rewritten four times by performing a full refresh for six lines.

Furthermore, in the present embodiment, within the range of the number of partial rewrite lines set as described above, according to the number of lines accessed by the CPU 11 and the line access state,
The actual number P of partial rewrite lines performed between refresh cycles is adjusted. In other words, by adjusting the dynamic T _b time according to the number of lines that CPU 11 accesses, for example, eliminating waste line rewriting cycle when the infrequently accessed from CPU 11, so as to improve the refresh rate. This makes it possible to dynamically optimize the relationship between the operation followability and the refresh rate.

This corresponds to, for example, Japanese Patent Application No.
This can be done according to the rules and configurations disclosed in 105626.

Next, an operation state in the case where there is an instruction for cursor movement display will be described with reference to FIG. However, in this drawing, the height h of the cursor is set to “1” for simplification.

In the device according to this example, partial rewriting for cursor movement display is performed during a line access period,
That is, the synchronization control circuit 39 shown in FIG. 2 outputs a response ACK to the request signal REQ only during the line access period. If there is an instruction during the line access period, the partial rewriting for the moving display is performed within that period. If there is an instruction in the line access period and the period expires and processing cannot be performed, the processing is performed in the next line access period.

FIG. 8 shows a process for moving the cursor at the position on the line having the address EX1 to the position on the line having the desired address EX2 and further to the position on the line having the address EX3. I have.

When moving from EX1 to EX2, first use the current address EX1
The request circuit 100 sends a signal REQ to the synchronization control circuit 39 in response to a request for access to the line in order to erase the cursor on the line having the following. The synchronization control circuit 39 returns the signal ACK after the end of the refresh period and switches the selector 50 so that the address EX1 is accepted. In response, the line having that address EX1 is accessed, and as described with respect to FIGS. 3 and 4, only the data in video memory 41 at that line is displayed, ie, the cursor is erased from that line. Will be done. The same applies to the erasing mode when moving from EX2 to EX3.

Then, in order to display a cursor on the line having the new address EX2, a request circuit for requesting access to the line is issued.
When the signal 100 is transmitted by the signal REQ, the synchronization control circuit 39 immediately returns the signal ACK in this case and switches the selector 50 to accept the line address. This accesses the line with that address EX2,
As described above, the cursor data is synthesized at the new position and the cursor is displayed. The same applies to the erasing mode when moving from EX2 to EX3.

In this case, although partial rewriting (output of L1) is performed by line access between the deletion of the cursor on EX1 and the display on EX2, the processing of the synchronization control circuit 39 and the partial rewriting request circuit 100 the speed or the like and displays the output of L ₁ to EX2 also be longitudinal.

In this example, the line access period is set to three lines for the sake of simplicity, and the cursor height is set to “1”. However, in actuality, as shown in FIG. In some cases, the line access period can be determined in consideration of this.

(Other Embodiments) The present invention is not limited to the above-described embodiments, but may employ various configurations and control methods.

For example, in the above example, the refresh period and the line access period are alternately performed, the cursor movement display is performed only within the line access period, and the cursor movement display is performed prior to the normal line access. . However, the cursor display may be performed during the refresh period or only during the refresh period, and the priority of the cursor display may be appropriately determined. Further, the refresh period and the line access period may not be alternately performed, and only one of the refresh period and the line access period may be performed.

Also, for example, a partial rewrite request circuit corresponding to a hard cursor
100 can also be configured as shown in FIG.

In Figure 9, 121 is a differential register, as shown in FIG. 10, the value y ₁ in the sub-scanning direction V of the old (current) position of the cursor (x _1, y _2), a new position (x ₂ , y ₂ ) is set to the absolute value | y ₁ −y ₂ | of the difference from the value in the same direction. 123 is a movement direction register, which is “0” when y ₁ > y ₂ and “1” when y ₁ <y ₂
Is set. Reference numeral 125 denotes a cursor size register similar to that described above, in which a cursor height h and a width w are set.

Reference numeral 129 denotes a comparison control circuit that compares the contents of each register when executing the operation as shown in FIG. 11, and outputs a load signal to the line address counter 133. 131
Is a current line register in which an address of a line including the current position of the cursor is set. A line address counter 133 loads the contents of the current line register 131 in response to the load signal of the comparison control circuit 129, sequentially outputs a line address group that has been incremented from the value (line address), and outputs a selector 50. Output to
A request control circuit 137 sends and receives signals REQ and ACK to and from the synchronization control circuit 39, and is determined by a deviation between the old position (y ₁ ) and the new position (y ₂ ) and a cursor size (h). Only during the period, an enable signal is output to the line address counter 133 to execute the above-described stepping and line address output.

FIG. 11 is a flowchart for explaining an operation example of the configuration shown in FIG.

There is a cursor movement instruction from the CPU 11 and the difference register 121
If there is a setting in the movement direction register 123 (and the size register 125 if the cursor size is changed) (step S1), the difference | y ₁ −y ₂ | is less than h, that is, less than the height of the cursor. It is determined whether or not the movement is performed (step S3).

If a negative determination is made here, the current line register 13
The value of 1 (here, the old position y ₁ ) is loaded into the line address counter 133 (step S5), and the signal REQ is transmitted. Next, when the signal ACK is returned, the signal REQ is deactivated (steps S9 and S11), and the line address counter 133 performs a predetermined operation. Next, it is detected whether or not the address output for the line corresponding to the cursor height h has been completed, and if not completed, the process returns to step S7 to return to steps S7 to S1.
Repeat step 3. In this process, in the same manner as described above, the data in the video memory 41 of the h line from y ₁ is output to the image data combining circuit 200, whereas since the image data combining circuit 200. New position of the cursor is held No merging of the cursor data is performed, that is, the cursor is deleted from the old position.

Next, in step S15, the old position (y ₁ ), the result of the difference (| y ₁ −y ₂ |, and the new position (y ₂ ) determined by the moving direction)
Is set in the current line register 131, and in step S17, the same processing as in steps S7 to S11 is performed for h lines (step S19). As a result, the cursor is displayed at the new position.

On the other hand, if the deviation between the new and old positions is less than h, the moving direction is determined first (step S21). Here, the “+” direction in which the cursor is moved to the lower part of the screen, ie, y ₁ <y ₂
In the case of, the same processing as in the above steps S7 to S11 is performed (step S23).

Next, it is determined whether or not this processing has been completed for h + | y ₁ −y ₂ | lines. This is because when | y ₁ −y ₂ | <h, the display lines of the new and old cursors, that is, before and after movement, overlap, and h-line access (access for 2h lines) is not performed for both positions. This is based on the fact that it is sufficient to access the number of lines obtained by subtracting the number of overlapping lines from the 2h line (2h− (h− | y ₁ −y ₂ |) = h + | y ₁ −y ₂ | =
y ₂ -y ₁ + h). As a result, line access is performed with high efficiency, and in the process, the cursor at the old position is erased and the cursor is displayed at the new position without fail. Incidentally, after the end of the line was treated in the same manner as the step S15, it sets the y ₂ in the current line register 131 (step S27).

If y ₁ > y _{2 in} step S21, first in step S15
By the same processing as described above, y _{2 is set} to the current line register 131.
(Step S31), the same processing as Steps S7 to S11 and S27 (Steps S33 and S35) is performed, that is, the number (2h− (h− | y ₁₎ obtained by subtracting the number of overlapping lines from the 2h line. −y ₂ |) = h + | y ₁ −y ₂ | = y ₁ −y ₂ + h)
Is performed, the cursor at the old position is deleted and displayed at the new position efficiently and reliably.

In the above description, the present invention has been described with respect to an example corresponding to the hard cursor function. However, examples of data (synthesis data) to be combined with the data in the video memory include not only a cursor but also a moving image window or a message. There are superimposition, some form of overlay, and the like, and the present invention can effectively cope with these.

In these cases, for example, the partial rewrite request circuit of FIG. 3 will be described. Only when the data for synthesis is moved, the old position of the synthesis data is loaded into the request address counter 109 and the partial rewrite to the synchronization control circuit 39 is performed. Request signal
Send REQ. When the acknowledge signal ACK is supplied from the synchronization control circuit 39, the request address counter 1
The count permission is given to 09, and the request address counter 109 has the same size as the cursor size register 105 in the size register (the number of lines) set in the size register.
While sequentially counting up the line address at the old position,
The value is sent to the selector 50 side. This is because the FLC has a memory property, so that the synthesizing data at the old position is immediately erased before updating the synthesizing data as will be described later. Specifically, in the video memory 41 at that position, Is a line address group used for redisplaying only the data of.

After that, the request control circuit 107 loads the value of the position register storing the new position into the counter 109, transmits the signal REQ, and responds to the input of the signal ACK.
For the new position (abbreviated as operation A). The line address group output at this time is provided for displaying the data for combination at the destination. If there is no movement, this operation A may be repeated at a constant period faster than the refresh rate of the entire screen.

On the other hand, the same configuration and control mode as described above can be adopted for the image data synthesizing circuit. For example, it is sufficient to change the cursor RAM 211 in FIG. 4 to a frame buffer or the like for displaying data for synthesis.

Further, the circuit unit 300 including these circuits 100 and 200 may be configured for a plurality of types of synthesis data. Further, such a circuit section 300 may be provided for each purpose, and one or a plurality of circuit sections 300 may be appropriately mounted to switch the performance as a display control circuit.

Further, by utilizing the fact that the elements of the FLCD have a memory property, the composition circuit may be configured to be able to cope with a plurality of types of events, and the event may be switched.

[Effects of the Invention] As is apparent from the above description, according to the present invention, the cursor display data before and after the movement is determined based on the cursor position before the movement, the cursor position after the movement, and the height (h) of the cursor. In addition to determining whether or not the displayed display lines overlap, the size of data (Y1) and (Y2) indicating the cursor position before and after the movement is determined. If it is determined that the display lines overlap, the data after the movement is determined. When it is determined that Y2 is larger than the data Y1 before the movement, a request is made to read the display data corresponding to (Y2-Y1 + h) display lines from the cursor position before the movement, and the data Y1 before the movement is If it is determined that the display data is larger than Y2 after the movement, the display data corresponding to the (Y1−Y2 + h) display lines is requested to be read from the cursor position after the movement, so that the display data corresponding to the respective display data is read. Transfer , On the basis of the cursor position information after the movement and the cursor height was to synthesize the cursor display data to the display data. Therefore, when the cursor display lines overlap before and after movement, the number of overlapping lines is subtracted from the 2 × h line without performing the processing for the cursor height (h line) for both the new and old positions of the cursor. Since it suffices to perform processing for a number of lines, line access is performed with high efficiency, and in this process, the cursor at the old position is deleted and the cursor is displayed at the new position.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration example of an entire information processing apparatus incorporating a display control device of the present invention, FIG. 2 is a block diagram of a display control device according to an embodiment of the present invention, FIG. FIG. 4 is a block diagram showing a configuration example of the partial data rewriting request circuit; FIG. 4 is a block diagram showing a configuration example of an image data synthesis circuit; FIG. 5 is an explanatory diagram for explaining a cursor as an example of data to be synthesized; FIG. 6 is an explanatory diagram of signals output from the FLCD body according to the present embodiment, FIGS. 7 and 8 are timing charts for explaining two examples of the operation of the device of the present embodiment, and FIG. 9 is a partial rewrite request circuit. FIG. 10 and FIG. 11 are a block diagram showing another example of the configuration and an explanatory diagram of the operation and a flowchart of an operation example. 11 ... CPU, 12 ... System bus, 13 ... Main memory, 14 ... DMA controller, 15 ... LAN interface, 16 ... LAN, 17 ... I / O device, 18 ... Hard disk drive, 19 ... ... Floppy disk drive, 20 ... Disk interface, 21 ... Printer, 22 ... Printer interface, 23 ... Keyboard, 24 ... Mouse, 25 ... Interface, 26 ... FLCD (FLCD display), 26a ... Temperature Sensor, 27 ... FLCD interface, 31 ... Address bus driver, 32 ... Control bus driver, 33,43,44 ... Data bus driver, 34 ... Sampling counter, 35 ... Address selector, 36 ... FIFO ( A) Memory, 37: FIFO (B) memory, 38: Address counter, 39: Synchronous control circuit, 40: Memory controller, 41: Video memory, 42: Driver Receiver, S1, S2 ... switch, 50 ... selector, 100, 150 ... partial rewrite request circuit, 101, 102, 105, 121, 123, 125, 131 ... register, 107, 137 ... request control circuit, 109, 133 ... address counter, 200 ... image data synthesis circuit, 201, 205 ... … Register, 207… sub-scan comparison circuit, 209… main scanning counter, 211… cursor RAM, 213 …… logic synthesis circuit.

Continuation of the front page (56) References JP-A-2-103094 (JP, A) JP-A-1-265291 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5 / 00-5/40 G09G 3 / 18,3 / 36 G02F 1/133 505-535 G02F 1/133 545-580 G06F 3/14-3/153

Claims (2)

(57) [Claims] 1. A display control device for a display device capable of updating a display state of a display element according to a display change according to a display change request from outside, wherein display data corresponding to each of the display elements is provided. Display data storage means for storing cursor display data; height data storage means for storing the height (h) of the cursor display data; and first storage means for storing a cursor position before movement. Second position storage means for storing a cursor position after movement; and cursor display data before movement based on the cursor position before movement, the cursor position after movement, and the height. Overlap determining means for determining whether or not a display line on which subsequent cursor display data is displayed overlaps; data (Y1) indicating the cursor position before the movement; A magnitude judging means for judging the magnitude of the subsequent data (Y2) indicating the cursor position; and if the overlap judging means judges that the cursor position overlaps, the magnitude judging means determines the cursor position after the movement. When it is determined that the indicated data is large, it is requested to read the display data corresponding to the (Y2-Y1 + h) display lines from the cursor position before the movement, and the magnitude determination means determines the cursor position before the movement by the size determination means. When it is determined that the indicated data is large, read request means for requesting read of display data corresponding to (Y1-Y2 + h) display lines from the cursor position after the movement, and a read control means based on the request of the read control means. When transferring each read display data, the cursor data is displayed on the display data based on the cursor position information after the movement and the height. Display control device is characterized in that comprises synthesizing means for synthesizing the over data, the. 2. A display control method for a display device capable of updating a display state of a display element according to a display change according to a display change request from the outside, wherein display data corresponding to each of the display elements is displayed. Display data storage means for storing the cursor position before the movement, storing the cursor position after the movement, based on the cursor position before the movement, the cursor position after the movement and the height of the cursor display data, It is determined whether or not the display lines on which the cursor display data before the movement and the cursor display data after the movement are displayed overlap, and when it is determined that the display lines overlap, the data indicating the cursor position before the movement (Y1 ) And the data (Y2) indicating the cursor position after the movement are judged to be larger or smaller, and the judgment indicates that the data indicating the cursor position after the movement is judged to be larger. At this time, the display data corresponding to (Y2−Y1 + h) display lines is read from the cursor position before the movement, and if the data indicating the cursor position before the movement is determined to be large, Requesting readout of display data corresponding to (Y1−Y2 + h) display lines from the cursor position of, based on the request, from display data storage means storing display data corresponding to each of the display elements. Reading display data, based on the cursor position information after the movement and the height,
A display control method comprising combining the display data with the cursor display data.