JP3187082B2 - Display control device and display control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device and a display control method, and more particularly, to a display state updated by application of an electric field or the like using, for example, a ferroelectric liquid crystal as an operating medium for updating a display. TECHNICAL FIELD The present invention relates to a display control device and a display control method for a display device having a display element capable of holding a display.

[0002]

2. Description of the Related Art Generally, a display device is connected to an information processing system or the like as information display means for performing a visual display function of information. A CRT is widely used as such a display device, and FIG. 6 shows an example of a display control device for a CRT connected to such an information processing device.

In FIG. 1, reference numeral 1 denotes an address bus driver,
Reference numeral 2 denotes a control bus driver, and reference numeral 3 denotes a data bus driver, which are connected to a system bus 4 for signal connection between devices constituting the information processing system. 5 is a video memory for storing display data transferred via the data bus driver 3, and 6 is a display controller and a CR.
The driver for data transfer to and from T is 7 a CRT.

The video memory 5 is a dual port DRAM
(Dynamic RAM), and display data is directly written. The display data written in the video memory 5 is sequentially read out by a CRTC (CRT controller) 8 and displayed on a CRT 7.

That is, when writing display data, the CPU of the information processing system (not shown) accesses the address of the video memory 5 corresponding to the display area of the CRT 7. First, the access request signal is given to the memory controller 9 via the control bus driver 2,
This signal is arbitrated with a data transfer request signal or refresh request signal provided from CRTC8. Accordingly, when the CPU accesses the memory, the memory controller 9 sends the address selector 10
And an access address for writing data from the CPU to the video memory 5 through the address driver 1 and the address selector 10. Accordingly, a DRAM control signal from the memory controller 9 and display data via the data bus driver 3 are given to the video memory 5. Thus, the display data is written to the video memory 5.

On the other hand, the display on the CRT 7 is such that the CRTC 8 supplies a synchronization signal to the driver 6 and, in accordance with the synchronization signal,
This is executed by the TC8 supplying a data transfer request signal to the memory controller 9 and a data transfer address to the address selector 10.

First, when a data transfer request signal is arbitrated by the memory controller 9 and an address selection signal is supplied from the memory controller 9 to the address selector 10 in response to the arbitration, the data transfer address from the CRTC 8 is transmitted to the address selector 10. To the video memory 5 via The video memory 5 is supplied with a DRAM control signal from the memory controller 9 to execute a data transfer cycle. The data transfer cycle is to transfer data in units of lines (corresponding to a raster of a front screen) of the video memory 5 to a shift register in the video memory 5. Line data can be transferred to the shift register.

The display data transferred to the shift register is sequentially read from the shift register and output to the CRT 7 for display by the serial port control signal from the CRTC 8 supplied to the video memory 5. The reading of display data from the video memory 5 and the accompanying display are performed line by line from the upper part to the lower part corresponding to the display area, and in one line, in a certain order from the left end to the right end. This is performed by a so-called full refresh operation.

Thus, in the case of CRT display control,
The writing operation of the CPU to the video memory 5 and the operation of reading and displaying the display data from the video memory 5 by the CRT controller 8 are executed independently.

In the display control device for a CRT as described above, the operation of writing display data to the video memory 5 for changing display information and the operation of reading the display data from the video memory 5 and displaying are independent. Therefore, the program of the information processing system does not need to consider display timing and the like at all, and has an advantage that desired display data can be written at an arbitrary timing.

On the other hand, the CRT, in particular, requires a certain length of the display screen in the thickness direction, so that the volume of the CRT as a whole increases, and it is difficult to reduce the size of the entire display device.
This also impairs the degree of freedom in using such an information processing system using a CRT as a display, that is, the degree of freedom in installation location, portability, and the like.

A liquid crystal display (hereinafter, referred to as LCD) can be used to compensate for this. That is, LC
According to D, it is possible to reduce the size (particularly, the thickness) of the entire display device. Some of such LCDs include the above-mentioned ferroelectric liquid crystal (hereinafter referred to as FLC: Ferroelectric Liquid Crystal).
(Hereinafter, referred to as an FLCD: FLC display) using a liquid crystal cell. One of the features of the display is that the liquid crystal cell has a display state preserving property when an electric field is applied. Therefore, when driving FLCD, CRT
Unlike other liquid crystal displays, there is enough time for the continuous refresh drive cycle of the display screen, and apart from the continuous refresh drive, the display state of only the part that is changed on the display screen Can be partially rewritten. Therefore, such an FLCD can be a large-screen display as compared with other liquid crystal displays.

Here, the FLCD has a sufficiently thin liquid crystal cell, and the elongated FLC molecules therein are oriented in a first stable state or a second stable state depending on the direction of application of an electric field. Even if the electric field is cut off, the respective alignment states are maintained. Due to such bistability of FLC molecules, FLCD has a memory property. Details of such FLC and FLCD are described, for example, in Japanese Patent Application No. 62-76357.

[0014]

However, when an FLCD having the above advantages is used as a display device of an information processing system by the same display control as the above-described CRT, the FLC
Because the speed of the display update operation is relatively slow, it may not be possible to follow a change in the display information, such as a cursor, character input, or scrolling, whose display must be rewritten immediately.

On the other hand, the information processing system uses the fact that partial rewriting, which is one of the features of the FLCD, is possible to perform this processing. Although there is a configuration in which the control program is provided, the control program in the information processing system must be largely changed in order to realize the above-described partial rewriting drive on the display screen.

An object of the present invention has been made based on the above-mentioned viewpoint, and an FLCD compatible with a CRT without largely changing software of an information processing system.
It is another object of the present invention to provide a display control device and a display control method.

It is another object of the present invention to provide a display control device and a display control method capable of realizing an optimum image quality by effectively utilizing the storability of a display state in an FLCD or the like.

[0018]

SUMMARY OF THE INVENTION The present invention provides a method for responding to temperature.
A display control device that uses a display device having a display screen on which a plurality of display elements having different responsiveness are arranged, and updates display based on display data on the display screen; Detecting means for detecting the temperature of the display device, and generating an address corresponding to a display line of the display screen at predetermined intervals based on the temperature of the display device detected by the detecting means. Means, reading means for reading display data from the storage means based on the address generated by the generating means, and transfer means for transferring the read display data to the display device. Here, the interval between the addresses generated by the generation unit is set to be wider between the address when the temperature detected by the detection unit is low and the address when the temperature is high detected by the detection unit. The present invention provides a display control device that uses a display device having a display screen on which a plurality of display elements having different responsiveness according to states are arranged, and updates display based on display data on the display screen. Storage means for storing
Detecting means for detecting the state of the display device; continuous address generating means for generating continuous addresses corresponding to display lines on the display screen; and continuous addresses generated by the continuous address generating means. The first
First converting means for converting the address into the address at the interval, second converting means for converting the continuous address generated by the continuous address generating means into the address at the second interval, and Selecting means for selecting any one of the first converting means or the second converting means based on the state of the display device; and the first converting means or the second converting means selected by the selecting means. Reading means for reading display data from the storage means based on the address converted by the converting means, and transfer means for transferring the read display data to the display device. Here, the temperature may be detected by the detection means. The present invention provides a display control method that uses a display device having a display screen on which a plurality of display elements having different responsiveness depending on temperature are arranged, and updates display on the display screen based on display data. Detecting a temperature of the device, generating an address corresponding to a display line of the display screen at predetermined intervals based on the detected temperature of the display device, and generating the address based on the generated address. The display data is read from a storage unit in which the display data to be displayed is stored, and the read display data is transferred to the display device. The present invention provides a display control method that uses a display device having a display screen on which a plurality of display elements having different responsiveness according to states are arranged, and updates the display on the display screen based on display data. Detecting a state of the device, generating a continuous address corresponding to a display line of the display screen, and setting the generated continuous address to a first address based on the detected state of the display device. Selecting one of the first conversion means for converting the address at the interval of the second or the second conversion means for converting the generated continuous address to the address at the second interval. Based on the address converted by the first conversion means or the second conversion means, display data is read from a storage means for storing display data, and the read display data is read Characterized in that it transferred to the display device.

[0019]

According to the above construction, the address of this line is generated from the address conversion means such as the address conversion table at intervals of a plurality of scanning lines composed of a plurality of display elements on the display screen. These lines are accessed in a so-called interlace mode, and the display state is updated.

The address conversion means has a plurality of conversion means, which are changed according to the temperature information and the address information to be rewritten, so that the display screen is constituted.
The interlace mode can be changed according to the temperature of the FLC or the like and the number of addresses for updating the display.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram of an information processing system using an FLC display device having a display control device according to an embodiment of the present invention as a display device for displaying various characters and image information.

In FIG. 1, reference numeral 11 denotes a CPU for executing control of the entire information processing system; 13, a main memory for storing a program executed by the CPU 11 and used as a work area for this execution; DMA controller (Direct Memory Access Controller) that transfers data between the main memory 13 and the various devices that make up this system without
troller (hereinafter referred to as DMAC). 15 is Ethernet
LAN (local area network) 16 such as (by XEROX) and LAN interface between the system, 17
Is an input / output device (hereinafter referred to as I / O) having a ROM, SRAM, RS232C interface, and the like. I / O 17
Various external devices can be connected. Reference numerals 18 and 19 denote a hard disk device and a floppy disk device, respectively, as external storage devices, and reference numeral 20 denotes a disk interface for performing signal connection between the hard disk device 18 and the floppy disk device 19 and the present system. 21A is a laser beam printer (hereinafter simply referred to as a printer) capable of recording at a relatively high resolution, 21B is a scanner as an image reading device, and 22 is a signal between the printer 21A and the scanner 21B and the system. A scanner / printer interface for making a connection. 23 is a keyboard for inputting various character information, control information, etc.
Reference numeral 24 denotes a mouse as a pointing device, and reference numeral 25 denotes a key interface for performing signal connection between the keyboard 23 and the mouse 24 and the present system. Reference numeral 26 denotes an FLC display device (hereinafter, also referred to as FLCD) whose display is controlled by an FLCD interface 27 as a display control device according to an embodiment of the present invention. It has a display screen as a medium. Reference numeral 12 denotes a system bus including a data bus, a control bus, and an address bus for connecting signals between the above-described devices.

In an information processing system including various devices connected as described above, generally, a user of the system
The operation is performed while corresponding to various information displayed on the display screen of the FLCD26. That is, external devices connected to the LAN 16 and the I / O 17, the hard disk 18, the floppy disk 19, the scanner 21B, the keyboard 23, the characters supplied from the mouse 24,
Image information and the like, and operation information related to the user's system operation stored in the main memory 13 are displayed on the display screen of the FLCD 26, and the user performs information editing and instructs the system while watching this display. Here, each of the above-mentioned various devices constitutes a display information supply unit for the FLCD 26.

FIG. 2 is a block diagram showing details of the FLCD interface 27.

In the figure, 31 is an address bus driver,
32 is a control bus driver, 33, 43 and 45 are data bus drivers, each of which is connected to each bus of the system bus 12. Address data when the CPU 11 accesses a video memory 41 to be described later for rewriting the display contents is supplied to one of the input sections of the memory controller 40 and the address selector 35 via the address bus driver 31, and the first switch S1 FIFO (A)
The data is selectively supplied to the memory 36 or the FIFO (B) memory 37 and stored therein. The FIFO (A) memory 36 and the FIFO (B) memory 37 (hereinafter, the FIFO (A) memory and the FIFO (B) memory are simply referred to as FIFO (A) and FIFO (B), respectively)
FIFO (First In) from which data is read in the writing order
First Out) memory, and the address data written in these memories 36 and 37 are selectively read according to the switching of the second switch S2.

The address data read from the memory 36 or 37 and the address data for accessing the video memory 41 similarly to the address data from the address conversion table memory 44, which will be described later, are the third data. Is selectively supplied to the other input section of the address selector 35 in accordance with the switching of the switch S3. Memory 44
The address conversion table is referred to based on the address from the address counter 38 which increments the value every time the display drive for one line of the display screen is performed, and the contents are output as address data. The address counter 38
As described above, the address is incremented by "1", and address data for refresh driving the entire display screen is generated. The generation timing of the address data is controlled by the synchronization control circuit 39. The synchronization control circuit 39 also generates a switching control signal for the switches S1, S2 and S3 and a data transfer request signal to the memory controller 40, which will be described later. The control of the signal generation timing and the switching timing of the switches S1, S2 and S3 by the synchronization control circuit 39 is performed by the horizontal synchronization signal (HSYNC) generated by the FLCD 26 every time the display drive for one line of the display screen is performed
It is made according to.

A control signal from the CPU 11 is supplied to a memory controller 40 via a control bus driver 32. The memory controller 40 controls a sampling counter 34, an address selector 35, and a video memory 41 described later in accordance with the control signal. Control. That is, when the CPU 11 determines address data for accessing the memory 41 during a predetermined period and accesses a different address, the memory controller 40 outputs only that data to the sampling counter 34, and the counter 34 counts this. This count value is given to the synchronization control circuit 39 and the interlace flag table memory 46, and may be used to determine a ratio of partial rewriting and refresh driving described later, or to determine an interlace mode. It is possible.

In the interlace flag table memory 46, the count value of the sampling counter 34 and the FL
One table is selected based on the information of the temperature sensor 26B in the C panel, and the contents are input to the address conversion table memory 44 to select a conversion table. In addition,
The information of the interlace flag table can be rewritten by supplying the contents of the table from the data bus driver 47.

The memory controller 40 performs arbitration between a memory access request signal from the CPU 11 and a data transfer request signal from the synchronization control circuit 39, and switches the output of the address selector 35 accordingly.
One of the two address data supplied to the input section of the address selector 35 is selected and supplied to the video memory 41.

The video memory 41 stores display data, and is constituted by a dual-port DRAM (dynamic RAM), and writes and reads display data via the data bus driver 33. The display data written in the video memory 41 is read out and displayed on the FLCD 26 via the driver receiver 42. Further, the driver receiver 42 supplies a synchronization signal from the FLCD 26 to the synchronization control circuit 39.

Further, data for setting a ratio between partial rewriting and refresh driving, which will be described later, and the like are supplied to the synchronization control circuit 39 via the data bus driver 43. Further, information for rewriting the contents of the address conversion table can be supplied to the memory 44 via the data bus driver 45.

The FLC panel 26A of the FLCD 26 is provided with a temperature sensor 26B for detecting its temperature, and the temperature control circuit 26C determines the temperature of the FLC panel 26A using a heater or the like based on the detected temperature. Perform control. The temperature control circuit 26C sets a flag value in the flag register 26E based on the detected temperature with reference to a table which the temperature control circuit 26C has and which will be described later with reference to FIG. At this time, the controller 26D that executes the control of the FLCD 26 switches the temperature table referred to above according to the state of the temperature table changeover switch 26S provided on, for example, the outer case of the FLCD 26 and operable by the user. By providing a plurality of tables according to the switch state, the temperature threshold value for the flag value can be changed, and as a result, the number of flags can be reduced. This makes it possible to simplify the hardware configuration. Note that a volume may be provided in place of the switch, and a plurality of temperature tables may be provided according to the value of the volume.

In the above configuration, when the CPU 11 changes the display, an address signal of the video memory 41 corresponding to the rewriting of the desired data is given to the memory controller 40 via the address bus driver 31.
Arbitration is performed between the memory access request signal and the data transfer request signal from the synchronization control circuit 39. Then, when the CPU access side obtains the right, the memory controller 40 sends the memory 41 to the address selector 35.
Switch to select the address accessed by the CPU as the address to be given to the CPU. At the same time, a control signal for the memory 41 is generated from the memory controller 40, and data is read and written via the data bus driver 33. At this time, the address data accessed by the CPU 11 is stored in the FIFO (A) 36 or the FIFO (B) 37 via the switch S1, and is used for transferring display data described later. As described above, the access method of the display data as seen from the CPU 11 is no different from the case of the above-described CRT.

When data is read from the video memory 41 and transferred to the FLCD 26, a data transfer request is issued from the synchronization control circuit 39 to the memory controller 40.
As an address for the video memory 41, an address conversion table 44 or an address on the FIFO side is selected by the address selector 35, and the memory controller
When a control signal for data transfer is generated from 40, the data of the corresponding address is transferred from the memory cell to the shift register, and is output to the driver 42 by the control signal of the serial port.

In the synchronization control circuit 39, as described above, the FLCD
Based on the horizontal synchronizing signal HSYNC from 26, a timing for generating a cycle for completely refreshing the screen in the interlace mode and a timing for causing a partial rewrite cycle for rewriting the line accessed by the CPU 11 are generated according to the embodiment of the present invention. . Here, the full refresh cycle refers to a cycle in which the lines constituting the display screen are displayed and driven at least once in the interlace mode, and this is the address conversion table 44 as described later.
The line to be accessed is determined according to the contents of the table selected by. The partial rewrite cycle of the access line is to rewrite the line accessed by the CPU 11 within a predetermined time immediately before the cycle.

As described above, in this example, basically,
The operation of refreshing the entire screen of the FLC display 26 and the operation of rewriting the partial line accessed by the CPU 11 to change the display content are alternately performed in a time-sharing manner. It is possible to set a period and a time ratio of those operations within one period.

First, the basic operation of the present example in which the refresh operation and the line rewrite operation are alternately performed in a time-division manner will be described.

To explain the state of the FIFO (A) 36 and the FIFO (B) 37, when the switch S1 is connected to the FIFO (A) 36 side,
The address of the line accessed by U11 is sampled and stored in the FIFO (A) 36. On the other hand, switch S1 is FIFO
When connected to the (B) 37 side, the address of the line accessed by the CPU 11 is stored in the FIFO (B) 37. Also switch
When S2 is connected to FIFO (A) 36, the address stored in FIFO (A) 36 is output.When switch S2 is connected to FIFO (B) 37, it is stored in FIFO (B) 37. The output address is output.

One refresh of the entire screen is completed,
When the FLCD 26 outputs the vertical synchronizing signal VSYNC or when a carry occurs in the address counter 38, the address counter 38 is cleared, and the line output in the next full refresh cycle returns to the line corresponding to the conversion table 44, Then, the count is sequentially incremented for each horizontal synchronization signal HSYNC provided through the synchronization control circuit 39. If the address of a certain line is accessed by the CPU 11 during this time, the switch S1 is connected to the FIFO (A) 36.
The address stored when S2 is connected to the FIFO (A) 36 is output therefrom, and an output line is selected. here,
The switching signal of the switch S3 is supplied from the synchronization control circuit 39, and is switched to the FIFO (A) 36 and FIFO (B) 37 as an output line address in the partial rewriting cycle.

At this time, the switch S1 is set to the FIFO (B) 37
The address for access is stored in the FIFO (B) 37 side because it is connected to the side. In the refresh cycle, the switch S3 is switched to the address conversion table memory 44 side, and the refresh operation is performed in the interlace mode based on the contents of the conversion table.

Hereinafter, the above operation is repeated in the same manner,
The reason why two FOs are prepared is to sample addresses accessed in memory on one side and output the sampled addresses on the other side at the same time and without inconsistency and efficiently. That is, the address sampling period is from the start of the output of the access line of the other FIFO to the end of the entire refresh cycle. After the end of the full refresh cycle, the cycle of the access line rewrite cycle for outputting the address sampled in the immediately preceding sampling period is completed. At the same time, the address sampling period of the other FIFO is started.

As described above, in the basic operation of this embodiment, the refresh cycle and the partial rewrite cycle are alternately repeated, and the ratio of these cycles is determined by the environmental conditions such as temperature, the type of data to be displayed, and the FLCD. It can be changed according to the difference of the display device materials. That is, if the refresh rate is increased, the refresh rate can be improved, and a favorable display state can be obtained even when the responsiveness of the FLC element is low, such as at low temperatures, or when displaying an image. Conversely, if the percentage of partial rewriting is increased, the responsiveness of the partial display change can be increased, and even if the refresh rate is not high, such as when the temperature is high, the display of characters such as characters, and the operation display thereof are not required. It will be able to deal with good cases.

Further, in one embodiment of the present invention, the above-described refresh cycle is performed in a so-called interlace mode in order to prevent or adjust flicker and image variation on a display screen and obtain an optimum image quality. According to the temperature of the FLC panel and the number of lines accessed from the CPU 11. Hereinafter, a refresh cycle operation in the interlace mode according to an embodiment of the present invention will be described.

FIG. 3 is a schematic diagram showing details of the address conversion table in the memory 44 shown in FIG. As shown in FIG. 3, four conversion tables are provided in the memory 44, and these tables are selected according to the interlace flag information set in the interlace flag table of the memory 46.

FIG. 4 shows an example of the contents of the interlace flag table developed in the memory 46. The information related to the interlace flag includes the temperature flag information "00", "01", "10", "11" set in the temperature flag register 26E and the number of lines accessed from the CPU 11 set in the sampling counter 38. One is selected by the combination with. Then, one of the four conversion tables in the address conversion table 44 is selected based on the selected interlace flag information.

Each conversion table in the memory 44 stores the address data of the line to be accessed on the display screen according to each of the addresses 0 to N generated by the address counter 38. For example, the table corresponding to the interlace flag “00” is a table corresponding to the 32 interlace mode, and the address data of the first line is stored at the address 0, the 33rd at the address 1,... I have. Thus, when this table is used for conversion, the address data lines to be stored are driven every 31 lines from address 0 to address N in this order in this order. The storage pattern of the address data, that is, the interlace mode in the refresh operation (the line access pattern in the refresh cycle) is obtained by accessing the temperature flag information set according to the temperature of the FLC panel 26A and the CPU 11 in each table. Each has a different tendency according to the number of lines. For example, when the temperature of the FLC panel 26A is relatively low and the number of lines accessed from the CPU 11 is small, the address jump generated as the address from the address counter 38 steps from 0 to N is compared. The table with the highest tendency is selected. This makes it possible to compensate for the characteristic of the FLC, in which the response speed to the drive signal is slow at low temperatures, and to secure an apparently constant refresh cycle period. As a result, it is possible to prevent flicker on the display screen particularly in a low-temperature environment.

On the other hand, when the number of lines accessed from the CPU 11 is large, it occurs as the address from the address counter 38 advances from 0 to N regardless of the temperature of the FLC panel 26A. A table having a relatively small tendency of address jump is selected. As a result, the entire display screen is rewritten for each address having a small flying manner, so that the display can be updated without a sense of incongruity.

FIG. 5 is a conceptual diagram showing a temperature flag table included in the temperature control circuit 26C shown in FIG. 2. As is apparent from FIG. 5, four types of flags consisting of 2 bits are used for the temperature sensor 26B. Temperature and switch 26
It is selected according to the state of S and set in the temperature flag register 26E. The switch 26S is operated by the user as described above, and the user can switch the state of the switch 26S to A or B according to the image quality or the like. Thereby, a plurality of temperature thresholds can be provided for the flags, and the number of flags can be reduced to simplify the hardware configuration. The temperature information is not supplied to the CPU side of the information processing system but is processed in the display control device. Therefore, there is no need for the CPU to perform, for example, an interrupt process according to the temperature information, and the entire hardware and software are simplified.

As described above, the temperature of the FLC panel 26A is detected, a predetermined flag value is set in the flag register 26E by referring to the temperature table based on the detected temperature, and the value of the flag register 26E and the sampling counter 34 When one piece of interlace flag information is selected in the interlace table according to the value, in the address conversion table 44, the table used for address conversion is changed to a table corresponding to the interlace flag information. For example, when the value set in the register 26E is "10" and the value of the sampling counter 34 is "768", "11" is selected as the interlace flag information, and the table of the 4 interlace mode shown in FIG. 3 is selected. Is done.

The timing of changing the address conversion table is independently determined at any time in the present embodiment. For example, the synchronization control circuit 39 controls the address conversion table 44 to respond to the occurrence of HSYNC. May be changed.

The address conversion table shown in FIG.
Needless to say, the number of tables included in 44, the type of interlace mode, and the like are not limited to the above examples.

[0053]

As described above, according to the present invention,
By detecting the temperature of the display device, generating an address at predetermined intervals based on the detected temperature, reading and displaying the display data based on the generated address, a plurality of display elements having different responsiveness depending on the temperature can be formed. The display device having the arranged display screen can be displayed at an optimum interval in accordance with its responsiveness, and a favorable display state can be obtained.

Further, according to the present invention, the state of the display device is detected, continuous addresses are converted into either the first interval or the second interval based on the detected state, and based on the converted address. By reading and displaying the display data, the state of the display device, in particular, a display device having a display screen on which a plurality of display elements having different responsiveness depending on temperature are arranged at an optimum interval according to the responsiveness. The display can be performed, and a favorable display state can be obtained.

[0055]

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing system incorporating a display control device according to one embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration example of an FLCD interface as a display control device in FIG.

FIG. 3 is a conceptual diagram of an address conversion table shown in FIG.

FIG. 4 is a conceptual diagram of an interlace flag table shown in FIG. 2;

FIG. 5 is a conceptual diagram of a temperature flag table included in the temperature control circuit shown in FIG.

FIG. 6 is a block diagram showing a configuration of a conventional CRT interface.

[Explanation of symbols]

 11 CPU 12 Address bus 13 System bus 14 DMA controller 15 LAN interface 16 LAN 17 I / O device 18 Hard disk device 19 Floppy disk device 20 Disk interface 21 Printer 22 Printer interface 23 Keyboard 24 Mouse 25 Key interface 26 FLCD (FLCD display) 26B Temperature sensor 26E Temperature flag register 26S switch 27 FLCD interface 31 Address bus driver 32 Control bus driver 33,43,45,47 Data bus driver 34 Sampling counter 35 Address selector 36 FIFO (A) memory 37 FIFO (B) memory 38 Address counter 39 Synchronization control circuit 40 Memory controller 41 Video memory 42 Driver receiver 44 Address conversion table memory 44A Image data header register 46 Interlace flag table memory S1, S2, S3 switches H

Continuation of the front page (56) References JP-A-63-243922 (JP, A) JP-A-2-93583 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5 / 00 G02F 1/133 G09G 3/36

Claims (6)

(57) [Claims] 1. A display control device which uses a display device having a display screen on which a plurality of display elements having different responsiveness depending on temperature are arranged and updates display on the display screen based on display data. Storage means for storing data; detecting means for detecting the temperature of the display device; and an address corresponding to a display line of the display screen, and a predetermined address based on the temperature of the display device detected by the detecting means. Generating means for generating addresses at intervals; read means for reading display data from the storage means based on the address generated by the generating means; and transfer means for transferring the read display data to the display device. A display control device characterized by the above-mentioned. 2. An address interval generated by the generating unit is characterized in that an interval between addresses when the temperature detected by the detecting unit is low and an address when the temperature is high is wide when the temperature is low. The display control device according to claim 1. 3. A display control device which uses a display device having a display screen on which a plurality of display elements having different responsiveness depending on states are arranged and updates display on the display screen based on display data. Storage means for storing data; detection means for detecting a state of the display device; continuous address generation means for generating a continuous address that is an address corresponding to a display line on the display screen; First converting means for converting the continuous addresses generated by the means into addresses at a first interval; and second converting the continuous addresses generated by the continuous address generating means into addresses at a second interval. With conversion means. Selecting means for selecting either one of the first converting means or the second converting means based on the state of the display device detected by the detecting means; and the first converting means selected by the selecting means. Reading means for reading display data from the storage means based on the address converted by the converting means or the second converting means, and transfer means for transferring the read display data to the display device. Characteristic display control device. 4. The display control device according to claim 3, wherein the detecting means detects a temperature. 5. A display control method for using a display device having a display screen on which a plurality of display elements having different responsiveness depending on temperature are arranged and updating display on the display screen based on display data. Detecting a temperature of a display device, generating an address corresponding to a display line of the display screen at predetermined intervals based on the detected temperature of the display device, and displaying the address based on the generated address. A display control device, comprising: reading out display data from storage means storing display data to be displayed on a screen; and transferring the read display data to the display device. 6. A display control method for using a display device having a display screen on which a plurality of display elements having different responsiveness depending on a state are arranged, and updating display on the display screen based on display data, Detecting a state of a display device, generating an address corresponding to a display line of the display screen, and generating a continuous address, based on the detected state of the display device, Selecting either one of the first conversion means for converting the addresses at one interval or the second conversion means for converting the generated continuous addresses to the addresses at the second interval; Reading display data from storage means for storing display data based on the address converted by the first conversion means or the second conversion means, Display control method characterized by transferring to the display device.