JP2880245B2 - Display control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display control device, and more particularly, to a display updated by, for example, applying an electric field using a ferroelectric liquid crystal as an operation medium for updating a display. The present invention relates to a display control device for a display device having a display element capable of holding a state.

[Related Art] Generally, a display device is connected to an information processing system or the like as information display means that performs a visual display function of information. A CRT is widely used as such a display device, and FIG. 13 shows an example of a display control device for a CRT connected to such an information processing device.

In the figure, 1 is an address bus driver, 2 is a control bus driver, 3 is a data bus driver,
Each of them is connected to a system bus 4 for signal connection between devices constituting the information processing system. 5 is a video memory for storing display data transferred via the data bus driver 3, 6 is a driver for transferring data between the display control device and the CRT, and 7 is a CRT.

The video memory 5 is configured by a dual-port DRAM (dynamic RAM), and display data is directly written. The display data written in the video memory 5 is sequentially read out by a CRTC (CRT controller) 8 and displayed on a CRT 7.

That is, when writing the display data, the CPU of the information processing system (not shown) accesses the address of the video memory 5 corresponding to the display area of the CRT 7. First, the access request signal is given to the memory controller 9 via the control bus driver 2, and this signal is sent to the CR.
It receives arbitration with a data transfer request signal or refresh request signal provided from TC8. Accordingly, when the CPU accesses the memory, an address selection signal is supplied from the memory controller 9 to the address selector 10, and an access address for writing data from the CPU is transferred to the video memory 5 via the address driver 1 and the address selector 10. Given to. Accordingly, a DRAM control signal from the memory controller 9 and display data via the data bus driver 3 are given to the video memory 5. Thus, the display data is written to the video memory 5.

On the other hand, the indication on the CRT 7 is that the CRTC 8 supplies a synchronization signal to the driver 6, and in accordance with the synchronization signal, the CRTC 8 supplies a data transfer request signal to the memory controller 9 and a data transfer address to the address selector 10. Is executed by

First, when the data transfer request signal is arbitrated by the memory controller 9 and an address selection signal is provided from the memory controller 9 to the address selector 10 in response to the arbitration, the data transfer address from the CRTC 8 is transmitted to the video via the address selector 10. It is provided to the memory 5. The video memory 5 is supplied with a DRAM control signal from the memory controller 9 to execute a data transfer cycle. This data transfer cycle refers to the video memory 5
Is transferred to the shift register in the video memory 5 in units of lines (corresponding to the raster of the front screen), and one to several lines of data can be transferred to the shift register in one data transfer cycle. .

Then, the display data transferred to the shift register is
In accordance with the serial port control signal from the CRTC 8 applied to the video memory 5, the data is sequentially read from the shift register, output to the CRT 7, and displayed. The reading of display data from the video memory 5 and the accompanying display are performed line by line from the upper part to the lower part corresponding to the display area, and in one line, in a certain order from the left end to the right end. This is performed by a so-called full refresh operation.

As described above, in the case of the CRT display control, the CPU write operation to the video memory 5 and the CRT controller 8
The operation of reading and displaying the display data from the video memory 5 is independently executed.

In the case of the display control device for a CRT as described above, the writing of display data to the video memory 5 for changing display information and the like, and the operation of reading the display data from the video memory 5 and displaying the data are independent. Therefore, the program of the information processing system does not need to consider display timing and the like at all, and has an advantage that desired display data can be written at an arbitrary timing.

On the other hand, a CRT, in particular, requires a certain length of the display screen in the thickness direction, and therefore has a large overall volume, making it difficult to reduce the size of the entire display device. This also impairs the degree of freedom in using the information processing system using such a CRT as a display, that is, the degree of freedom in installation location, portability, and the like.

As a supplement to this point, a liquid crystal display (hereinafter, referred to as LCD) can be used. That is, according to the LCD,
The whole display device can be reduced in size (especially thinner). Among such LCDs, there is a display (hereinafter, referred to as FLCD: FLC display) using a liquid crystal cell of the above-described ferroelectric liquid crystal (hereinafter, referred to as ELC: Ferroelectric Liquid Crystal). The problem is that the liquid crystal cell has a display state preserving property with respect to application of an electric field. Therefore, when driving an FLCD, unlike a CRT or other liquid crystal display, there is time margin in the cycle of continuous refresh driving of the display screen, and apart from the continuous refresh driving, Partial rewrite driving that updates the display state of only the part corresponding to the change on the display screen becomes possible. Therefore, such an FLCD can be a large-screen display as compared with other liquid crystal displays.

Here, the FLCD has a sufficiently thin liquid crystal cell, and the molecules of the elongated FLC in the liquid crystal cell are oriented in a first stable state or a second stable state depending on the direction of application of the electric field, and the electric field is reduced. Even if it is cut, each alignment state is maintained. The FLCD has a memory property due to the bistability of the molecule of the FLC. Details of such FLC and FLCD are described in, for example, Japanese Patent Application
2-76357.

[Problem to be Solved by the Invention] However, the FLCD having the above advantages is replaced with the above-mentioned CR.
When used as a display device of an information processing system with the same display control as T, the time required for the display update operation of the FLC is relatively slow. For example, if the display is not immediately rewritten by cursor, character input, scrolling, etc. In some cases, it is not possible to follow a change in display information that cannot be achieved.

On the other hand, in order to perform this processing by utilizing the fact that partial rewriting, which is one of the features of FLCD, is possible, the information processing system must provide information for identifying this processing. Although there is a configuration for performing the above, in order to realize the above-described partial rewriting drive on the display screen, a significant change in the control program in the information processing system has been required.

The present invention has been made based on the above viewpoints,
Without drastically changing the software of the information processing system,
It is an object of the present invention to provide a display control device such as an FLCD compatible with a CRT.

It is another object of the present invention to provide a display control device capable of realizing optimal image quality by effectively utilizing the preservability of a display state in an FLCD or the like.

Means for Solving the Problems In order to achieve the object, the present invention provides a display control device for a display device capable of partially changing the display state of a pixel, in which a display on the entire screen of the display device is updated. Means for alternately performing a first period for updating the display content and a second period for updating only a portion where the display content is changed, a unit for storing the portion where the display content is changed and outputting the same in the second period, and the display Means for preventing the storage when a duplication of a part whose contents are changed is detected.

[Operation] According to the present invention, by providing a means for alternately performing a cycle of rewriting the entire screen in order and a cycle of rewriting a line accessed from the host side such as a CPU in a time-sharing manner,
It is not necessary to identify whether data is to be partially written in response to a command or the like, it is possible to maintain a constant refresh rate, and it is also possible to immediately display rewritten data.

Further, when the same portion is accessed repeatedly during the period of sampling and storing the above portion, the address of that portion is stored only once, so that the storage means can be used efficiently. In addition, even when the output amount is limited at the time of rewriting the changed portion, it is possible to prevent or reduce the occurrence of a portion that is accessed but is not displayed.

In addition, by making the repetition period and the time ratio of the above two cycles variable and configurable, it is possible to eliminate the effects of differences in operating temperature, display contents, etc., and to achieve optimization in various cases. Become.

Examples Hereinafter, the present invention will be described in detail with reference to the drawings.

First Embodiment FIG. 1 is a block diagram of an entire information processing system incorporating a display control device according to an embodiment of the present invention.

In the figure, reference numeral 11 denotes a CP that controls the entire information processing system.
U and 12 are system buses consisting of an address bus, control bus, and data bus, and 13 is for storing programs,
The main memory 14 is used as a work area. A direct memory access controller (DMA) 14 transfers data between the memory and I / O devices without the intervention of the CPU 11.
AC), 15 is L for Ethernet (by XEROX)
LAN interface with AN (local network) 16, I / O device 17 for connecting I / O devices consisting of ROM, SRAM, RS232C interface, etc., 12 hard disk device, 19 floppy disk device, 20 Is a disk interface for the hard disk device 18 and the floppy disk device 19; 21A is a high-resolution printer such as a laser beam printer, an ink jet printer;
B is a scanner as an image reading device, 22 is an interface for the printer 21A and the scanner 21B, 23 is a keyboard for inputting characters and other characters such as numbers, etc., 24 is a mouse as a pointing device, 25
Is an interface for keyboard 23 and mouse 24,
Reference numeral 26 denotes an FLCD (FLC display) which can be configured by using the display disclosed by the present applicant in Japanese Patent Application Laid-Open No. 63-243993 and the like, and 27 denotes an FLCD interface for the FLCD 26.

In the information processing system connected with the various devices described above, the user of the system generally performs an operation while corresponding to various information displayed on the display screen of the FLCD 26.
That is, external devices connected to the LAN 16, the I / O 17, the hard disk 18, the floppy disk 19, the scanner 21B, the keyboard 23, the characters supplied from the mouse 24, image information, etc.
In addition, operation information and the like related to the user's system operation stored in the main memory 13 are displayed on the display screen of the FLCD 26, and the user performs information editing and instructs the system while watching this display. Here, each of the above-mentioned various devices constitutes a display information supply unit for the FLCD 26.

FIG. 2 shows an FLCD as an embodiment of the display control device of the present invention.
6 is a block diagram illustrating a configuration example of an interface 27. FIG.

In the figure, 31 is an address bus driver, 32 is a control bus driver, and 33, 43, and 44 are data bus drivers. Address data from the CPU 11 is supplied from the address bus driver 31 to one of the input units of the memory controller 40 and the address selector 35, and is selectively supplied to the FIFO memory 36 or 37 by switching the first switch S1. Stored. Reference numeral 60 denotes a control unit for controlling the sampling of the address data. As will be described later, when an address included in the same line arrives twice or more in one sampling period, the storage of the second and subsequent addresses is prevented. I do. These memories 36 and 37 (hereinafter also referred to as FIFO (A) and FIFO (B), respectively) store data in a FIFO
(First In First Out) memory and these memories
The address data written in 36 and 37 is selectively read by switching the second switch S2.

The address data read from these memories 36 or 37 and the address data from an address counter 38 described later are selectively supplied to the other input section of the address selector 35 by switching a third switch S3. The address counter 38 generates address data for refreshing the entire screen line by line.
The generation timing of the address data is determined by the synchronization control circuit 39.
Is controlled by The synchronization control circuit 39 also generates a switching control signal for the switches S1, S2, and S3 and a data transfer request signal to the memory controller 40 described later.

The control signal from the CPU 11 is given from the control bus driver 32 to the memory controller 40, and the memory controller 40 generates a control signal for the address selector 35 and a control signal for the video memory 41 described later. The address selector 35 is a memory controller
Based on the control signal from 40, the address selector 35
Select one of the two address data supplied to the input section and supplies it to the video memory 41.

The video memory 41 stores display data,
It is composed of a dual-port DRAM (dynamic RAM), and writes and reads out display data via the data bus driver 33. The display data written to the video memory 41 is transmitted to the FLCD via the driver receiver 42.
Transferred to 26 and displayed. In addition, the driver receiver 42 supplies a synchronization signal from the FLCD 26 to the synchronization control circuit 39.

Through the data bus driver 43, data for setting a ratio between partial rewriting and refresh driving, which will be described later, according to the type of image and the like is given to the control register 51.

The FLC panel 26A of the FLCD 26 is provided with a temperature sensor 26B for detecting its temperature, and the temperature control circuit 26C uses the FLC using a heater or the like based on the detected temperature.
The temperature of the panel 26A is controlled. The temperature control circuit 26C
Sets a flag value in the flag register 26E based on the detected temperature with reference to a table described later with reference to FIG. At this time, the controller that executes the control of FLCD26
26D switches the table referred to above according to the state of a temperature table changeover switch 26S provided on, for example, an outer case of the FLCD 26 and operable by a user. By providing a table according to this switch, the number of flags can be reduced, and the hardware configuration can be simplified. Note that a volume may be provided instead of the above switch, and a plurality of tables may be provided according to the value of the volume.

53 is a ratio / cycle setting unit, which is a control register
In accordance with the information such as the image type stored in 51 and the information on the detected temperature (temperature flag), the driving conditions of the FLC panel 26A (the ratio of the refresh cycle and the partial rewrite cycle described later and their repetition cycle) are set. A form having a memory storing a table for selection can be adopted. As a form thereof, a RAM can be used as long as it does not require rewriting of the table contents from the system side, as long as it is based on ROM. Then, the operation of the synchronization control circuit 39 is controlled according to the table, and the FLC
Panel 26A can be driven appropriately.

In the above configuration, when the CPU 11 changes the display, the video memory 41 corresponding to the rewriting of the desired data is used.
Is given to the memory controller 40 via the address bus driver 31, and arbitration is performed between the memory access request signal of the CPU 11 and the data transfer request signal from the synchronization control circuit 39. When the CPU access side obtains the right, the memory controller 40
Switches the address selector 35 to select the address accessed by the CPU as the address to be given to the memory 41. At the same time, a control signal for the video memory 41 is generated from the memory controller 40, and data is read and written via the data bus driver 33. At this time, CP
The U access address is stored in the FIFO (A) 36 via the switch S1.
Alternatively, the data is stored in the FIFO (B) 37 and is used when transferring display data described later. As described above, the access method of the display data as viewed from the CPU 11 is not different at all from the case of the above-described CRT.

When data is read from the video memory 41 and transferred to the FLCD 26, the synchronization control circuit 39 sends the data to the memory controller.
Data transfer request to 40, video memory
Address counter 38 or FI as address for 41
The FO side address is selected by the address selector 35, and a control signal for data transfer is generated from the memory controller 40, so that the data of the corresponding address is transferred from the memory cell to the shift register, and the control signal of the serial port is used. Output to the driver 42.

In the synchronization control circuit 39, the horizontal synchronization signal HSYN
Based on C, a timing is generated to alternately generate a cycle in which the screen is entirely refreshed line by line in units of a plurality of lines and a partial rewrite cycle in which the line accessed by the CPU 11 is rewritten. here,
The full refresh cycle is to sequentially rewrite downward from the top line (top line) on the display screen, and to the bottom line, return to the top line again and repeat rewriting. Things. The access line rewrite cycle (partial rewrite cycle) is to rewrite the line accessed by the CPU 11 within a predetermined time immediately before the cycle.

As described above, in this example, basically, the operation of sequentially refreshing the entire screen of the FLC display 26 and the operation of rewriting the line accessed by the CPU 11 to change the display content are time-divisionally performed. In addition, the repetitive synchronization of these operations and the time ratio of those operations within one cycle can be set according to the type of image data, temperature conditions, and the like.

First, a basic operation of the present example in which the refresh operation and the line rewrite operation are alternately performed in a time-division manner will be described with reference to FIG. Here, an example is shown in which a refresh cycle is performed in units of four lines and a rewrite cycle of an access line is performed in units of three lines.

In FIG. 3, REE / ▲ ▼ is a timing at which a full refresh cycle and an access line rewrite cycle are alternately generated. When “1”, the full refresh cycle is performed, and when “0”, the access line is rewritten. Indicates a rewrite cycle. Further, T _a time of the entire surface of the refresh cycle, T _b represents the time of rewriting cycles access lines. In this example, T
_{Although a} : T _b = 4: 3, an optimal value can be selected depending on a required refresh rate or the like. That is,
By increasing the ratio of T _a can be increased refresh rate, it is possible to improve the responsiveness of the partial changes by increasing the proportion of T _b. This aspect will be described later.

To explain the states of the FIFO (A) 36 and the FIFO (B) 37, when the switch S1 is connected to the FIFO (A) 36 side (state
A / = 1, line address accessed by CPU11 is FIF
O (A) 36 is sampled and stored. On the other hand, when the switch S1 is connected to the FIFO (B) 37 side, A / = 0), CP
The line address accessed by U11 is stored in the FIFO (B) 37. When the switch S2 is connected to the FIFO (A) 36 (A / = 1), the address stored in the FIFO (A) 36 is output, and the switch S2 is connected to the FIFO (B) 37. (A / = 0), the address stored in the FIFO (B) 37 is output.

When one refresh of the entire screen is completed and the FLCD 26 outputs the vertical synchronizing signal VSYNC or when the carry occurs in the address counter 38, the address counter 38 is cleared and the line output in the next full refresh cycle is Returning to the 0th line, the synchronization control circuit 39
"1", "2",
Counts up sequentially to “3”. During this time, when the addresses of the lines L1, L2, and L3 which are not duplicated are accessed by the CPU 11, since the switch S1 is connected to the FIFO (A) 36, the addresses of L1, L2, and L3 are stored here. When the switch S2 is connected to the FIFO (A) 36, the addresses of L1, L2, L3 are output from here, and L1, L2, L3 are output lines.
Is selected. Here, the switching signal of the switch S3 is given as RFF / ▲ ▼ from the synchronization control circuit 39, and in the line access cycle, FIFO is used as the output line address.
(A), is switched to the FIFO (B) side.

At this time, since the switch S1 is connected to the FIFO (B) 37 side, the access address is stored in the FIFO (B) 37 side. When REF / ▲ ▼ becomes “1”, switch S3
Is switched to the address counter 38 side, and the refresh operation is performed from the line following the previous cycle. In FIG. 3, the lines "4", "5", "6", and "7", which are the continuation of the previous cycle, are output after the line L3 is output. In the same manner as above, the above operation is repeated, but the reason for preparing two FIFOs is to consistently and efficiently perform sampling of an address accessed by memory on one side and outputting the sampled address on the other side at the same time. To do that. That is, during the address sampling period, the other FI
From the start of the output of the FO access line to the end of the full refresh cycle.After the end of the full refresh cycle, the rewrite cycle of the access line that outputs the address sampled in the immediately preceding sampling period is started, and at the same time, the address of the other FIFO is read. The sampling period will be started.

And the same line is 2 in one sampling period.
If the address data is accessed more than once, the address data from the second time onward is
Is not remembered. That is, for example, in FIG.
(B) During the period when the sampling is performed by the CPU 37, the CPU 11 sets L4, L5, L5,
Although the line L6 is accessed, since the access to the line L5 is duplicated, the addresses of L4, L5, and L6 are stored in the FIFO (B) 37 without duplication. On the other hand, when the address sampling control section 60 is not provided, the address of the line L5 is redundantly stored. Therefore, in this case, assuming that the number of output lines in the partial rewrite cycle is "3" as in the example of FIG. 3, the address of L5 is stored in duplicate, so that the line of L6 is immediately rewritten. Is not performed, but in the case of this example, the rewriting of the lines L4, L5, L6 is immediately performed in the next partial rewriting cycle. In addition, this makes it possible to efficiently store the address of the line in the FIFO, which can contribute to miniaturization of the capacity.

FIGS. 4A and 4B show an example of the configuration of the sampling address control unit 60 and its operation, respectively. Here, 61 is the latch of the input address (step
The latch unit 63 that performs the process of S401) compares the input address with the latched address (the process of step S403), and determines whether there is a match (the process of step S405).
The comparison circuit 65 performs the storage in response to the coincidence signal, and inhibits the FIFO (A) 36 or the FIFO (B) 37 during the sampling operation from storing the address (step S407). This is a control circuit for generating a signal to cause the operation (step S409).

With this configuration, storage of the same address is prevented in units of lines, wasteful storage of duplicate addresses can be avoided, the size of the FIFO can be reduced, and data can be rewritten immediately as shown in FIG. The occurrence of a missing line can also be prevented.

It should be noted that overlapping addresses are not continuous, for example, L4, L5, L
Assuming a case where the data is transmitted as shown in FIG. 6 and L5, the address latch unit may be configured in a plurality of stages, and the current address may be compared with the already latched address.

The basic operation of the present embodiment repeatedly alternating with cycles of the refresh cycle and the line rewriting, T _a in the Figure 3 the repetition period of 7 lines as a unit: T _b = 4: has been described as 3, this embodiment in addition the type of data to be environmental conditions and displays such as temperature, or even to allow changing the ratio of T _a and T _b by the refresh rate or the like which is required according to the difference of the display device material FLCD. That is,
T _a (corresponding to the line number M within one refresh cycle, i.e. T _a = M × (period of HSYNC)) ratio of can be improved refresh rate if the large, for example, the responsiveness of the low temperature such as FLC device , And a good display state can be obtained even when an image is displayed. Conversely, the proportion of T _b (corresponding to the line number N in one partial rewrite cycle, T _b = N × (the period of the HSYNC) increasing the responsiveness of a large Tosureba partial representation of changes Can be done, at high temperature, when displaying characters such as characters, etc.
It is possible to cope with a case where the refresh rate does not need to be high.

Further, in the present embodiment, the number of lines in the repetition period can also be set, so that the refresh cycle and the rate of partial rewriting can be changed more finely, and more fine optimization can be achieved. For example, if it is necessary to give priority to the refresh rate or if it is desired to give priority, if the number of lines in the repetition cycle is set to 40 and T _a : T _b = 4: 1, the entire line is refreshed for 32 lines and the access line 8 lines can be rewritten. If partial rewriting can be prioritized or prioritized, the number of lines in the repetition period is set to 10 and _Ta :
If T _b = 3: 2, the entire surface refresh can be performed for six lines and the access line can be rewritten for four lines.

FIG. 5 shows an example of the structure of data processed by the system shown in FIG. One unit of data is composed of a management area CA and a data area D, and data composed of character strings such as characters and numerals, and data such as line drawings, natural pictures, and photographs are developed in the data area. The management area CA is provided with an area CRTL of management information (for example, data size and pitch and other information in the case of character data) about the expanded data and an area HA of header information indicating the image type.

When the user inputs a document or the like using the keyboard 23, information indicating that the data is a character string or the like is provided in the area HA, and management information for editing or the like is stored in the area CTRL. Will be added. Scanner 21B
When the input is performed by using, information of the mode (character mode for reading a character string, photo mode for reading a photo, photo fine mode for clearly reading a photo, etc.) set at the time of the reading is used. In the header information area HA,
Other management information is expanded in the area CTRL. Then, the data to which the management area CA set as described above is added is registered in a hard disk or a floppy disk in the form of a file.

In this example, when displaying an image input from the scanner 21B or the like, a character input from the keyboard 23 or the like, or a file read from a hard disk or a floppy disk, information indicating an image type is extracted from the header information area, and this is extracted. The header information H is stored in the control register 51 shown in FIG. Further, the user can rewrite the contents of the header information area HA, and the user can select the display quality.

FIG. 6 is a conceptual diagram showing a temperature flag table included in the temperature control circuit 26C shown in FIG. 2. As is apparent from FIG. 6, four types of flags composed of two bits are:
The selection is made in accordance with the temperature detected by the temperature sensor 26B and the state of the switch 26S, and is set in the flag register 26E. The switch 26S is operated by the user as described above, and the user can switch the state of the switch 26S to A or B according to image quality or the like.

Figure 7 is an image type (character, line drawing, a natural image, photographs, photos Fine etc.) optimal allocation repetition period and refresh cycles / partial rewrite cycle in accordance with the header information H and the temperature information indicating the T _H (ratio) 5 shows a configuration example of a setting unit 53 for selecting a setting. As shown, the setting unit 53, image type-specific header information H1, H2, ..., HY and, information T _H 1 corresponding to the temperature _{flag, T H 2, ..., T} H X ( in this example 4 The table has stored therein an M value (the number of lines in one refresh cycle) and an N value (the number of lines in one partial rewrite cycle) according to the combination with the type.

Therefore, one of M values in accordance with the header information H and the temperature information T _H at that time during the period of the display control operation (Figure 9), N values are read, the synchronization control circuit 39 in accordance with this A counter (not shown) counts the synchronization signal HSYNC and outputs a signal REF / ▲ ▼. The repetition period (= (M + N) ×
) And assignment (the period of _{HSYNC) (T a: T b} = M: N) will be is determined.

FIGS. 8 (A) to 8 (C) relate to one embodiment of the present invention, and are flowcharts showing a control procedure by the CPU 11 in response to a user operation in the information processing system shown in FIG. Figure (D) shows the FLCD following the above control procedure.
6 is a flowchart showing an operation procedure of the interface 27.

FIG. 8A shows an image input mode by the scanner 21B and a control procedure when the input data is displayed by the ELCD 26. In step S501, when a scanner icon on the display screen of the FLCD 26 is selected by, for example, operating the mouse 24 by the user, a window for displaying an input image at a predetermined position on the display screen is opened in step S502. Further, according to the image input by the scanner 21B in step S503, the user inputs characters, photos,
When the input mode is set from the photo fine, in step S504, the header information as described above with reference to FIG. 4 is selected as a default from a plurality of predetermined header values and is added thereto. At the same time, in step S505, this header information is set in the control register 51 shown in FIG.

Thereafter, in step S506, the input operation of the scanner 21B is started, and accordingly, in step S507, the input image data is temporarily stored in the main memory 13 in order to adjust the resolution of the scanner 21B and the FLCD 26.
The image data is expanded on the video memory 41 and displayed.

Next, in step S509, it is determined whether or not the user has changed the display state by operating, for example, a control symbol displayed on the display screen using a mouse or the like to change the display image quality. In this case, another header value is selected from the plurality of header values according to this change in step S510, and this header information is set in the control register 51 in step S511. Step S509
If it is determined that the display state has not been changed, the process ends.

FIG. 8B shows a control procedure in a character input mode compatible with a word processor. For example, when this processing is started by a predetermined key operation on the keyboard 23, the step
In S521, the input paper is displayed at a predetermined position on the display screen. Accordingly, in step S522, a predetermined header value is selected from the plurality of header values by default and added to a predetermined area of the memory. Further, in step S523, the header value is set in the control register 51.

Thereafter, when a key input is performed in step S524, the key input data is expanded and displayed in the video memory 41 in step S525.

Next, in step S526, it is determined whether or not the display state has been changed by the user in the same manner as in the control procedure of FIG. 8A. If the display state has been changed, the header value is changed in step S527. Then, the process returns to step S523 to set a header value in the control register 51 for display change. If the display state has not been changed, step S5
At 28, it is determined whether or not the key input has been completed. If the key input has been completed, the present process ends, and if not, the process returns to step S524.

FIG. 8C shows a control procedure of a file display mode for displaying a file stored in the hard disk 18 or the floppy disk 19.

When this process is started, the header information of the file is read in step S531, and the header information added to the file is set in the control register 51 in step S532. Subsequently, in step S533, the data in the file is stored in the memory 13 in order to adjust the resolution as described above, and then, in step S534, these data are developed and displayed in the video memory 41. Further, in steps S535 to S537, steps S509 to S511 in FIG.
A process similar to the process of is performed.

FIG. 8D shows the operation of the FLCD interface according to each control procedure shown in FIGS. 8A to 8C.

That is, in the FLCD interface 27, step S5
There is a change in the contents of the control register 51 in 41,
When the temperature had changed, it receives the H values and / or T _H values had this change in step S542, M, N values are reset in S543 in step S543. Therefore, in step S544, the operation of the synchronization control circuit 39 according to the M and N values is performed.

FIG. 9 shows an example of a display operation procedure performed by each unit of the apparatus shown in FIG.

First, in step S201, the initial state of the switches S1 and S2 is set. Here, the switch S1 is set to the FIFO (A) 36 side, and the switch S2 is set to the FIFO (B) 37 side. In step S202, the address counter 38 is cleared, and the refresh address is set to an initial value, for example, “0”. Next, in step S203, REF / ▲ is set to “1” so that the entire refresh cycle is performed. Also, a counter for counting the number of transfer lines in one refresh or partial rewrite cycle (here, one refresh cycle) is cleared, and the counter value LN is set to "0".

Next, in step S205, it is determined whether or not the period up to the last line is completed and a carry is generated in the address counter (return period). If the period is during the period, the process returns to step S200A. If it is not during the period, wait for HSYNC to come in step S206. When HSYNC comes, the data of the line indicated by the refresh line address is FL
Transfer to CD26. In step S208, it is determined whether or not the number M of lines to be transferred in one full refresh cycle (set by the setting unit 53) has been completed.
Is smaller than M, the process proceeds to step S209, the address counter 38 is counted up, and LN is incremented by one in step S210.
Step back and return to step S206. This is repeated until M lines are transferred. In the example shown in FIG.
Since = 4, the loop of steps S206 to S210 is repeated four times.

When the transfer of the M line is completed, at step S211 REF /
▲ ▼ is set to “0” so that the access line rewrite cycle is performed. Also, switch S1 and switch
The connection state with S2 is reversed, and the roles of FIFO address sampling and line address output are reversed.
Next, in step S212, the counter value LN is set to "0" again in order to count the number of transfer lines during the access line rewrite cycle. In step S213, FIFO (A) 36 or
The sampled address is read from one of the FIFOs (B) 37.

In step S215, the process waits for the HSYNC to be received. If the HSYNC is received, the data of the line at the address read out earlier is transferred to the FLCD 26 in step S216. Next, in step S217, it is determined whether the transfer of the line has been completed for N (set by the setting unit 53) lines. That is, if LN is smaller than N, the process proceeds to step S218, where LN is incremented by +1 and step S2 is performed.
Return to step 13 and repeat this until N lines have been completed. If N = 4, the loop of steps S213 to S218 is repeated four times. When the N lines are completed, the process returns to step S203 to execute the entire refresh cycle again.

As described above, the contents of the video memory 41 are displayed by repeating the full refresh cycle from step S203 to S208 and the access line rewriting cycle from step S211 to S217, and a carry occurs in the address counter 38. This is performed by returning the line of the entire refresh cycle to the head and initializing the signal.
On the other hand, the CPU 11 may read and write data from the video memory 41 independently of the display operation in order to obtain the displayed content.

As described above, reading data from the video memory 41 and transferring it to the FLCD 26 does not require command interpretation. Not only can it be configured with a relatively simple circuit, but also a graphic processor can be provided to interpret commands. This can be realized at lower cost than performing display control, and the performance can be improved while reducing the cost of the entire system.

(Others) Note that the present invention is not limited to the above-described embodiments, and it is needless to say that appropriate modifications can be made without departing from the spirit of the present invention.

For example, within the range of the number of partial rewrite lines set as in the above example, the actual number P of partial rewrite lines performed between refresh cycles is adjusted according to the number of lines accessed by the CPU 11 and the line access state. You may make it. According to this, by adjusting the dynamic T _b time according to the number of lines CPU11 has accessed, for example, eliminating waste line rewriting cycle when the CPU11 infrequently accessed, so as to improve the refresh rate It is possible to dynamically optimize the relationship between the following performance and the refresh rate.

In the above example, the repetition period and the ratio of the refresh cycle / partial rewrite cycle are set during the operation period based on the temperature information and the image type. However, the timing of the setting can be determined as appropriate. It may be performed during the flyback period. Further, not only the temperature information but also other environmental conditions may be considered. Further, if sufficient, the above setting may be performed based on one of the environmental condition such as temperature information and the image type.

Further, the configuration of the sampling address control unit 60 for preventing the duplicate address sent in one sampling period from being stored in the FIFO is not limited to that shown in FIG. 4A, and may be appropriately configured. it can. For example, when a character string is to be displayed on a line composed of a plurality of continuous lines, the CPU 11 may repeatedly access the plurality of lines (for example, lines L16 to L31) repeatedly.

FIG. 10 shows an example of the configuration of a sampling address control unit for coping with such a case. Here, 61-1,61-
2,..., 61-K are address latch units, each having a plurality of stages (K
), And the latched contents are shifted each time address data is input.
, 63-K are combined with the address latch units 61-1, 61-2,..., 61-K, respectively. And an OR circuit 64 for receiving the output signals of the comparison circuits 63-1 to 63-K.
Then, the FIFO control circuit 65 determines whether the FIFO
(A) Controls writing of address data to 36 or FIFO (B) 37.

In such a configuration, when the CPU 11 sequentially accesses a plurality of continuous lines and repeats them, in the first sequential access, none of the comparison circuits output a coincidence signal because the addresses of the plurality of lines do not overlap. Therefore, writing of those addresses to the FIFO is performed. However, in the second and subsequent sequential accesses, one of the comparison circuits outputs a coincidence signal.
The coincidence signal is supplied to the control circuit 65, so that the writing of the address to the FIFO is prohibited. This allows the FI
The efficient use of FO becomes possible.

Note that the number of stages K can be determined as appropriate, and within that range, overlapping sampling during sequential and repeated access of a plurality of lines is prevented.

FIG. 11 shows another example of the configuration of the sampling address control circuit 60. In this example, the value of K can be set.
It is not stored in the FO. Here, 601 is a register in which the K value is set by the CPU 11 through the data bus driver 603, 605 is an address latch unit that latches, for example, the first incoming address data in one sampling period, and 607 is the address and the next and subsequent addresses. Is a computing unit that computes the difference from the address that has entered. A comparator 609 compares the operation output with the K value set in the register 601. When the operation output is smaller than K, the comparator 609 outputs a signal indicating this and outputs the signal to the FIFO control circuit 611 via the FIFO control circuit 611. Inhibits the write operation.

The K value is appropriately set by the CPU 11. For example, when displaying 16-bit characters (characters extending over 16 lines), this may be set to "16". When displaying an image, for example, this can be set to “1”.

In this example, when the partial rewriting of the FLCD 26 is performed, the display is performed by simultaneously driving ± K lines with the set K lines as a unit, for example, with the lines stored in the FIFO as the center. Thus, the access line can be prevented from falling off. If data such as the character height is added to the header information shown in FIG. 5, and such data is also stored in the control register 51 shown in FIG. 2, the register 601 may not be provided.

FIG. 12 shows still another configuration example of the sampling address control circuit. Here, reference numeral 621 denotes a comparison bit number control register for controlling the number of bits to be compared between addresses. 623 is an address latch unit, 625 is an incoming address and the latched address,
The comparison is performed for the number of bits set in the register 621. Reference numeral 627 denotes a FIFO control circuit which inhibits writing of the FIFO when the comparison circuit 625 detects that the contents of both addresses correspond to the number of bits.

For example, if a character spans 10 lines, for simplicity, if considered in decimal, for example, even if the address of the line is "123" or "127", it belongs to the same 120s. That is, by comparing the upper two digits of the address to be compared, it can be determined that the addresses belong to the same row. That is, if data B indicating the number of upper digits to be compared is set in the comparison bit number control register 621 according to the height of a character or the like, the comparison is performed for all digits constituting the address. It becomes unnecessary. Actually, since the address is represented by a binary number, the configuration of the present example in which the upper few bits are compared is effective.

The B value can be set from the CPU 11 or the first value.
1, setting may be made from the control register 51 side as in the illustrated embodiment.

[Effects of the Invention] As described above, according to the present invention, there is provided means for alternately performing a cycle of rewriting the entire screen in order and a cycle of rewriting a line accessed from the host side such as a CPU in a time-division manner. Thus, it is not necessary to identify whether or not the data is to be partially written in response to a command or the like, and a constant refresh rate can be maintained, and the rewritten data can be displayed immediately.

Further, if the repetition period and the time ratio of the above two cycles can be made variable and settable, it is possible to eliminate the effects of differences in operating temperature, display contents, etc., and to achieve optimization in various cases. .

Further, when the same line is accessed a plurality of times in one sampling period, the address is stored only once, so that the FIFO memory or the like can be used efficiently and the subsequent partial rewriting cycle can be performed. In, even when the number of output lines is limited, it is possible to prevent or reduce the occurrence of lines that are accessed but are not displayed.

Therefore, the screen display can follow the movement of figures and cursors with high responsiveness without changing the specifications of the software and the like of the system using the FLC display at all, and the characteristics of the FLC can be further improved. It is also possible to provide a good display that is utilized for the minute. Also, from the viewpoint of the system
Compatibility between CRT and FLC is also maintained. In addition, since it is realized with a simple circuit configuration, it is possible to perform inexpensive and high-speed display control.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing apparatus incorporating a display control device according to an embodiment of the present invention. FIG. 2 is a block diagram showing a configuration of an FLCD interface as an embodiment of the present invention. 4 is a timing chart for explaining the basic operation of the FLCD interface shown in FIG. 2; FIG. 4A is a block diagram showing a configuration example of a sampling address control unit shown in FIG. 2; 5 is a flowchart for explaining the operation of the sampling address control unit shown in FIG. 4A, FIG. 5 is a block diagram showing an example of the structure of data processed by the control information system shown in FIG. FIG. 7 is a conceptual diagram showing a temperature flag table included in the temperature control circuit shown in FIG. 2, FIG. 7 is a conceptual diagram showing a configuration example of a setting unit shown in FIG. 2, and FIG. processing 9 is a flowchart showing an example of a control procedure by the CPU of the system; FIG. 9 is a flowchart showing an example of a display operation procedure performed by each unit of the apparatus shown in FIG. 2; FIG. 10, FIG. 11 and FIG. FIG. 13 is a block diagram showing another example of a different configuration of the sampling address control unit shown in FIG. 13. FIG. 13 is a block diagram showing the configuration of a conventional CRT interface. 11 CPU, 12 System bus, 13 Main memory, 14 DMA controller, 15 LAN interface, 16 LAN, 17 I / O device, 18 Hard disk device, 19 ... Floppy disk drive, 20 ... Disk interface, 21A ... Printer, 21B ... Scanner, 22 ... Printer interface, 23 ... Keyboard, 24 ... Mouse, 25 ... Key interface, 26 ...
… FLCD (FLC display), 26A …… Panel, 26B ……
Temperature sensor 26C temperature control circuit 26D controller 26E flag register 26S changeover switch
27 ... FLCD interface, 31 ... Address driver, 32 ... Control bus driver, 33,43 ... Data bus driver, 35 ... Address selector, 36 ... FIFO
(A) memory, 37: FIFO (B) memory, 38: address counter, 39: synchronous control circuit, 40: memory controller, 41: video memory, 42: driver receiver, S1, S2, S3 ... Switch, 51 ... Control register, 53 ... Ratio / cycle setting unit, 60 ... Sampling address control circuit, 61 ... Address latch unit, 63 ... Comparison circuit, 65 ... FIFO control circuit, 61-1 , 61-2, ‥‥ 1-36 ……
Address latch section, 64: OR circuit, 601: Register, 6
03: Data bus driver, 605: Address latch unit, 607: Operation unit, 609: Comparator, 611: FIFO control circuit, 621: Comparison bit number control register, 623: Address latch unit, 625 ...... Comparison circuit, 627 ... FIFO control circuit.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G02F 1/133 G09G 3/20 G09G 3/36 G09F 9/00

Claims (2)

(57) [Claims] 1. A display control device for a display device capable of partially changing the display state of a pixel, wherein a first period for updating the display of the entire screen of the display device and only a portion where the display content is changed are updated. Means for alternately performing the second period, means for storing a portion where the display content is changed and outputting the same during the second period, and storing the portion when the overlap of the portion where the display content is changed is detected. A display control device comprising means for blocking. 2. The display control device according to claim 1, further comprising means for setting a repetition period of the first period and the second period and a time ratio of these periods.