SU1660051A1 - Storage - Google Patents

Description

The invention relates to computing and can be used as a common graphic memory for the installation of physical experiments and computing systems, as well as when displaying the contents of this memory on a raster display screen. The aim of the invention is to expand the scope of the device due to the input of image elements at arbitrary addresses through an additional port and reading the image displayed on the screen. The storage device contains a raster generator, the first and second groups of memory blocks, multiplexers from the first to the seventh, the first and second code converters, the first and second decoders, inverter, register, first and second elements OR NOT and the element NOT. The purpose of the invention is achieved by organizing in the device an additional asynchronous port interfaced with a sensor with an arbitrary type of scan, and there are no distortions on the screen while the asynchronous port is operating. An asynchronous port can also be used to read the image displayed on the screen for secondary processing. 4 il.

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The invention relates to computing and can be used as a common graphic memory for the installation of physical experiments and computing systems, as well as to display the contents of this memory on the raster display screen.

The aim of the invention is to expand the scope of the device due to the possibility of entering image elements at arbitrary addresses through an additional asynchronous port and reading the image displayed on the screen.

Figure 1 shows the structural diagram of the storage device; in fig. 2-4functional circuits, respectively, of the raster generator, the first (second) decoder, and the address shaper.

The storage device (Fig. 1) contains the raster 1 generator, the first multiplexer 2, the shift register unit 3, the NOT element 4, the address generator 5, the first element OR NOT 6, the 7/8 code converters, the decoders 9,10 multiplexers from the second 11 on the sixth 15, the second element OR-NOT 16. the first 17 and the second 18 groups of memory blocks, the seventh multiplexer 19. register 20.

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In FIG. 1, the address inputs 21 and 22 of the first port of the device, the address inputs 23 and 24 of the second port of the device, the inputs of the data tracking signal 25, the write 26 and read 27, the first synchronization output 28 and the output 29 of the write confirmation signal, the data inputs 30 are also indicated. the second device port, the output-inputs 31 of the data of the first port of the device, the second synchronization output 32, and the information outputs 33-38 of the device.

The raster generator 1 (FIG. 2) contains L <flip-flops 39-42, elements AND-NO 43-45, element AND / 1I-HE 46, counters 47 and 48, register 49, converter 50 codes, counters 5153, element NOT 54 , converter 55 codes, elements IL AND-NOT 56 and 57.

The first (second) 9 (10) decoder (fig.Z) contains the elements AND NOT 58-63.

The shaper 5 .signal signals (figure 4) contains the register 64, the elements AND-NOT 65 and 66, ΰΚ-trigger 67.

2 also denotes a clock pulse generator 68.

The storage device operates in display mode and in blanking / regeneration mode.

In the display mode, a low level is present at the I / O output of the raster generator 1, which controls the multiplexer 2, and the signals "X" or "U" of the raster generator 1 are connected to the output of multiplexer 2, depending on the logic level of the signal "5O" of the raster generator 1, which are the address of a 4-point sequence displayed on the screen. Signals 23 and 24 from the sensor, which are the address of the recorded point, are connected to the input of multiplexer 11 depending on the logic level of the signal "50". Address (X and Y of the raster generator 1) of the four-point sequence displayed on the screen and address (23 and 24) The points recorded from the sensor are sent to multiplexers 12 and 13, which, using a signal from a 7-converter, connect them alternately to the address inputs of blocks 17 and 18 (one to 17, the other to 18, then vice versa), and switching occurs every 320 ns and is determined by the lower address address generator Ator 1 raster. The resolution of writing and reading depends on the control signals "CA5", "1Λ / Ε", "KA51", "BA52", "KA53", "BA54", which are generated on the decoder 9 and 10 of the following signals " KA5 "," CA5 "," 50 "from the 1 raster generator using control signals for" PA5 "from the converter 7 codes and for" CA5 "and" ννΕ "from the converter 8 codes. The signal number "KA5" is determined by the two low-order bits of the address 23 of the sensor, and the third digit determines the number of the storage unit, i.e. signal "САЗ" (and signal "УУЕ” depending on the write / read cycle). Since multiplexers 12 and 13 switch depending on the low-order bit of the address of the 1 raster generator, the 1 raster generator takes precedence, therefore if the third bits of the generator address do not match 1 raster and sensor address 23, the circulation goes simultaneously to two different blocks 17 and 18 of the accumulators, when the third digits coincide, the raster generator 1 is accessed. The sensor, if there is a signal 25 for tracking the sensor data, gets access to the block of the accumulator In the next cycle (after 320 ns), since the next call of the raster generator 1 will be to another block of drives. Simultaneously with the sensor data tracking signal 25, data from the sensor is received on bus 30, which are controlled synchronously with multiplexers 12 via multiplexers 14 and 15 and 13, are fed alternately to the information inputs of one of the blocks 17 or 18, where they are recorded by control signals from the decoders 9 and 10. At the end of each memory cycle, regardless of whether there was a sensor tracking signal 25 in this cycle or not output 29 generates a signal to confirm the recording of sensor data for additional synchronization of the sensor by binding to the end of the memory cycle. The information read at the address of the raster 1 generator is fed to the inputs of the shift register unit 3, where this information is recorded by the signal "PE" of the raster 1 generator following end of each read cycle. Then, on the signal "C from the raster generator 1, information from the block 3 of the shift registers is sequentially pushed out by the device output, followed by the signal" 5ΥΝΟ "sync mix of lowercase and frame sync pulses. Thus, in the frame display mode, the information is displayed on the screen and the information from the sensor without distortion of the information displayed on the raster display.

In the damping mode, the signal "N / 1L / E" has a high logic level. This signal controls multiplexer 2, connecting to its output addresses 21 "X" or 22 ’Ύ" computers depending on the signal '50 "of the raster 1 generator. The circulation of the sensor at the inputs 23, 24, 25 and at the output 29 to the blocks 17 and 18 is similar to the display mode. Instead of the 1 raster generator and this mode, the computer port is addressed by address buses 21 and 22, signals

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26-28 and input / output data 31. The two lower digits of the address 23 of the computer port are determined through a converter of 8 codes and decoders 9 and 10 of the segment number (signal number "KA5") of blocks 17 and 18 and the number of switched multiplexer inputs 19. The third digit of address 21 of the computer port determines the block number 17 or 18, where does the conversion take place. The recording signal from the computer port from the input 26 enters the inverter 5, where a signal is generated allowing through the converter 7 codes of the decoder 9 and 10 to issue control signals for recording information into the corresponding segment of blocks 17 and 18. This information is antiphased through multiplexers 14 and 15 information 30 of the sensor is fed alternately to the information inputs of the block 17 or 18. The read signal 27 from the computer port enters the inverter 5, where a signal is generated allowing through the decryption code converter 7 To tori 9 and 10, to issue control signals for reading information from the corresponding segment of block 17 or 18. Read information from a segment of blocks 17 or 18 through multiplexer 19 and information register 20, gated at the end of the memory cycle with a "PE" signal, subject to the presence of computer circulation signals in this cycle, is fed to the information inputs-outputs 31 of the computer port. After each cycle of the memory of recording or reading information from the computer port, in the presence of write signals 26 or 27 read, a passive device SIP synchronization signal 28 is output from the address generator 5. In the regeneration mode, for one memory cycle, through multiplexer 2, the address inputs of memory blocks 17 and 18 receive information from the raster generator 1, which is a regeneration counter. The regeneration cycle is repeated every 16 memory cycles, therefore, in order to regenerate 128 lines of memory blocks, it is necessary to connect to the multiplexer 2 addresses a 1 raster generator as shown in FIG. Bus addresses 23 and 24 are connected similarly to multiplexer 11. Thus, in blanking mode, the blocks 17 and 18 of the sensor and the computer are accessed simultaneously, which is impossible when using the prototype.

Claims (3)

Claims of storage device containing the first multiplexer, the information inputs of the first group of which are connected to the address outputs of the raster generator, and the information inputs of the second group are the address inputs the first and second groups of the first port of the device. The first group of memory blocks, the outputs of which are connected to the information inputs of the shift register block, the second group of memory blocks, the first and second code converters, characterized in that, in order to expand the field of application of the device due to the possibility of entering image elements at arbitrary addresses through an additional asynchronous port and reading the image displayed on the screen, multiplexers are introduced into the device, from the second to the seventh, the address shaper, the first and second decoders, the first and second the OR elements are NOT, the element is NOT and the register, the information inputs of the first and second groups of the second multiplexer are address inputs of the first and second groups of the second port of the device, the outputs of the first multiplexer are connected to the information inputs of the first and second groups of the third and fourth multiplexers, respectively, whose outputs are connected to the address inputs of the first and second groups of memory blocks, respectively, whose information inputs are connected to the outputs of the fifth and sixth multiplexers, respectively, and the outputs you Borki and write-read connected to the corresponding outputs of the first and second decoders, groups of inputs of which are connected to the outputs of the first and second groups of the first code converter, respectively, the inputs of the first and second groups of which are connected to the address inputs of the first group of the second and first ports of the device, respectively, the first and the second group of memory blocks are connected to the information inputs from the first to the fourth groups of the seventh multiplexer, the outputs of which are connected to the information inputs of the register, the outputs which are the input-output data of the first port of the device and connected to the information inputs of the first and second groups of the sixth and fifth multiplexers, respectively, the information inputs of the second and first groups respectively of which are the data inputs of the second port of the device, the first control output of the raster generator is connected to the first inputs of the first and the second decoders, the second inputs of which are connected to the second control output of the raster generator, the third control output of which is connected to the first control yuschim input of the first multiplexer, the third inputs of the first and second decoders, with the second and fourth inputs respectively of the first and vtoΊ 1660051 eight code converters and the control input of the second multiplexer, the outputs of which are connected to the information inputs of the second and first groups of the third and fourth multiplexers, respectively, whose control inputs are connected to the control inputs of the fifth and sixth multiplexers and the fifth output of the second converter, codes, the first input of which is connected to one of the inputs of the first group of the first code converter, the first input of which is connected to the tenth controlling output of the raster generator and to the third input of the car of the first through seventh, except the fifth, which are connected respectively to the fourth inputs of the first and second decoders, to the fifth inputs of the first and second decoders, to the first inputs of the second and first elements OR NOT, one of the inputs of the second group of the first converter codes are connected to the first and second control inputs of the seventh multiplexer, and another input is connected to the second input of the second code converter, the fifth input of which is the input of the data tracking signal and is connected to tert the input of the first code converter, the fourth input of which is connected to the first output of the inverter and to the sixth input of the second code converter, the seventh and eighth inputs of which are connected respectively to the second output of the addressing driver and to the eighth control input of the generator 5 raster, the ninth control output of which is connected to the second control input of the first multiplexer, the output of the second element OR is NOT connected to the register clock, the input of which is 10 is a read input of the device and connected to the third input of the inverter, the second input and the third output of which are, respectively, the write input and the first output of the device exchange confirmation, the fourth control output of the raster generator is connected to the control input of the shift register unit and to the element input NOT, output to ^{: one} connected to the second input of the second 20 elements OR NONE, the fifth control output of the raster generator is connected to the synchronous input of the shift register unit, the sixth control output of the raster generator is connected to the first input of the addressing driver and the second input of the first OR element, the output of which is the output of the device recording confirmation, the seventh raster generator control output is a sync output 30 devices, the outputs of the block shift registers are information outputs of the device. 1660051 Φϋ & Ζ 1660С51 FIG. eight