SU1363297A1 - Apparatus for representing graphic information on the screen of tv colour display - Google Patents

Abstract

The invention relates to automation and computing and can be used in display devices for color graphic information. The aim of the invention is to improve the image quality by expanding the range of reproducible color shades. The device contains digital-to-analog converters 1, 2, 3, switching unit 4, three registers 5, 6, 12, three blocks 7, 8, 9 of memory, comparison block 10, trigger 11 and register block 13 with necessary connections. The goal is achieved by the introduction of register 12, comparison block 10, register block 13 and trigger allows to obtain color shade codes not only from the outputs of memory block 8, but also from the outputs of memory blocks 7 and 9, which increases the range of reproducible shades . 5 il. i (L F1 / g. /

Description

one

The invention relates to automation and microscopic techniques and can be used in devices of devices | razheni color graphic information.

The aim of the invention is to improve the image quality by expanding the range of reproducible color shades.

1. shows a block diagram of the device; figure 2 - scheme

switching unit; Fig. 3 is a block diagram of registers; FIGS. 4 and 5 are timing charts of the operation of the device.

The device contains digital-analogue converters 1-3, switching unit 4, the first 5 and second 6 registers, the first 7, the second 8 and the third 9

memory blocks, block 0 comparison, trigger 11, third register 12, block

13 registers.

Block 4 of the combo contains the first

14J second 5 and third 16 switches.

The register block 13 contains the fourth 17, fifth 18 and sixth 19 registers, to the information inputs of which chromaticity codes (chromaticity table) of the respective primary colors (k, s, 3 J.) are applied.

The inputs of the device are sync rotate i20, information input 21. And address input -22,

The first 7 and third 9 blocks are intended for storing modifications and outputting a raster image to the display screen synchronously with a television scan.

The first 5 and second 6 registers are intended for storing codes of numbers received from the first 7 and third 9 memory blocks, respectively, and act as buffer registers between the specified memory blocks on one side and switching unit 4 and digital-analog converters 1 -3 on the other.

The third register 12 is intended to store a code of a number defining a chromaticity range on which the color value is recoding. At the same time, information from the first 7 and third 9 memory blocks, the second memory block 9 containing the chromaticity table, is fed to the inputs of digital-to-analog converters 1-3 through the comming unit ACCH1.

632972

The trigger 1 is designed to store the result of comparing the codes of numbers coming from the unit 10 of the comparison. - The second memory block 8 of the color table / is designed to increase the range of reproducible color and color shades by transcoding the information received from the first 10 memory block 7,

The iO comparison block is intended for comparing the codes of numbers received from the third memory block 9 and the third register 12 of the device, and generating If result codes arriving at

trigger 11, Switching unit 4 consists of the first 14, second 15 and third 16 switches and is intended for switching to the inputs of digital-to-20 analogue converters 1-3

information received either from block 13 of registers or from the first 5 and second 6 registers depending on the control signal received 25 from the output of the trigger 11,

The device input 21 is designed to transmit data from a computer to a device and combines the following signals:

DZp is a data bus for recording the difference of 30 times n, where in the general case, the width of the computer;

ZpBP, ZpBP2, ZpBPZ - signals

writing data to the first 7, second 8 and third 9 memory blocks 35;

Zprg - data recording signal in

third register 12 devices.

The device input 22 is intended 40 for receiving control signals from the scanning circuits and combines the following signals:

AHU — address pins in the X and Y coordinates, respectively, 45, which means the row and column addresses in memory blocks 7 and 9; SYNCHRO - input from the clock generator

pulses;

50W - content read signal

blocks 7 and 9 of memory.

The device input 20 is designed to supply gating signals (c) to registers 5 and 6, trigger 11, and block 13 of registers. A specific feature of the formation of the SI is the clearing of the SYNHRO sync series under the action of one of the recording signals, t, e.

SI CHFIXPO + ZpBSh + ZpVP2 +

+ ZPBI 3 + 3 pRgZ,

Reading of blocks 7 and 9 of memory is carried out in the intervals between actions of recording signals, i.e.

Thu ZpBP + ZpBP2 + ZpBPZ +

+. ЗпРгЗ.

The device works as follows

The required contents of memory blocks 7–9 and the third register 12 are formed by computer hardware and software. The timing diagram of the read cycle is shown in FIG. The address input of memory block 8 is labeled AEP2. The sweep circuits through the input 22 form the address AXU's address at the address inputs of memory blocks 7 and 9, with which the content of one memory element is read from the GTI signal via the CH signal from the GTI gate. If it is necessary to modify the image (by modifying the image we mean changing the contents of the memory by writing new data into it), then the address of the modified cell comes from the scanning circuits via input 20. At the same time, a DZp and one of the control signals of the ZpBP, ZPBP 3 recording signal are received from the computer via the 2G input, depending on whether it is modified; what block of memory (7 or 9) is recorded. In the presence of the indicated signals and the SYNCHRO strobe, recording is performed in block 7 or 9 of the memory.

Recording condition

- 3h

t

in)

where - the duration of the recording signal;

- data writing time in memory blocks 7 and 9.

To write data to memory block 8, it is necessary at the output of memory block 7 to obtain in this way the address of the cell being modified, on the DZp bus bus the required contents of this cell and to modify memory block-8 using the signal ЗпБП2. The data is written to the register 12 when the required data is available on the DZp bus, according to the signal of the RRP.

After reading, the codes of the elements of the information field from the memory block 7 are transferred to the register 5, where the records 632974

are transmitted on the falling edge of the signal from input 20, and to memory 8 for transcoding. At the same time, the codes g of the elements of the information field from memory block 9 are fed to register 6, where they are written on the falling edge of the signal from input 20, and to block 10, where they are compared to co-

10 D ° of the number coming from the register

12. The result of the comparison on the falling edge of the signal from the input 20 is written to the trigger 11. If the specified codes of numbers do not match, then block 4 commutator mutates the inputs of the converters 1 to the information from block 13 of registers, otherwise the information from registers 5 and b. The specified actions. are carried out in one regeneration cycle. The timing diagram of the operation of these blocks is shown in Fig.5. It is assumed that the outputs of the third memory block 9 and the register 12 of the device are one-bit.

25 The proposed device in comparison with the known at the same hardware costs allows to significantly increase the number of displayed shades.

30 Let M be the number of bits.

on the image element of the first memory block; N -. the number of bits per image element of the third memory block. If K is the quantity

2g bits for the displayed shade of one of the primary colors of the second memory block 8, the color chart (TC), the number of reproducible color shades with the HELP of the TC will be equal to 40 if the volume of the TC is 2 words. Connecting the third memory block 9 divides the color representation range into -2 zones, in each of which a simultaneous presentation is possible.

45 .2 color shades.

For example, with and the required amount of TC is 256 words. The word length of each word in the TC is equal to the 24th bit - 8 for each

50 is the primary color, which allows for each color to obtain, if necessary, a smooth change in brightness. The total size of the first and third memory blocks 9 allows

4096 colors at the same time

“- t- - -. shades, 256 of which are specified with large. precision color table,

which is sufficient in most cases.

Thus, the proposed device for displaying graphical information on the screen of a color raster display with the same hardware costs as known makes it possible to increase the field of application of such devices by increasing the range of reproducible color shades compared to the previous devices for displaying information.

Claims (1)

Invention Formula A device for displaying graphical information on a color television display screen containing digital-to-analog converters, the outputs of which are video outputs of the device colors, information inputs of digital-to-analog converters are connected to. the outputs of the switching unit, the first and second information inputs of which are connected to the outputs, respectively, of the first and second registers, the control inputs of which are the synchronous input of the device, the information input of the first register connected to the output of the first memory block, connected to the address input of the second block memory info five 0 5 o The data input of which is the information input of the device, connected by the information inputs of the first and third memory blocks, the address inputs of which are the address input of the device, the output of the third memory block is connected to the information input of the second register, characterized in that image by expanding the range of reproducible color shades, the device contains a comparison unit, a trigger, a third register and a register unit, the information input of which is connected to the output of the second memory unit, the output of the register unit is connected to the third information input of the switching unit, the control input of which is connected to the trigger output, the gate input of which is connected to the synchronous input of the device connected to the control input of the register unit, the information input of the trigger is connected to the output of the comparison unit, the first input of which is connected to the output of the third memory block, and the second input to the output of the third register, the information input of which is connected to the information input of the device. Fi.Z  nj ijhjTJjTj 3nBnii3J ZPBP2 J one J one on Jtjl ZZ-ZZZZIX J J git rUTT . FIG. If CM20 W / 5 / RGZ (121. Z 5KM C nOKQl with pssucmpoSSuS FIG. five VNIIPI Order 6368/45 Circulation 433 Subscription Proizn-polygr. pr-tie, Uzhgorod, st. Project, 4