KR970057687A - Memory device of PDP TV - Google Patents

Memory device of PDP TV Download PDF

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Publication number
KR970057687A
KR970057687A KR1019950060949A KR19950060949A KR970057687A KR 970057687 A KR970057687 A KR 970057687A KR 1019950060949 A KR1019950060949 A KR 1019950060949A KR 19950060949 A KR19950060949 A KR 19950060949A KR 970057687 A KR970057687 A KR 970057687A
Authority
KR
South Korea
Prior art keywords
image data
signal
pdp
control pulse
generating
Prior art date
Application number
KR1019950060949A
Other languages
Korean (ko)
Other versions
KR100213296B1 (en
Inventor
박원정
Original Assignee
배순훈
대우전자 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 배순훈, 대우전자 주식회사 filed Critical 배순훈
Priority to KR1019950060949A priority Critical patent/KR100213296B1/en
Publication of KR970057687A publication Critical patent/KR970057687A/en
Application granted granted Critical
Publication of KR100213296B1 publication Critical patent/KR100213296B1/en

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/907—Television signal recording using static stores, e.g. storage tubes or semiconductor memories
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/28—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using luminous gas-discharge panels, e.g. plasma panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Plasma & Fusion (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Control Of Gas Discharge Display Tubes (AREA)
  • Transforming Electric Information Into Light Information (AREA)

Abstract

본 발명은 피디피 티브이(PDP TV)의 메모리 장치에 관한 것으로,제어펄스 발생부로부터의 S2신호에 의거하여 A/D변환부를 통해 디지탈로 변환된 영상데이타가 8비트 단위로 1시프트 레지스터 또는 제2시프트 레지스터에 병렬로 입력되고,클럭에 의거하여 한 비트씩 출력된 다음,제어펄스 발생부로부터의 S1신호와 S2신호에 의거하여 제1선택부를 통해 제1프레임 메모리 또는 제2프레임 메모리에 선택적으로 기록된다.그 다음,제1프레임 메모리 또는 제2프레임 메모리에 선택적으로 기록된다.그 다음,제1프레임 메모리 또는 제2프레임 메모리에 한 프레임 용량의 영상데이타가 기록되면,다른 프레임 메모리에 저장된 영상데이타가 제어펄스 발생부로부터의 S1신호에 의거하여 PDP TV의 구동회로로 선택적으로 제공되므로써,시프트 레지스터를 통해 영상데이타의 재배열을 수행하는 동시에,두 개의 프레임 메모리를 이용하여 PDP TV로 디스플레이되는 영상데이타의 순차주사 방식을 간단하게 처리할 수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device of a PDP TV, in which image data converted into digital through an A / D converter based on an S2 signal from a control pulse generator is converted into one shift register or second in 8-bit units. Input in parallel to the shift register, and output bit by bit based on the clock, and then selectively into the first frame memory or the second frame memory through the first selector based on the S1 and S2 signals from the control pulse generator; Then, it is selectively recorded in the first frame memory or the second frame memory. Then, when image data of one frame capacity is recorded in the first frame memory or the second frame memory, the image stored in the other frame memory The data is selectively provided to the drive circuit of the PDP TV based on the S1 signal from the control pulse generator so that the image data can be transferred through the shift register. While rearranging, two frame memories can be used to easily process sequential scanning of image data displayed on a PDP TV.

Description

피디피 티브이(PDP TV)의 메모리 장치Memory device of PDP TV

본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음Since this is an open matter, no full text was included.

제1도는 본 발명의 바람직한 실시예에 따른 PDP TV의 메모리 장치에 대한 개략적인 블럭구성도 ,1 is a schematic block diagram of a memory device of a PDP TV according to an exemplary embodiment of the present invention.

제2도는 제1도의 제어펄스 발생부로부터 발생되는 S1신호를 설명하기 위한 도면,2 is a view for explaining the S1 signal generated from the control pulse generator of FIG.

제3도는 제1도의 제어펄스 발생부로부터 발생되는 S2신호를 설명하기 위한 도면.3 is a view for explaining the S2 signal generated from the control pulse generator of FIG.

Claims (1)

영상데이타를 저장한 다음 PDP TV로 제공하는 메모리 장치에 있어서,상기 영상데이타 중에 포함된 수평도기신호와 수직동기신호 및 외부로부터 제공되는 클럭에 의거하여 S1신호와 S2신호를 발생하기 위한 제어펄스 발생수단(110); 상기 아날로그의 영상데이타를 디지탈의 영상데이타로 변환하기 위한 A/D변환수단(120); 상기 제어펄스 발생수단(110)으로부터의 S2신호에 의거하여 상기 A/D변환수단(120)을 통해 디지탈로 변환된 영상데이타를 8 비트씩 병렬로 입력한 다음 상기 클럭에 의거하여 한 비트씩 직렬로 제공하기 위한 복수개의 시프트 레지스터(130,140); 상기 제어펄스 발생수단(110)으로부터 제공되는 S1신호와 S2신호에 의거하여 상기 복수개의 시프트 레지스터(130,140)로부터 제공되는 영상데이타를 선택적으로 스위칭하기 위한 제1스위칭수단(150);상기 제어펄스 발생수단(110)으로부터의 S1신호에 의거하여 상기 제1스위칭수단(150)을 통해 제공되는 영상데이타의 기록 및 판독 어드레스를 발생하는 어드레스 발생수단 (155);상기 어드레스 발생수단(155)으로부터 제공되는 기록 및 판독 어드레스에 의거하여 상기 제1스위칭수단(150)을 통해 제공되는 영상데이타를 상기 기록 어드레스에 상응하여 기록하고,상기 판독 어드레스에 기록된 영상데이타를 판독하는 복수개의 프레임 메모리(160,170);상기 제어펄스 발생수단(110)으로부터 제공되는 S1신호에 의거하여 상기 복수개의 프레임 메모리(160,170)에서 판독되어 제공되는 영상데이타를 상기 PDP TV로 선택적으로 제공하기 위한 제2선택 수단(180)으로 구성된 것을 특징으로 하는 피디피 티브이(PDP TV)의 메모리 장치.A memory device for storing image data and then providing the same to a PDP TV, comprising: generating a control pulse for generating an S1 signal and an S2 signal based on a horizontal pottery signal and a vertical synchronization signal included in the image data and a clock provided from the outside; Means 110; A / D conversion means (120) for converting the analog image data into digital image data; Based on the S2 signal from the control pulse generating means 110, the image data converted into digital through the A / D conversion means 120 is input in parallel by 8 bits, and then serialized by one bit based on the clock. A plurality of shift registers 130 and 140 for providing; First switching means 150 for selectively switching image data provided from the plurality of shift registers 130 and 140 based on the S1 signal and the S2 signal provided from the control pulse generating means 110; generating the control pulse Address generating means 155 for generating a write and read address of the image data provided through the first switching means 150 based on the S1 signal from the means 110; provided from the address generating means 155 A plurality of frame memories (160, 170) for recording the image data provided through the first switching means (150) corresponding to the write address based on the write and read address, and reading the image data recorded at the read address; The plurality of frame memories 160 and 170 are read based on the S1 signal provided from the control pulse generating means 110. Of the image data to be ball PDP television (PDP TV) according to claim 2 characterized in that consists of the selection means (180) for selectively providing to the PDP TV memory device. ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.※ Note: The disclosure is based on the initial application.
KR1019950060949A 1995-12-28 1995-12-28 Memory in plasma display panel television KR100213296B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950060949A KR100213296B1 (en) 1995-12-28 1995-12-28 Memory in plasma display panel television

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Application Number Priority Date Filing Date Title
KR1019950060949A KR100213296B1 (en) 1995-12-28 1995-12-28 Memory in plasma display panel television

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KR970057687A true KR970057687A (en) 1997-07-31
KR100213296B1 KR100213296B1 (en) 1999-08-02

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100377402B1 (en) * 2001-03-10 2003-03-26 삼성에스디아이 주식회사 Address-While-Display driving method using plural frame memories for plasma display panel
KR100403515B1 (en) * 1998-09-30 2003-12-18 주식회사 대우일렉트로닉스 PDTV's data processing circuit
KR100492951B1 (en) * 1997-11-04 2005-10-12 엘지전자 주식회사 A data array circuit of ac pdp display

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100492951B1 (en) * 1997-11-04 2005-10-12 엘지전자 주식회사 A data array circuit of ac pdp display
KR100403515B1 (en) * 1998-09-30 2003-12-18 주식회사 대우일렉트로닉스 PDTV's data processing circuit
KR100377402B1 (en) * 2001-03-10 2003-03-26 삼성에스디아이 주식회사 Address-While-Display driving method using plural frame memories for plasma display panel

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