KR940008712B1 - Ic circuit for driving type in image display device - Google Patents

Abstract

The circuit can perform a regular data processing regardless of input bits to reduce chip size. The circuit comprises: a control circuit (20) generationg internal control signal according to inputs of start pulse signal, clock pulse signal and sample and hold control signal, a shift register (30) shifting binary data, a D/A convertor (10) converting N bits image data to analog data, a sample and hold/OP amp circuit (40) generating LCD unit driving output combined by block units.

Description

Integrated circuit for driving image display device

1 is a block diagram showing an embodiment of an integrated circuit for driving an image display device according to the present invention.

FIG. 2 is a detailed circuit diagram of a sample end hold / OP amplifier circuit in the block diagram of the integrated circuit for driving the image display device of FIG.

3 is a schematic diagram showing an integrated circuit for driving an image display device according to the present invention.

4A to 4I are timing charts according to the respective block diagrams of the integrated circuit for driving the video display device shown in FIGS.

5 is a block diagram of a conventional integrated circuit for driving a liquid crystal display device,

FIG. 6 is a detailed circuit diagram of the voltage selection switch in the block diagram of the integrated circuit for driving the liquid crystal display of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit for driving a liquid crystal display device for driving an active matrix-type liquid crystal display device, and more particularly, to a digital display of a segment driver in a thin film transistor (TFT) liquid crystal display device. An integrated circuit for driving an image display device for converting a data output into an analog data output to drive a liquid crystal display device in a Tisted Nematic (TN) mode.

In general, a display panel in which a plurality of data lines and scanning lines are arranged in a matrix state and liquid crystals or electroluminescent display cells are arranged at intersections thereof is widely known as an image (or image) display device (hereinafter referred to as an LCD). An integrated circuit for driving an image display device for driving the same is also well known.

5 schematically shows each block of a conventional integrated circuit for driving a liquid crystal display device.

In the liquid crystal display driving integrated circuit including a control circuit 20 to drive the segment driving circuit 80 according to the start pulse STH and the clock pulse CLK, which are external signals as shown in the figure. The segment driving circuit 80 latches the shift register 30 for outputting start synchronization data according to the control signal synchronized by the control circuit 20, the output of the start synchronization data of the shift register, and the latch clock pulse. A data latch circuit 50 for generating and outputting the digital data, an N-bit decoder 60 for decoding the digital data output latched by the data latch circuit, and a digital data output decoded by the N-bit decoder. And a voltage selection switch circuit 70 for generating an LCD drive output in accordance with the gate voltage difference value applied from the gate application voltage terminals V1 -Vn.

In the conventional liquid crystal display driving integrated circuit configured as described above, first, a segment driving circuit composed of a shift register 30, a data latch circuit 50, an N-bit decoder 60, and a voltage selection switch circuit 70 ( In order to drive 80, a control signal output from the control circuit 20 can be applied.

Next, the control circuit 20 generates a synchronized control signal by inputting a start pulse ST and a clock pulse CK, which are external signals of the system. Subsequently, the shift register 30 moves data by one stage for every clock starting from the synchronized start pulse output from the control circuit. In addition, the data shifted in the shift register is latched through the data latch circuit 50, respectively. At this time, when the user wants to display the N-bit data input (2 ⁿ = N) of the data latch circuit in eight gradations, the user inputs three bits of data and inputs four bits of data in the sixteen gradations.

Therefore, N-bit data input to the shift register 30 is output as latched data by 3 bits or 4 bits each time the shifted data is converted to high. Data latched through the data latch circuit 50 is input to the N-bit decoder 60, respectively, and then decoded data is output to the voltage select switch circuit 70.

A process of generating the decoded data to the LCD driving output through the voltage selection switch circuit 70 will be described with reference to FIG.

The voltage selection switch circuit 70 is an output terminal of the N-bit decoder 60 so as to output data corresponding to the number of input bits of the N-bit decoder 60 according to the voltage applied to each transmission gate. ) Is connected and provided. In this case, the gate transfer terminal 71 is connected to the transfer gate consisting of complementary MOS transistors IM4 to IMn, respectively. In the gate common terminal, inverters IN7 to INn are directed from the least significant bit to the most significant bit. ) Is connected.

Further, gate voltage application terminals V1 to Vn are connected to the respective source terminals of the complementary MOS transistors IM4 to IMn, and drain terminals thereof are commonly provided through the LCD driving output terminals S1 to Sn. It is connected to an LCD panel (not shown).

As described above, since the output terminal of the N-bit decoder 60 includes the gate transfer stage 71 corresponding to the number of input bits, only one transfer gate is turned on among the transfer gates according to the gate voltage value applied to each transfer gate. And the remaining transfer gates turn off. Subsequently, the gate voltages of the gate voltage application terminals V1 to Vn are output as one selected driving voltage through the turned-on transfer gate. Therefore, since the gate voltage is input through the driving output terminal of the LCD device, the display panel is sequentially driven by selecting columns and rows of the LCD device.

The conventional video display device integrated circuit configured and operated as described above is transmitted to the N-bit decoder as the number of batts increases to 16 gradations, 32 gradations, and 64 gradations when the shifted data is latched through the shifted data latch circuit. The gate count increases by the number of data inputs (2 ⁿ = N). In addition, as data input pads are increased, the chip size increases when the circuit for driving the image display device is integrated. As a result, the system itself becomes very complicated when the number of bits increases to 64 gradations or more. There are various problems that make this impossible.

Therefore, in order to solve the above-mentioned conventional problems, the object of the present invention is to operate the display panel of the LCD device satisfactorily by processing the data amount regardless of the number of input bits even when the number of input bits increases to 2 ⁿ = N. The present invention provides a driving circuit for a video display device employing a sample end hold / OP amplifier circuit.

Another object of the present invention is to reduce the chip size and improve yield and reliability, respectively, by one-chip the conventional data latch circuit, the N-bit decoder, and the voltage selector switch circuit itself. An integrated circuit for driving a display device is provided.

An integrated circuit for driving an image display device according to the present invention for achieving the above object includes a control circuit for generating an internal control signal in response to input of a start pulse signal, a clock pulse signal, and a sample and hold control signal; A shift raster for shifting the binary data information stored in the memory to the right or the left by inputting an internal control signal and a synchronous clock pulse of the control circuit; A D / A converter for performing data conversion by inputting N-bit bitio data; And driving a combined LCD unit in block units by inputting the synchronous sample end hold control signal in the control circuit, the shift output signal in the shift register, and the data-converted N-bit data signals in the D / A converter. And a sample end hold / OP amplifier circuit for generating an output.

In addition, the integrated circuit for driving an image display device according to the present invention is connected in parallel to a row driving circuit of N gates and a column driving circuit of M gates for selecting individual array elements in an LCD panel device arranged in a matrix form. And a synchronous control circuit for applying a synchronous control signal and a clock pulse signal to each of the row and column drive circuits.

Hereinafter, an embodiment according to the present invention will be described in detail with reference to the accompanying drawings.

Example 1

FIG. 1 shows an embodiment of an image display device driving circuit according to the present invention, which is a start pulse signal STH, a clock pulse signal CLK, and a sample end hold control signal S & H CNTL, which are external signals of the system. Control circuit 20 for generating a control signal synchronized with the shift register, a shift register 30 for outputting shift synchronization data in accordance with the control signal synchronized with the control circuit, an output signal of the shift register and the control circuit. The sample end hold / OP amplifier circuit 40 for generating the drive output of the LCD device according to the same control signal applied thereto, and converts the N-bit digital data signal into an analog data signal to the sample end hold / OP amplifier circuit. And a D / A converter 10 for application.

Referring to the accompanying drawings, FIG. 2 shows a sample end hold / OP amplifier circuit 40 in a block diagram of an integrated circuit for driving an image display device, in which inverters IN4 and IN5 are bidirectionally connected to gate terminals, respectively. The shift output signal S1 and the sampling control signal to the complementary mode transistors CM1 and CM2 and the gate common terminals of the complementary MOS transistors CM1 and CM2 that are commonly connected to each other to perform a switching mode operation. The capacitors C1 and C2 pass through the NOR gates NOR1 and NOR2 including the inverters IN1 to IN3 for applying the SP as a logic signal, and the hold control signal HD. Complementary mode transistors CM3 and CM4 for holding a sampled signal, an inverter IN6 for applying a hold control signal HD to the unidirectional gate terminal of the complementary MOS transistor, and The shift output signal, the sampling control signal and the hold control And an op amp circuit (OP) for holding the sampling time (for 1H) according to the call value and buffering and amplifying the sampled video data signal to output to the drive output terminals D1 to DN of each LCD device. have. At this time, the sample end hold / OP amplifier circuit 40 is sequentially composed of n stages of sample end hold / OP amplifier circuits 41 suitable for the number of n bits.

Referring to Figure 4 according to the configuration as described above will be described in detail the operation. The horizontal synchronization signal STH, the vertical synchronization signal STV, the clock pulse signals CLK1 and CLK2, and the sample end hold control signals S & H CNTL are input from the control circuit 20, and these signals are synchronized with each other. In each block of the control circuit so as to be combined bitwise (see FIGS. 4A to 4D). Here, when the horizontal synchronization signal STH is input to the shift register 30 to turn on the first transfer gate during the horizontal synchronization clock signal ST1, the input data is clocked every time according to (CLK1) to the first clock pulse. The first shift output S1, the second shift output S2, and the third shift output S3 are shifted by one stage for each CP1. And the like (see Figs. 4E and 4F). At this time, the shift output is converted into analog data by inputting the video data (R, G, B) of n bits to the D / A converter every time it becomes 'high' (refer to FIG. 4 (g)). .

In this case, when the sample signal is 'low' and the shift output signal is 'high', the outputs of the NOR gates NOR1 and NOR2 become 'high' so that n-bit video data is input to the transmission gate terminal and a complementary MOS transistor ( CM1 and CM2) are stored in one of the complementary mode transistors according to the switching mode operation order.

Therefore, the video data of one horizontal synchronization period is sequentially stored in the MOS transistor. Next, when the vertical synchronizing signal STV is input to the shift register 30, the second clock pulse during the one period pulse ST2 of the vertical synchronizing signal STV when the hold signal HD is inverted from high to low level. Since it is synchronized with the clock pulse (CP2) of CLK2), the video data stored in the MOS transistor is input to the OP amplifier circuit (OP) according to the charging voltages of the capacitors (C1) and (C2) and buffered and amplified, and then the LCD drive output terminal (D1). ) (See FIGS. 4 (c), (d) to 4 (g), (i)).

Subsequently, when the next data is shifted in the shift register 30 and the second transfer gate T2 is turned on, the video data R, G, and B are stored in another morph transistor and the OP is operated in the same manner as described above. The amplifier circuit outputs the n LCD drive output terminals D1 to Dn.

In the LCD driving output stages, a sample end hold / OP amplifier circuit 41 having n LCD driving output stages D1 to Dn may be sequentially daisy-chained according to a user's request.

Example 1

FIG. 3 shows a schematic schematic diagram of an integrated circuit for driving an image display device, which selects individual array elements of the panel device 400 (for example, TFT, TN mode LCD panel, etc.) arranged in a matrix form. The row drive circuit 300 of the N gates G1 to Gn and the column drive circuit 100 of the M gates D1 to Dm are connected in parallel to each of the row drive circuits and the column drive circuits. A synchronous control circuit 200 for applying the synchronous control signals STH, STV, and clock pulse signals CLK1, CLK2 is included.

According to the above configuration, when the vertical synchronous signal Vp is applied to the synchronous control circuit 200, the start vertical synchronous signal STV and the synchronized first clock pulse CLK1 are applied to the row driving circuit 300. Is approved. Therefore, the row driving circuit 300 selects the rows G1 to Gn serving as predetermined gates according to the first shift output value and the selected voltage value.

Next, when the horizontal synchronizing signal HP is applied to the synchronous control circuit 200, the column driving circuit 100 includes the start horizontal synchronizing signal STH, the second clock pulse CLK2, and the sample end hold control signal S &. H CNTL) is applied. Therefore, the column driving circuit 100 selects columns D1 to Dn serving as predetermined gates according to the second shift output value S2 and the selected voltage value.

As such, when each row and column is selected by the row and column driving circuits, the n-bit video data R, G, and B are driven by the panel apparatus 400 arranged in a matrix form and output as analog data.

The application system according to the second embodiment described above is not limited to the operation of the LCD panel, but is applied to a TFT type active matrix or a liquid crystal TV connected to a Lap Top, so that various modulation variations can be made without departing from the technical spirit. Is possible.

Therefore, the integrated circuit for driving an image display device according to the present invention has the advantage of being able to drive various LCD panel devices simply and easily because the segment driving circuit employing the sample end hold / OP amplifier circuit can be integrated.

Claims (6)

A control circuit for generating an internal control signal in response to input of a start pulse signal, a clock pulse signal, and a sample end hold control signal; A shift register configured to shift the binary data information stored in the memory to the right or the left by inputting an internal control signal and a synchronous clock pulse of the control circuit; A D / A converter for performing data conversion by inputting N-bit image data; And a drive output of the LCD device combined in units of blocks by inputting the sample end hold control signal synchronized in the control circuit, the output signal shifted in the shift register, and the N-bit data signals data converted in the D / A converter. An integrated circuit for driving an image display device, comprising: a sample end hold / OP amplifier circuit for generating one chip. The complementary MOS transistor of claim 1, wherein the sample end hold / OP amplifier circuit comprises at least one inverter connected to the gate terminal in common in both directions to perform a switching mode operation, and a gate common residue of the complementary MOS transistor. Two NOR gates including at least one inverter for applying the shift output signal and the sampling control signal to the logicized signal, and a complementary type for holding the sampled signals passed through the two capacitors according to the hold control signal. MOS transistors, other inverters for applying the hold control signal to the complementary MOS transistors, respectively, to the one-way gate terminal, and sampling the image voltage value according to the shift output signal, the sampling control signal, and the hold control signal. Time-hold and buffer amplify sampled video data signals Over a plurality of OP amplifier circuit that outputs the LCD driving output and the video display device driving integrated circuit, characterized in that comprises a. The n-stage sample end hold / OP amplifier circuit according to claim 2, wherein the n-stage sample end hold / OP amplifier circuit is sequentially adapted to the number of n bits, and the n-stage sample end hold / OP amplifier circuit is sequentially adapted to the number of n bits. An integrated circuit for driving a video display device, characterized by a daisy chain structure. A control circuit for generating a control signal synchronized with a start pulse signal, a clock pulse signal, and a sample end hold control signal that are external signals of the system; a shift register for outputting start synchronization data according to the synchronized control signal of the control circuit; A sample end hold / OP amplifier circuit for generating a drive output of the LCD device according to the output signal of the shift register and the same control signal of the control circuit; and N bit image data in the sample end hold / OP amplifier circuit. And a D / A converter (10) for applying a signal. A row drive circuit of N gates and a column drive circuit of M gates are connected in parallel to an LCD panel device arranged in a matrix form, and a synchronous control signal is provided to each of the row and column drive circuits. And a synchronous control circuit for applying a clock pulse signal to the video display device driving integrated circuit. 6. The integrated circuit for driving a video display device according to claim 5, wherein the column driving circuit is highly integrated with a sample end hold / OP amplifier circuit and outputs N bits of synchronized video data.