KR100213296B1 - Memory in plasma display panel television - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device of a PDP TV, wherein image data, which is digitally transformed through an A / D converter based on an S2 signal from a control pulse generator, is first shifted or first in 8-bit units. Input in parallel to the 2 shift registers, and output one bit at a time based on a clock, and then selectively to the first frame memory or the second frame memory through the first selector based on the S1 and S2 signals from the control pulse generator. Is recorded. Then, when image data of one frame capacity is recorded in the first frame memory or the second frame memory, the image data stored in the other frame memory is selectively sent to the driving circuit of the PDP TV based on the S1 signal from the control pulse generator. By providing the rearrangement of the image data through the shift register, it is possible to easily process the sequential scanning method of the image data displayed on the PDP TV using two frame memories.

Description

Memory device of PDP TV

1 is a schematic block diagram of a memory device of a PDP TV according to a preferred embodiment of the present invention.

2 is a diagram for generating an S1 signal generated from the control pulse generator of FIG. 1;

3 is a view for explaining the S2 signal generated from the control pulse generator of FIG.

4 is a view for explaining the operation of the shift register of FIG.

* Explanation of symbols for main parts of the drawings

110: control pulse generator 120: A / D converter

130, 140: shift register 150, 180: selection unit

155: address generator 160, 170: frame memory

The present invention relates to a PDP TV (PLASMA DISPLAY PANEL TELEVISION, hereinafter abbreviated as PDP TV), and more specifically, to a PDP TV to store image data in two frame memories and then selectively provide the PDP TV ( PDP TV).

Among the various display devices that are applied to various fields, cathode ray tubes (CATHODE PAY TUBE) (hereinafter abbreviated as CRT) that can display clearly and colorize, are simple to operate, and have low manufacturing cost are used. However, the CRT is large in size because it has a structure of a Frasco (FRASCO) type, requires a high operating voltage of approximately 10,000 V, and has a big disadvantage that display distortion occurs.

Therefore, there is a strong demand for the emergence of a display device that can replace the CRT, and a study on a so-called flat display device having a large display area and a small volume has been continuously studied in many fields related thereto.

On the other hand, the flat display device as described above includes active elements such as ELECTRO LUMINESCENCE, LIGHT EMITTING DIODE, PDP, and other liquid crystal display, ELECTRO CHROMIC DISPLAY) and the like, and the present invention relates to a display device using a PDP which is substantially one of the active elements.

For reference, as an advantage of the above-described PDP display device, there is a memory function that continues discharge when the input pulse is input once, and since the display point is defined by the matrix structure, there is no distortion of the light and the emission frequency is 50-100 kHz. Because it is high, there is no flicker. In addition, the PDP has a single-sided structure, which is advantageous for miniaturization, and because it uses a material that reduces the extinguishing caused by discharge on the surface of the dielectric layer in contact with the discharge, the life is long, and the panel structure mainly composed of the glass plate projects the semi-fixed information as a slide. It is possible to superimpose on a slide, which is advantageous for simplicity.

On the other hand, in order to display image data on a PDP TV, interlaced image data must be converted to sequential scanning, image data of one field is reconstructed into a plurality of subfields, and then rearranged from the most significant bit to the least significant bit. There is a need to repeatedly read and scan image data with two frame memories to ensure the continuity of the image data.

On the other hand, as described above, the necessity of converting image data to sequential scanning, rearranging, and having two frame memories for display on a PDP TV is known. However, these memory devices have been specifically described. none.

Accordingly, the present invention provides a memory device of a PDP TV that can be rearranged and selectively stored in two frame memories, and then continuously displayed on a PDP TV. The purpose is to provide.

In order to achieve the above object, the present invention provides a memory device for storing image data and then providing the same to a PDP TV, comprising: a S1 signal based on a horizontal synchronous signal and a vertical synchronous signal included in the image data and a clock provided from the outside; And control pulse generating means for generating an S2 signal, A / D conversion means for converting the analog image data into digital image data, and the A / D based on the S2 signal from the control pulse generating means. A plurality of shift registers for inputting the digitally converted image data in parallel by 8 bits through the conversion means and then providing them serially one by one based on the clock; and the S1 signal provided from the control pulse generating means; First selection for selectively switching image data provided from the plurality of shift resists based on an S2 signal; Means, address generating means for generating a write and read address of video data provided through said first selecting means based on the S1 signal from said control pulse generating means, and write and read addresses provided from said address generating means. A plurality of frame memories for recording the image data provided through the first selecting means in correspondence with the recording address, and reading the image data recorded in the read address, and S1 provided from the control pulse generating means. And a second selection means for selectively providing the image data read out from the plurality of frame memories to the PDP TV based on a signal.

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of a memory device of a PDP TV according to an exemplary embodiment of the present invention, which includes a control pulse generator 110 and an A / D converter; Abbreviated as 120, the first sis register 130, the second shift register 140, the first selector 150, the address generator 155, the first frame memory 160, and the second frame memory. And a second selector 180.

In the drawing, the control pulse generator 110 generates the S1 and S2 signals based on the horizontal synchronous signal Hs, the vertical synchronous signal Vs, and the clock CLK separated through the synchronous separation unit, not shown. The A / D converter 120 converts analog video signals into digital video data.

Here, the S1 signal generated from the control pulse generator 110 is based on the frame signal (Fig. 2b) generated based on the vertical synchronization signal (Fig. 2a, Vs) provided from the synchronous separation unit (not shown). The clock is toggled every frame (Fig. 2c), and the S2 signal is toggled every eight times by counting the clocks (CLK, Fig. 3b) in the horizontal synchronization signal (Fig. 3a, Hs) provided from the synchronization separator. It is a pulse (FIG. 3C).

Meanwhile, in FIG. 1, the first shift register 130 inputs digitally converted image data to the A / D converter 120 in parallel based on the S2 signal provided from the control pulse generator 110. Next, the controller outputs one bit in series based on the clock signal CLK and provides it to one end of the first selector 150, and the second shift register 140 is provided from the control pulse generator 110. Based on the signal, the A / D conversion unit 120 inputs the image data converted to the de-emission in parallel and then outputs one bit in series based on the clock (CLK) signal to generate another bit of the first selection unit 150. To the side end.

Specifically, in the parallel input serial output method of the first shift register 130 and the second shift register 140, as shown in FIG. 4, 8-bit data D0 to D7 are based on the S2 signal. Then, it is stored in the shift register and is serially outputted one by one based on the clock CLK (O).

In addition, the first selector 150 outputs the image data one bit from the first shift register 130 and the second shift register 140 based on the S1 and S2 signals provided from the control pulse generator 110. Is selectively provided to the first frame memory 160 or the second frame memory 170, and the address generator 155 writes or reads the image data based on the S1 signal provided from the control pulse generator 155. Addresses are provided to the first frame memory 160 or the second frame memory 170, respectively.

In addition, the first frame memory 160 records the image data provided through the first selector 150 in correspondence with the write address W provided from the address generator 155, and writes an address among the recorded image data. The image data stored in the read address R provided from the generator 155 is extracted and provided to one end of the second selector 180.

In addition, the second frame memory 170 records the image data provided through the first selector 150 in correspondence with the write address W provided from the address generator 155, and among the recorded image data. The image data stored in the read address R provided from the address extracting unit 155 is extracted and provided to the other end to the second selecting unit 180.

Meanwhile, the second selector 180 selectively selects the image data extracted from the first frame memory 160 or the second frame memory 170 based on the S1 signal provided from the control pulse generator 110. Provided as the driving circuit of the PDP TV.

An operation process of the memory device of the PDP TV according to the present invention, which is constituted as described above, will be described in detail with reference to FIG.

First, the S1 signal and the S2 signal are respectively generated from the control pulse generator 110 based on the horizontal synchronization signal Hs, the vertical synchronization signal Vs, and the clock CLK provided from the synchronization separator, not shown. The analog video signal is converted into digital video data by the A / D converter 120.

Next, 8-bit image data converted into digital through the A / D converter 120 is input in parallel to the first shift register 130 based on the S2 signal from the control pulse generator 110, The first frame memory 160 is provided to one end of the first selector 150 in serial bit by bit based on the clock CLK, and is based on the S1 and S2 signals from the control pulse generator 110. The first frame memory 160 is written in the first frame memory 160 corresponding to the write address R provided from the address generator 155.

Then, the next 8-bit image data converted into digital through the A / D converter 120 is input in parallel to the second shift register 140 based on the S2 signal from the control pulse generator 110. Next, the first frame memory 160 is provided to the other input terminal of the first selector 150 serially by one bit based on the clock CLK and based on the S1 signal and the S2 signal from the control pulse generator 110. ) Is written in the first frame memory 160 corresponding to the write address R provided from the address generator 155.

On the other hand, when the capacity of the image data recorded in the first frame merbi 160 becomes one frame, the image data provided in serial by one bit from the first shift register 130 and the second shift register 140 is controlled. On the basis of the S1 signal and the S2 signal from the pulse generator 110, the second frame memory 170 is written to the second frame memory 170 through the first selector 160. The second frame memory 170 is written in correspondence with R).

At the same time, the image data recorded in the first frame memory 160 based on the read address W from the address generator 155 is based on the S1 signal from the control pulse generator 110. Through 180) to the driving circuit of the PDP TV.

On the other hand, when the capacity of the image data recorded in the second frame memory 170 becomes one frame, the image data provided in serial by one bit from the first shift register 130 and the second shift register 140 is controlled. The first frame memory 160 is written to the first frame memory 160 based on the S1 signal and the S2 signal from the pulse generator 110, and at this time, the write address provided from the address generator 155 ( Corresponding to R) is written in the second frame memory 170.

At the same time, the image data recorded in the second frame memory 170 based on the read address W from the address generator 155 is based on the S1 signal from the control pulse generator 110. 180 to the driving circuit of the PDP TV.

As described above, the first shift register 130 or the second image data, which is digitally converted through the A / D converter 120 based on the S2 signal from the control pulse generator 110, in 8-bit units. It is input in parallel to the shift register 140, and outputs bit by bit based on the clock CLK, and then the first selector 150 is controlled based on the S1 signal and the S2 signal from the control pulse generator 110. The data is selectively written in the first frame memory 160 or the second frame memory 170. Then, when image data of one frame capacity is recorded in the first frame memory 160 or the second frame memory 170, the image data stored in the other frame memory is based on the S1 signal from the control pulse generator 110. It is optionally provided as a driving circuit of the PDP TV.

Therefore, according to the present invention, it is possible to easily process the sequential scanning method of the image data displayed on the PDP TV using two frame memories while simultaneously rearranging the image data through the shift register.

Claims (1)

A memory device for storing image data and providing the same to a PDP TV, comprising: generating a control pulse for generating an S1 signal and an S2 signal based on a horizontal synchronous signal and a vertical synchronous signal included in the image data and a clock provided from the outside; Means 110, A / D conversion means 120 for converting the analog image data into digital image data, and the A / D conversion based on the S2 signal from the control pulse generating means 110. A plurality of shift registers 130 and 140 for inputting digitally converted image data in parallel by means of 8 bits and then serially providing bit by bit based on the clock, and the control pulse generating means 110. First selection means 150 for selectively switching image data provided from the plurality of shift registers 130 and 140 based on the S1 and S2 signals provided from Address generation means 155 for generating a write and read address of the image data provided through the first selection means 150 based on the S1 signal from the control pulse generation means 110, and the address generation means; The image data provided through 155 is recorded based on the recording and reading address, and the image data provided through the first selecting means 150 is recorded corresponding to the recording address, and the image data recorded at the reading address is recorded. A plurality of frame memories 160 and 170 for reading a plurality of frames and image data read and provided from the plurality of frame memories 160 and 170 based on the S1 signal provided from the control pulse generating means 110. Memory device of the PDP TV, characterized in that the second selection means for providing (180).