KR100195635B1 - Memory device in a plasma display system - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device of a PDP display device, wherein image data of an odd number converted into digital through an A / D conversion unit is stored in odd registers among a plurality of registers by 8 bits, and then, from a pulse generator. The image data stored in the registers of the horizontal axis selected on the basis of the pulse S2 for the scan of the shifted bit by bit based on the count signal Sc from the subfield counting means, not shown, and addressing from the pulse generator. Bit values having the same weights are sequentially provided to the addressing unit based on the pulse for the memory, wherein the even-numbered image data digitally converted by the A / D converter is sequentially added to the even-numbered registers by 8 bits. The image data stored in the registers of the odd number is provided to the addressing unit, Since the image data stored in the terminals are sequentially provided to the addressing unit, the image data can be stored and addressed using a plurality of registers without a separate controller for memory control, thereby increasing the integration degree for the custom IC. The manufacturing cost will be reduced.

Description

Memory device of PDP display device

1 is a schematic block diagram of a memory device of a PDP display device according to a preferred embodiment of the present invention.

2 is a view for explaining the operation of the image data is stored and retrieved in accordance with the present invention.

3 is a schematic block diagram of a memory device of a PDP display device according to a conventional exemplary method.

* Explanation of symbols for main parts of the drawings

110: A / D converter 120: memory

130: data processing unit 135: registration separation unit

136: first shift register 137: second shift register

138: a plurality of registers 139: third shift register

140: pulse generator 150: sustain unit

160: scan and sustain unit 170: addressing unit

180: PDP

The present invention relates to a PDPMA display device, and more particularly, to a memory device of a PDP display device capable of storing image data using a plurality of registers. .

Among the various display devices that are applied to various fields, cathode ray tubes (CATHODE RAY TUBE; abbreviated as CRT) that can display clearly and colorize, are simple to operate, and have low manufacturing cost are used. However, since the CRT itself has a structure of a Frasco (FRASCO) type, the size is large, requires a high operating voltage of approximately 10,000V, and has a big disadvantage that display distortion occurs.

Therefore, there is a strong demand for the emergence of a display device that can replace the above CRT, and research on a so-called flat display device having a large display area and a small volume has been continuously conducted in many fields related thereto.

On the other hand, the flat display device as described above includes active elements such as ELECTRO LUMINESCENCE, LIGHT EMITTING DIODE, PDP, LIQUID CRYSTAL DISPLAY, ELECTRO CHROMIC, etc. DISPLAY) and the like, and the present invention relates to a display device using a PDP which is substantially one of the active elements.

For reference, the advantages of the above-described PDP display device include a memory function for sustaining discharge when a write pulse is input once, and a display point is defined by a metric structure, so that there is no distortion of the image and the emission frequency is 50-. There is no flicker because it is high at 100kHz. In addition, since the PDP has a planar structure, it is advantageous for miniaturization, and since the material that reduces the extinguishing due to discharge is used on the surface of the dielectric layer in contact with the discharge, the life is long, and the panel structure mainly composed of the glass plate projects semi-fixed information as a slide It is possible to superimpose on a slide, which is advantageous for simplicity.

FIG. 3 is a schematic block diagram of a memory device of a conventional PDP display, which is an A / D conversion unit (abbreviated as A / D conversion unit 110) and a memory 120. ), A data processor 130, a synchronization separator 135, a pulse generator 140, a sustain unit 150, a scan and sustain unit 160, an addressing unit 170, and a PDP 180.

In the drawing, the A / D changer 110 converts analog image data into digital image data based on a sampling clock provided from the outside, and the memory 120 uses the digital image through the A / D converter 110. Save the converted image data.

In addition, the data processor 130 converts the interlaced digital image data stored in the memory 120 into digital image data of the sequential scan method, and collects image data having the same weight (WEIGHT) and collects one sub image. The field is reconfigured and then provided to the addressing unit 170.

On the other hand, the synchronization separator 135 separates the vertical synchronization signal (VERTICAL SYNC; hereinafter referred to as Vsync) included in the image data and provides it to the pulse generator 140, and the pulse generator 140 synchronizes. Using the Vsync provided from the separator 135 generates a pulse for sustain, a pulse for scan and a pulse for addressing, respectively.

In this case, the pulse generator 140 alternately generates a pulse for sustain to the sustain unit 150 and the scan and sustain unit 160.

In FIG. 1, the sustain unit 150 applies a high voltage, for example, 180V to 340V, to the sustain electrode of the PDP 180 based on a pulse for sustain provided from the pulse generator 140, and scans the scan. The sustain unit 160 applies a high voltage to the scan and sustain electrodes of the PDP 180 based on the pulse S1 for the scan provided from the pulse generator 140.

In addition, the scan and sustain unit 160 applies a high voltage to the scan and sustain electrodes based on the pulse S2 for the sustain provided from the pulse generator 140, and the addressing unit 170 may include a pulse generator ( The high voltage is applied to the addressing electrode of the PDP 180 according to the image data provided from the data processor 130 based on the pulse for addressing provided from the 140.

The PDP 180 includes M × N unit cells, and each unit cell includes a sustain electrode, a scan and sustain electrode, and an addressing electrode.

An operation process of a memory device of a conventional typical PD display device including the above-described components will be described with reference to FIG. 3.

First, analog image data is converted into digital image data through the A / D converter 110 and stored in the memory 120, and is processed through the data processor 130.

In detail, the interlaced scanning digital image data is processed into progressive scanning digital image data, and the subfields are reconstructed by the image data having the same weight WEIGHT and provided to the addressing unit 170.

On the other hand, the Vsync included in the analog image data is separated from the sync separator 135 and provided to the pulse generator 140, and from the pulse generator 14 based on Vsync provided from the sync separator 135. Pulses for scanning, pulses for sustaining, and pulses for addressing are respectively generated and provided to the sustaining unit 150, the scan and sustaining unit 160, and the addressing unit 170, respectively.

Then, a high voltage is supplied to the scan electrode of the PDP 180 through the scan and sustain unit 160 based on the pulse for the scan from the pulse generator 140, at which time the address from the pulse generator 140 is addressed. The image data processed through the data processor 130 is addressed to the addressing electrode of the PDP 180 based on the pulse for the PDP 180.

After the above scan and addressing are all performed, a high voltage is supplied to the sustain electrode of the PDP 180 through the sustain unit 150 and the scan and sustain unit 160 based on the pulse for sustaining from the pulse generator 140. This alternate application is applied to sustain all horizontal lines corresponding to one subfield.

However, the memory 120 included in the conventional PDP display device is a DRAM (DYNAMIC RANDOM ACCESS MEMORY), which is expensive and complicated in hardware configuration.

Accordingly, an object of the present invention is to provide a memory device of a PDP display device capable of storing and addressing image data in a plurality of registers.

In order to achieve the above object, the present invention converts an analog video signal transmitted from a broadcasting station into digital through A / D conversion means, and then addresses from pulse generating means based on a vertical synchronous signal separated by synchronous separation means. A memory device of a PDP for addressing a digital video signal based on a pulse for a memory, comprising: a first shift register for selecting horizontal registers among a plurality of registers, and the plurality of registers based on a sampling clock provided from the outside; A second shift register for selecting the registers of the vertical axis among the three registers, and a third shift for selectively addressing the digital video signals stored in the plurality of registers based on a pulse for scanning from the pulse generating means Registers and the first and second shifts A pulse for addressing from the pulse generating means by storing image data provided from the A / D conversion means in a predetermined bit unit in a register selected on the basis of a jitter, and then shifting bit by bit based on a sub fill count signal. According to the present invention, there is provided a memory device of a PDP display device comprising the plurality of registers for sequentially providing bit values having the same weight.

The above and other objects and various advantages of the present invention will become more apparent from the preferred embodiments of the present invention described below with reference to the accompanying drawings by those skilled in the art.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a schematic block diagram of a memory device of a PDP display device according to an exemplary embodiment of the present invention. The A / D converter 110, the sync separator 135, the first shift register 136, The second shift register 137, the plurality of registers 138, the third shift register 139, the pulse generator 140, the sustain unit 150, the scan and sustain unit 160, the addressing unit 170, and It consists of the PDP 180.

Meanwhile, among the components of the memory device of the PDP display device according to the present invention, the A / D converter 110, the synchronization separator 135, the pulse generator 140, the sustainer 150, the scan and sustain The unit 160, the addressing unit 170, and the PDP 180 may include the A / D conversion unit 110, the synchronization separation unit 135, and the pulse generator (A / D conversion unit 110) among the components of the conventional typical PDP display device as described above. 140, the sustain unit 150, the scan and sustain unit 160, the addressing unit 170, and the PDP 180 perform substantially the same functions, and thus descriptions thereof will be omitted to avoid overlapping substrates. do.

Therefore, the memory device of the PDP display device according to the present invention is different from the memory device of the conventional typical PDP display device, the first shift register 136, the second shift register 137, the plurality of registers 138 and As the third shift register 139, the following will focus on the operation of these components.

In FIG. 1, the first shift register 136 selects registers on the horizontal axis among the plurality of registers based on the horizontal synchronization signal Hsync separated through the synchronization separator 135, and the second shift register 137. ) Selects registers on the vertical axis from among a plurality of registers based on a sampling clock provided from the outside.

Then, the plurality of registers 138 are composed of a plurality of 8-bit registers, and as shown in FIG. 2, the A / D to the register selected by the first shift register 136 and the second shift register 137. 8-bit image data D0 and D1 stored in each register based on the pulse S3 for addressing provided from the pulse generator 140 after storing the image data provided from the conversion means in units of 8 bits. The bit value Output having the same weight among, D2,..., And D7 is provided to the addressing unit 170.

At this time, the plurality of registers 138 are shifted one bit at a time based on the count signal Sc provided from the subfield counting means, not shown.

The third shift register 139 selects registers to be addressed from among the plurality of registers based on the pulse S2 for scanning from the pulse generator 140.

An operation process of the memory device of the PDP display device according to the present invention, which is constituted as described above, will be described in detail with reference to FIGS. 1 and 2.

First, analog image data is converted into digital image data through the A / D conversion unit 110, and the horizontal synchronization signal (Hsync) and Vsync included in the analog image data are separated from the synchronization separating unit 135 to Vsync. Is supplied to the pulse generator 140, and the horizontal synchronization signal Hsync is provided to the first shift register 136.

On the other hand, the registers of the vertical axis of the plurality of registers 138 are selected based on the sampling clock 137 from the outside, and the plurality of registers 138 are based on the horizontal synchronization signal Hsync separated by the synchronization separating unit 135. The registers of the horizontal axis are selected and the image data converted into digital by the A / D converter 110 is provided to the registers selected in units of 8 bits.

Specifically, registers S11, S12,..., S1N of the first horizontal axis of the plurality of registers 138 are sequentially selected through the first shift register 136 and the second shift register 137. The image data converted into digital through the / D converter 110 is sequentially stored in the registers S11, S12, ..., S1N of the first horizontal axis by 8 bits.

Then, the registers S31, S32,..., S3N of the third horizontal axis are sequentially selected through the first shift register 136 and the second shift register 137. Image data converted into digital through the 8 bit is sequentially stored in the register (S31, S32, ..., S3N) of the third horizontal axis, and five through the first shift register 136 and the second shift register 137 While the registers S51, S52,..., S5N of the first horizontal axis are sequentially selected, the image data converted into digital data through the A / D converter 110 is registered in the fifth horizontal axis by 8 bits. ..., S5N).

The above-described operation is repeatedly performed from the seventh register to the last radix registers so that the image data of the radix field converted into digital through the A / D conversion unit 110 is the registers of the radix among the plurality of registers. Are stored in.

Next, odd registers are sequentially selected from among the plurality of registers 138 through the third shift register 139 based on the pulse S2 for scanning from the pulse generator 140, and then the addressing unit 170. And then a high voltage is applied to the corresponding addressing electrode of the PDP 180.

Here, the image data stored in the odd registers among the plurality of registers 138 may have bit values having the same weight based on the pulse S3 for addressing from the pulse generator 140. Is provided bit by bit, and the plurality of registers 138 are shifted by one bit as a whole based on the count signal Sc from the subfield counting means, not shown.

Meanwhile, image data stored in odd registers among the plurality of registers 138 is provided to the addressing unit 170, and image data of the even field converted digitally through the A / D conversion unit 110 is stored. Each bit is sequentially provided to the registers of the even number among the plurality of registers 138 through the above-described operation process.

If all of the image data stored in the odd registers among the plurality of registers 138 are provided to the addressing unit 170, the image data stored in the even registers among the plurality of registers 138 is the addressing unit. The image data of the next radix field, which is provided to 170 and digitally converted by the A / D conversion unit 110, is sequentially stored in the registers of the radix by 8 bits.

As described above, both scanning and addressing of the PDP 180 are performed, and then the PDP is sustained through the sustain unit 150 and the scan and sustain unit 160 based on the pulse for sustaining from the pulse generator 140. High voltage is alternately applied to the sustain electrode of 180 to sustain all horizontal lines corresponding to one subfield.

As described above, image data of the radix converted into digital through the A / D conversion unit 110 is stored in the registers of the odd number of the plurality of registers 138 by 8 bits, then from the pulse generator 140 The image data stored in the registers of the horizontal axis selected on the basis of the pulse S2 for scanning are shifted by one bit based on the count signal Sc from the subfield counting means, not shown, from the pulse generator 140. The bit values having the same weight are sequentially provided to the addressing unit 170 based on the pulse for addressing of the digital signal. In this case, the excellent image data, which is digitally converted through the A / D converter 110, is stored in the plurality of registers. 8 bits are sequentially stored in the even-numbered registers during 138, and the image data stored in the odd-numbered registers are all provided to the addressing unit 170, and then stored in the even-numbered registers. Data is provided in sequence to the addressing unit (170).

Therefore, according to the present invention, since image data can be stored and addressed using a plurality of registers without a separate controller for memory control, not only can the integration degree for a custom IC be increased, but the manufacturing cost can be reduced. It can be effected.

Claims (1)

The analog video signal transmitted from the broadcasting station is converted to digital through the A / D conversion means 110, and then addressed from the pulse generating means 140 based on the vertical synchronous signal separated by the synchronous separation means 135. A memory device of a PDP (PDP) for addressing a digital video signal based on a pulse, comprising: a first shift register (136) for selecting registers on a horizontal axis from among a plurality of registers (138); A second shift register (137) for selecting registers of a vertical axis among the plurality of registers (138) based on a sampling clock provided from the outside; A third shift register (139) for selectively addressing the digital video signals stored in the plurality of registers (138) based on the pulses for scanning from the pulse generating means (140); The image data provided from the A / D conversion means 110 is stored in a predetermined bit unit in a register selected based on the first and second shift registers 136 and 137 and then based on a sub-fill count signal. PDDP characterized in that the plurality of registers (138) for sequentially providing a bit value having the same weight based on the pulse for addressing from the pulse generating means 140 while shifting bit by bit Memory device of the display device.