KR100363673B1 - Apparatus and Method of Conversing Video Signal in Plasma Display Panel - Google Patents

Abstract

The present invention relates to an apparatus and method for converting video signals of a plasma display panel to reduce manufacturing costs.

The video signal conversion apparatus of the plasma display panel of the present invention includes a clock generator for generating a clock pulse of a predetermined frequency, a signal processor for generating converted data by recombining input data bit by bit, and a clock pulse input from the clock generator. A frequency multiplier for multiplying the frequency by an integer multiple, a memory controller for generating a column address strobe signal to signal the column address of the memory in synchronization with the multiplied clock pulses, and a column address strobe At least one memory for storing the converted data in synchronization with the signal. The memory may be a dynamic random access memory (DRAM).

According to the present invention, the frequency of the input clock signal is doubled to generate a converted clock signal, and the data is stored in the memory in synchronization with the converted clock signal.

Description

Apparatus and Method of Conversing Video Signal in Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a video signal converting apparatus of a plasma display panel capable of reducing manufacturing costs. The present invention also relates to a video signal conversion method for converting data using a video signal conversion apparatus.

Plasma Display Panel (hereinafter referred to as "PDP") is a display device using visible light generated from a phosphor when ultraviolet light generated by gas discharge excites the phosphor. PDP is thinner and lighter than Cathode Ray Tube (CRT), which has been the mainstay of display means, and has the advantage of being able to realize high-definition large screen. PDP is composed of a plurality of discharge cells arranged in a matrix form, one discharge cell constitutes a pixel of the screen.

1 is a perspective view showing a conventional AC surface discharge PDP.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge type PDP is formed on a scan / sustain electrode 12Y and a common sustain electrode 12Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / sustain electrode 12Y and the common sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 12Y and the common sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

Referring to FIG. 2, a conventional AC surface discharge type PDP driving apparatus includes m / n discharge cells 1 having scan / sustain electrode lines Y1 to Ym, common sustain electrode lines Z1 to Zm, and A PDP 30 arranged in a matrix so as to be connected to the address electrode lines X1 to Xn, a scan / sustain driver 32 for driving the scan / sustain electrode lines Y1 to Ym, and a common sustain; The common sustain driver 34 for driving the electrode lines Z1 to Zm, the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1 and the even-numbered address electrode lines X2. First and second address drivers 36A and 36B for dividing and driving .X4, ..., Xn-2, Xn are provided. The scan / sustain driver 32 sequentially supplies scan pulses and sustain pulses to the scan / sustain electrode lines Y1 to Ym so that the discharge cells 1 are sequentially scanned in line units, and m × n The discharge in each of the four discharge cells 1 is maintained. The common sustain driver 34 supplies a sustain pulse to all of the common sustain electrode lines Z1 to Zm. The first and second address drivers 36A and 36B supply image data to the address electrode lines X1 through Xn in synchronization with the scan pulse. The first address driver 36A supplies image data to the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1, and the second address driver 36B supplies the even-numbered address electrode lines ( Image data is supplied to X2, X4, ..., Xn-2, Xn).

Fig. 3 is a block diagram showing a conventional video signal converter for supplying address data to an address driver.

Referring to FIG. 3, in the conventional video signal converter, first and second synchronous dynamic random accesses for storing data supplied to the address driver 36 in units of frames and supplying the stored data to the address driver 36 are provided. Synchronous Dynamic Random Access Memory (hereinafter referred to as " SDRAM ") 40A and 40B and memory controller 44 for supplying clock pulse and read / write control signals to the first and second SDRAMs 40A and 40B. ), A clock generator 46 for supplying clock pulses to the memory controller 44, and a signal processor for supplying 16 bit data (Input Data Arrangement: IDA) to the first and second SDRAMs 40A and 40B. The clock generator 46 generates a clock pulse of a predetermined frequency and supplies the clock pulse to the memory controller 44. The memory controller 44 supplies write control signals to the first and second SDRAMs 40A and 40B that store 16 bit data IDA, and outputs the stored data. Supply the read control signal to. The memory controller 44 also relays the clock pulses supplied from the clock generator 46 to the first and second SDRAMs 40A and 40B. The signal processor 48 receives 8 bit data from the input line 49 and recombines bit by bit to generate 16 bit data IDA. The first and second SDRAMs 40A and 40B store 16 bit data IDA supplied from the signal processor 48 in synchronization with a clock pulse supplied from the memory controller 44 or store 16 bit data IDA stored therein. Is supplied to the address driver 36.

In detail, the operation of the clock generator 46 generates a clock pulse of a predetermined frequency and outputs the clock pulse to the memory controller 44. The memory controller 44 relays the clock pulses input from the clock generator 46 to the first and second SDRAMs 40A and 40B, and supplies the write control signal to the first SDRAM 40A, and the read control signal. Is supplied to the second SDRAM 40B. Meanwhile, as shown in FIG. 5, the signal processor 48 may output 16 bit data IDA corresponding to D0 of the 16 8 bit data arrays 50 input from the input line 49 to the first and second SDRAMs 40A, 40B). In this case, the first SDRAM 40A receives a clock pulse and a write control signal from the memory controller 44, and receives 16 bit data IDA from the signal processor 48. The first SDRAM 40A receives a clock pulse, a write control signal, and 16 bit data IDA, and stores data at the rising edge of the clock pulse as shown in FIG. 4. That is, the first SDRAM 40A stores 16 bit data IDA in synchronization with a clock pulse. On the other hand, the second SDRAM 40B receives clock pulse and read control signals from the memory controller 44 and receives 16 bit data IDA from the signal processor 48. The second SDRAM 40B receives a clock pulse and a read control signal and outputs the stored 16 bit data to the address driver. In the next address period, the signal processor 48 supplies 16 bit data IDA corresponding to D1 to the first and second SDRAMs 40A and 40B. The first SDRAM 40A receives a clock pulse and a read control signal and outputs the stored 16 bit data to the address driver 36. The second SDRAM 40B receives a clock pulse, a write control signal, and 16 bit data IDA, and stores 16 bit data IDA.

Such PDPs are advantageous for large area and slimming and can provide high definition image quality. However, PDPs are difficult to be popularized due to high manufacturing cost. Higher memory such as SDRAM is pointed out as one of the driving factors for the manufacturing cost. Accordingly, in order to realize the popularization of PDPs more quickly, there is a demand for a method capable of reducing the cost of PDPs.

Accordingly, an object of the present invention is to provide an apparatus and method for converting video signals of a plasma display panel which can reduce manufacturing costs.

1 is a perspective view showing a conventional AC surface discharge PDP.

FIG. 2 is a view showing a driving apparatus of the AC surface discharge type PDP shown in FIG. 1;

3 is a block diagram showing a conventional video signal conversion apparatus.

4 is a waveform diagram illustrating a data storage method of the video signal conversion apparatus shown in FIG. 3.

FIG. 5 is a diagram illustrating input data of a signal processor of FIG. 3; FIG.

6 is a block diagram showing a video signal conversion apparatus of the present invention.

FIG. 7A is a waveform diagram illustrating a process of generating a column address stove signal according to the embodiment of FIG. 6; FIG.

FIG. 7B is a waveform diagram illustrating a data storage method of the video signal conversion apparatus shown in FIG. 6.

<Description of Symbols for Main Parts of Drawings>

1: discharge cell 10: upper substrate

12Y: scan / sustain electrode 12Z: common sustain electrode

14,22 dielectric layer 16: protective film

18: lower substrate 20X: address electrode

24: partition 26: phosphor

30: PDP 32: scan / sustain drive unit

34: common sustain driver 36A: first address driver 36B: second address driver 40A: first SDRAM

40B: Second SDRAM 44,54: Memory controller

46,58: clock generator 48,60: signal processor

49,59: Input line 50: 8-bit data array

52A: first DRAM 52B: second DRAM

56: frequency multiplier

In order to achieve the above object, a clock generator for generating a clock pulse having a predetermined frequency, a signal processor for generating converted data by recombining input data bit by bit, and multiplying the frequency of the clock pulse input from the clock generator by an integer multiple. A frequency controller to generate a column address strobe signal for indicating a column address of a memory in synchronization with the multiplied clock pulse, and a memory controller for generating a column address strobe signal for synchronizing with the multiplied clock pulse. And at least one memory for storing the converted data. The memory of the present invention is a dynamic random access memory (DRAM). It is characterized by multiplying the clock pulse twice.

The video signal conversion method of the plasma display panel according to the present invention comprises the steps of multiplying the frequency to integrally multiply the frequency of the input clock pulse, recombining the input data bit by bit to generate converted data, and synchronizing with the multiplied clock pulse Generating a column address strobe signal for indicating a column address of a memory, and storing the converted data in a memory in synchronization with the column address strobe signal.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 6 to 7B.

Fig. 6 is a block diagram showing a video signal converter of the present invention for supplying address data to an address driver.

Referring to FIG. 6, in the video signal conversion apparatus of the present invention, the data supplied to the address driver 36 is stored in units of frames, and the first and second dynamic random accesses for supplying the stored data to the address driver 36 are provided. Memory (Dynamic Random Access Memory: " DRAM " hereinafter) 52A, 52B, frequency multiplier 56 for doubling the frequency of the clock pulse input from the clock generator 58, and doubled A clock controller converts a clock pulse into a column address strobe (hereinafter referred to as "CAS", column address strobe) signal and is configured as a memory controller 54 for supplying the first and second DRAMs 52A and 52B. Other parts are the same as the conventional video signal converter shown in FIG. That is, a clock generator 58 for generating a clock pulse of a predetermined frequency and a signal processor 60 for supplying 16 bit data IDA to the first and second DRAMs 52A and 52B are provided. The clock generator 58 generates a clock pulse of a predetermined frequency. The frequency multiplier 56 extracts an output of a frequency that is an integer multiple of an input frequency, and doubles the frequency of the clock pulse input to the clock generator 58. The memory controller 54 converts a clock pulse input from the frequency multiplier 56 into a CAS signal and supplies it to the first and second DRAMs 52A and 52B, and supplies read / write signals to the first and second DRAMs 52A. 52B). The signal processor 60 generates 16 bit data IDA by recombining 16 8 bit data arrays supplied from the input line 59. The first and second DRAMs 52A and 52B store 16 bit data IDA input from the signal processor 60 or supply the stored data to the address driver 36.

When the operation thereof is described in detail, clock pulses of a predetermined frequency generated by the clock generator 58 are supplied to the frequency multiplier 56. The frequency multiplier 56 multiplies the frequency of the clock pulse input from the clock generator 58 by 2 times and supplies it to the memory controller 54. The memory controller 54 synchronizes the 16-bit data IDA input from the signal processor 60 with the first and second DRAMs 52A, in synchronization with the rising edge of the clock pulse input from the frequency multiplier 56 as shown in FIG. 7A. Generate a CAS (Column Address Strobe) signal for writing to 52B). The memory controller 54 outputs the generated CAS signal to the DRAM 52, supplies a write control signal to the first DRAM 52A, and supplies a read control signal to the second DRAM 52B. Meanwhile, the signal processor 60 generates 16 bit data IDA by recombining 16 8 bit data inputted from the input line 59 bit by bit and generates 16 bit data IDA. To supply. In this case, the first DRAM 52A receives a CAS signal and a write control signal from the memory controller 54, and receives 16 bit data IDA from the signal processor 60. Thereafter, the first DRAM 52A stores 16 bit data IDA input from the signal processor 60 at the falling edge of the CAS signal as shown in FIG. 7B. That is, the first DRAM 52A stores 16 bit data IDA in synchronization with the CAS signal. On the other hand, the second DRAM 52B receives the read control signal from the memory controller 54 and outputs the stored data to the address driver 36. In the next address period, the first DRAM 52A is transferred from the memory controller 54. The read control signal is input and outputs the stored data to the address driver 36, and the second DRAM 52B receives the write control signal from the memory controller 54 and 16 bit data (IDA) input from the signal processor 60. Save).

As described above, the apparatus and method for converting a video signal of a plasma display panel according to the present invention multiply the frequency of an input clock signal by two times to generate a converted clock signal, and store data in memory in synchronization with the converted clock signal. . As a result, DRAM can be used as a memory.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (9)

A clock generator for generating a clock pulse of a predetermined frequency; A signal processor for reconstructing the input data bit by bit to generate converted data; A frequency multiplier for outputting the frequency of the clock pulse input from the clock generator in an integer multiple, A memory controller for generating a column address strobe signal for notifying a column address of a memory in synchronization with the multiplied clock pulse; And at least one memory for storing the converted data in synchronization with the column address strobe signal. The method of claim 1, And the memory is a dynamic random access memory (DRAM). The method of claim 1, And the signal processor generates 16-bit converted data by recombining 16 data packets each having 8 bits input for each frame. The method of claim 1, And the frequency multiplier multiplies the clock pulses twice. The method of claim 2, And the memory controller supplies a read and write control signal to the random access memory. Multiplying the frequency to integrally multiply the frequency of the input clock pulse; Recombining the input data bit by bit to generate converted data; Generating a column address strobe signal for indicating a column address of a memory in synchronization with the multiplied clock pulse; And storing the converted data in a memory in synchronization with the column address strobe signal. The method of claim 6, And the memory is a dynamic random access memory (DRAM). The method of claim 6, The generating of the converted data comprises converting 16 data packets each having 8 bits inputted per frame to generate 16 bit converted data. The method of claim 6, The multiplying the frequency may include multiplying the clock pulse by a factor of two.