KR100527422B1 - Data Integrate Circuit and the Control Method in Plasma Display Panel - Google Patents

Abstract

The data integrated circuit of the present invention includes a storage medium 701 for receiving and storing data pulse values, a latch 602 for temporarily storing data pulse values output from the storage medium 701, and a power supply at the same time. And a voltage adjusting unit 603 that sequentially charges an appropriate address voltage to be applied to the electrode line, and applies each charging voltage to the corresponding address electrode line according to the data pulse value from the latch 602.

Description

Data integrated circuit and driving method of plasma display panel {Integrate Circuit and the Control Method in Plasma Display Panel}

The present invention relates to a driving apparatus and a driving method of a plasma display panel, and more particularly, to a structure and a driving method of a data integrated circuit used in a plasma display panel.

Plasma Display Panels display images containing characters or graphics by emitting phosphors by 147 nm ultraviolet rays generated upon discharge of inert mixed gases of He + Xe, Ne + Xe and He + Ne + Xe. The plasma display panel is not only thin and large in size, but also greatly improved in image quality due to recent technology development. In particular, the three-electrode AC surface discharge type plasma display panel has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 is a perspective view showing a conventional AC surface discharge plasma display panel.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type plasma display panel includes a scan electrode 12Y and a sustain electrode 12Z formed on an upper substrate 10, and an address formed on a lower substrate 18. An electrode 20X is provided.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 12Y and the sustain electrode 12Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan electrode 12Y and the sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

These discharge cells are arranged in a matrix form as shown in FIG. In FIG. 2, the discharge cells 11 are provided at the intersections of the scan electrode lines Y1 to Ym, the sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn. The scan electrode lines Y1 to Ym are sequentially driven, and the sustain electrode lines Z1 to Zm are commonly driven. The address electrode lines X1 to Xn are driven by being divided into odd-numbered lines and even-numbered lines.

3 is a diagram illustrating the flow of data between the plasma display panel and the data integrated circuit.

A conventional plasma display panel is composed of a block (signal processing block) that changes input image data (spatially aligned data) into subfield mapping data and a block (data alignment block) that sorts the subfield mapping data into temporal data. The data integrated circuit receives the time-aligned data during the scan time and outputs it.

4 is a diagram illustrating a method of driving a conventional data integrated circuit.

Referring to FIG. 4, an address discharge is generated by supplying a scan pulse SP to the scan electrode Y and a data pulse DP to the address electrode X in the addressing period. In general, the logic level control data for outputting the above is received by the main controller of the plasma display panel. The control data is input via the shift register 601 of the data integrated circuit. The input terminal of the shift register 601 is generally six. In addition, 96 output terminals are designed for one data integrated circuit. Thus, six clocks require 96 clocks per scan line for 96 outputs. On the other hand, this operation must continue to operate for the duration of the addressing discharge, and for 16 clocks is the time to be secured for control regardless of the discharge characteristics.

5 is a block diagram of a conventional data integrated circuit.

Referring to FIG. 5, a data integrated circuit used in a conventional plasma display panel includes a shift register 601, a latch 602, and a voltage adjusting unit 603. In this embodiment, six inputs are received for 16 clocks, and each of the six inputs is stored in a shift register and output to 96 outputs at a time. Therefore, the scan time for addressing must be greater than (16 / fsysclk) (fsysclk: system frequency).

However, due to the development of technology, scan time is gradually decreasing, making it difficult to secure this time.

An object of the present invention is to provide a data integrated circuit having a memory device capable of storing and reading one frame data required for subfield driving at one time.

It is another object of the present invention to provide stable operation by storing subfield data necessary for one frame at a time in a memory of a data integrated circuit and taking it out if necessary.

In order to achieve the above object, the data integrated circuit of the present invention includes a storage medium 701 for receiving and storing data pulse values, a latch 602 for temporarily storing data pulse values output from the storage medium 701, and A voltage adjusting unit which sequentially charges an appropriate address voltage to be applied to each address electrode line while applying power, and applies each charging voltage to a corresponding address electrode line according to a data pulse value from the latch 602. 603).

In the present invention, the number of addresses of the storage medium 701 is preferably equal to or half the number of horizontal lines of the plasma display panel.

In the present invention, one address of the storage medium 701 is preferably provided with a storage space of the number of bits in which data pulses can be output at one time.

In order to achieve the above object, according to the present invention, a method of driving a data integrated circuit stores all values corresponding to one frame before the data pulse generated in the addressing step is completed, and extracts the stored signal. And discharging the data pulses.

In the present invention, data values are partially stored in the remaining sections except for the addressing step, and all data pulse values corresponding to the frames are stored before one frame is completed.

In the present invention, it is preferable that data values are partially stored only in a fixed specific section and all data pulse values corresponding to a frame are stored before one frame is completed.

In the present invention, the data value is preferably stored in the entire data pulse value corresponding to each frame before the start of every frame.

Hereinafter, the present invention will be described in more detail with reference to the accompanying drawings.

6 is a block diagram showing the configuration of a data integrated circuit according to an embodiment of the present invention.

In this embodiment, the data integrated circuit includes a storage medium 701, a latch 602, and a voltage adjuster.

The above embodiment shows a state in which data pulse values are stored and moved.

Referring to FIG. 6, one data integrated circuit stores data pulses of one frame of each vertical line before discharging them to the address electrode.

Since the device for storing the data pulse is required for the above process, the data integrated circuit includes a suitable storage medium 701 therein. However, since the data pulse value in one frame is quite large, it is preferable to store the data pulse value using a section other than the addressing step in the subfield. The storage medium 701 may use a variety of devices according to the purpose of the invention, but it is preferable to use a flash memory or RAM already known.

The storage method will be described later with reference to FIG. 7.

The storage space of the storage medium 701 may be variously changed according to the screen size of the plasma display panel.

 For example, assume that there is a plasma display panel in which the video mode is 640x480, is driven by a dual scan method, uses 16 subfields, and one data integrated circuit covers 96 vertical lines.

The storage medium 701 may have an address. The number of addresses may vary depending on the size of the vertical line of the plasma display panel, but in the above embodiment, the addresses have 240 addresses. Addresses are assigned from 0 to N (total number of vertical lines) -1. That is, if the dual mode is used as described above and the number of vertical lines is 480, a total of 240 addresses are required, and the addresses are assigned from 0 to 239.

One of the storage mediums 701 is provided with a storage space corresponding to the total number of output terminals which one data integrated circuit can output. In the above example, since 96 data integrated circuits are capable of outputting, one address is given a space capable of storing 96 bits.

Thus, one data integrated circuit has 240 * 16 * 96 = 368640 bits of storage therein.

However, as long as sufficient input / output terminals of the data integrated circuit can be secured, it is also possible to store data pulses using a general memory. In addition, if high-speed data transfer between the data integrated circuit and the data alignment block is possible, a simple first-in first-out (FIFO) can be used using only two terminals.

7 is a diagram illustrating a method of driving a data integrated circuit according to an exemplary embodiment of the present invention.

In this embodiment, the signal for driving includes a scan pulse, a sustain pulse, and a data pulse.

The above embodiment shows a method of storing data pulses.

In the conventional method, one line of data is loaded into the data integrated circuit within each scan pulse time. Referring to FIG. 7, the present invention enables loading into the data integrated circuit outside the addressing period.

That is, in the present invention, since there was no storage space, the data pulse value was immediately read and used at the time required. However, in the present invention, since the storage medium 701 is included, the data pulse is loaded and stored in the storage medium 701 in addition to the addressing period. It is possible to do

Therefore, the addressing period during which the discharge is sustained in the plasma display panel can be avoided, thereby reducing the malfunction of the panel discharge. 7 discloses a method of storing data in an integrated circuit during a setup period.

However, the data pulse storage operation can be performed in a period during which there is no operation due to a relatively high voltage waveform among other operation periods even if it is not necessarily a setup period.

For example, it is also possible to store and use data pulses corresponding to an entire frame at a time before one frame starts.

Alternatively, one frame data may be divided and stored in a manner of storing in a specific section in each subfield in consideration of the correlation between the loading time and the driving waveform.

Thereafter, when the data pulse is stored in the data integrated circuit, the data pulses are sequentially output by the function of the data integrated circuit, which is already built in, and the data pulses are discharged to the plasma display panel in the same manner as in the related art.

As described above, according to the present invention, by installing the storage medium 701 in the data integrated circuit and using the same, there is an effect of distributing the frame memory function of the conventional plasma display panel control.

In addition, since the required data can be loaded at a time separated from the addressing discharge, a stable operation can be performed.

In addition, it is possible to shorten the input terminal of the data integrated circuit according to the application method.

As a result, the product produced by using the present invention is to improve the added value to improve the merchandise and quality of the product, as well as to have the effect to give reliability and the like.

As described above, although described with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and modified within the scope of the present invention without departing from the spirit and scope of the present invention described in the claims below. It will be appreciated that it can be changed.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a layout view of electrodes of the plasma display panel shown in FIG. 1.

3 is a block diagram illustrating a data flow of a panel and a data integrated circuit.

4 is a diagram illustrating a method of driving a conventional data integrated circuit.

5 is a block diagram of a conventional data integrated circuit.

6 is a block diagram in a data integrated circuit that is an embodiment of the invention.

7 is a diagram illustrating a method of driving a data integrated circuit according to an exemplary embodiment of the present invention.

*** Explanation of the main symbols in the drawings ***

10: upper substrate 12Y: scanning / sustaining electrode

12Z: sustain electrode 14,22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor layer 601: shift register

602: latch 603: voltage adjusting unit

701: storage medium

Claims (8)

One address is provided with a storage space having a number of bits for outputting data pulses at one time. The storage medium 701 receives and stores data pulse values, and the data pulse values output from the storage medium 701. The latch 602 for temporarily storing and the power are applied, and at the same time, an appropriate address voltage to be applied to each address electrode line is sequentially charged, and the respective charging voltages are stored according to the data pulse values from the latch 602. A data integrated circuit of a plasma display panel including a voltage adjusting unit (603) applied to a line. The data integrated circuit of claim 1, wherein the number of addresses of the storage medium (701) is equal to the number of horizontal lines of the plasma display panel. The data integrated circuit of claim 1, wherein the number of addresses of the storage medium (701) is half of the number of horizontal lines of the plasma display panel. delete A reset step of overwriting and discharging the cells to form wall charges; An addressing step of address-discharging specific cells of all of the full-surface write discharge cells to invert the wall charge polarity of the specific cells, and to maintain the wall charge polarity due to the front write discharge in the remaining cells except for the specific cells; A driving method of a plasma display panel comprising a holding step of holding and discharging only certain cells whose wall charge polarities are inverted by a holding pulse. Before the data pulse generated in the addressing step is completed one frame, all values corresponding to one frame is stored, and the data signal is extracted to discharge the data pulse. The method of claim 5, wherein the data values are partially stored in the remaining sections except for the addressing step, and all data pulse values corresponding to the frames are stored before one frame is completed. . The method of claim 5, wherein the data value is partially stored only in a specific specific section, and all data pulse values corresponding to the frame are stored before one frame is completed. The method of driving a plasma display panel according to claim 5, wherein the data value is stored at a time of the entire data pulse value corresponding to each frame before the start of every frame.