KR100433213B1 - Method and apparatus for driving plasma display panel - Google Patents

Abstract

The present invention relates to a method and apparatus for driving a plasma display panel to simplify a driving circuit.

The method and apparatus for driving the plasma display panel continuously supply a DC voltage to the sustain electrode during the address period and the sustain period, and alternately sustain the positive and negative sustain voltages having opposite polarities in the sustain period. Supply to the scan electrode adjacent to the electrode.

Description

TECHNICAL AND APPARATUS FOR DRIVING PLASMA DISPLAY PANEL}

The present invention relates to a plasma display panel, and more particularly to a method and apparatus for driving a plasma display panel to simplify the driving circuit.

Plasma Display Panels (hereinafter referred to as "PDPs") display images containing characters or graphics by emitting phosphors by 147 nm ultraviolet rays generated during discharge of He + Xe or Ne + Xe gas. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development.

The three-electrode AC surface discharge type PDP lowers the voltage required for discharge by using wall charges accumulated on the surface during discharge, and has advantages of low voltage driving and long life because it protects the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a conventional three-electrode AC surface discharge type PDP (hereinafter, referred to as a “three-electrode PDP”) includes a scan electrode Y and a sustain electrode Z formed on an upper substrate 10, and a lower substrate ( And a data electrode X formed on 18).

The scan electrode Y and the sustain electrode Z are formed on the upper substrate 10 side by side, including the wide transparent electrodes 12Y and 12Z and the narrow metal bus electrodes 13Y and 13Z, respectively.

An upper dielectric layer 14 and a passivation layer 16 are stacked on the upper substrate 10 to cover the scan electrode Y and the sustain electrode Z. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The data electrode X is perpendicular to the scan electrode Y and the sustain electrode Z.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18. The phosphor layer 26 is applied to the surfaces of the lower dielectric layer 22 and the partition wall 24. The partition wall 24 separates horizontally adjacent discharge spaces to prevent optical and electrical crosstalk between adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue.

An inert mixed gas such as He + Xe or Ne + Xe is injected into the discharge space provided between the upper substrate 10, the lower substrate 18, and the partition wall 24.

The PDP is driven by dividing one frame into several subfields having different number of emission times in order to realize gray level of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray scale according to the number of discharges. When the image is to be displayed in 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. Each of the eight subfields SF1 to SF8 is divided into a reset period, an address period, and a sustain period. The reset period and the address period of each subfield are the same for each subfield. The address discharge for selecting the cell is caused by the voltage difference between the data electrode X and the scan electrode Y. The sustain period is increased at a rate of 2n (n = 0,1,2,3,4,5,6,7) in each subfield. In this way, the gray scale necessary for displaying an image is realized by adjusting the number of sustain discharges in the sustain period in each subfield. The sustain discharge is caused by a high voltage pulse signal alternately supplied to the scan electrode Y and the sustain electrode Z, as shown in FIG.

Referring to FIG. 2, the PDP is driven by dividing into a setup period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

During the setup period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges and space charges in the cells. Subsequently, a ramp ramp down (Ramp-down) is applied to the scan electrodes (Y). Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain. Here, the rising ramp waveform Ramp-up rises to the positive set-up voltage Vset_up, and the falling ramp waveform Ramp-down falls to the negative set-down voltage -Vy.

In the address period, the negative scan pulse (-SCNP) for decreasing the scan voltage Vsc to the negative set-down voltage (-Vy) is sequentially applied to the scan electrodes Y, and the positive electrode is applied to the data electrodes X. The surname data pulse DP is applied. As the voltage difference between the scan pulse (-SCNP) and the data pulse (DP) and the wall voltage generated during the setup period are added, an address discharge is generated in the cell to which the data pulse (DP) is applied. Wall charges are generated in the cells selected by this address discharge. During the address period, the positive pole DC voltage Vdc is supplied to the sustain electrodes Z in order to prevent erroneous discharge due to the voltage difference from the scan electrode Y.

In the sustain period, a sustain pulse SSUS is applied to the scan electrode Y and the sustain electrode Z alternately. The cell selected by the address discharge has a surface discharge form between the scan electrode (Y) and the sustain electrode (Z) each time the sustain pulse (SUSP) is applied while the voltage difference between the wall voltage and the sustain pulse (SUSP) in the cell is added. This causes a sustain discharge.

The driving circuit for driving the scan electrode Y is integrated into an integrated circuit (hereinafter referred to as a "drive IC"). As shown in FIG. 3, the scan driving IC is supplied with driving voltages (for example, + 5V and -15V), and is set as the driving voltage as the positive set-up voltage Vset_up, the negative set-down voltage (-Vy), and the scan voltage. (Vsc) and the positive sustain voltage Vs are input. The driving voltages having different voltage levels are switched by switching elements integrated in the driving IC and supplied to the k scan electrodes Y1 to Yk. In addition, the driving circuit for driving the sustain electrode Z is composed of switching elements for alternately supplying the sustain voltage Vs. Therefore, the scan driving circuit and the sustain driving circuit have a high manufacturing cost because their configuration is complicated and includes many switching elements. As a result, the manufacturing cost of the conventional PDP is inevitably increased by the scan driving circuit and the sustain driving circuit, and the thickness of the conventional PDP becomes thick due to the volume of the driving ICs.

Accordingly, an object of the present invention is to provide a method and apparatus for driving a PDP to simplify the driving circuit.

1 is a perspective view showing a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a driving waveform diagram for driving the plasma display panel shown in FIG. 1.

FIG. 3 is a diagram illustrating an input voltage of a scan driving integrated circuit for generating the scan driving waveform shown in FIG. 2.

4 is a block diagram schematically illustrating an apparatus for driving a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 5 is a driving waveform diagram of the plasma display panel shown in FIG. 4.

FIG. 6A is a waveform diagram illustrating another example of the ramp waveform illustrated in FIG. 5.

FIG. 6B is a waveform diagram illustrating still another embodiment of the ramp waveform shown in FIG. 5.

7 is a diagram illustrating an input voltage of a scan driving integrated circuit according to the present invention.

<Explanation of symbols for main parts of drawing>

X: Data electrode Y: Scan electrode

Z: sustain electrode 10: upper substrate

12Y, 12Z: transparent electrode 13Y, 13Z: metal bus electrode

14,22 dielectric layer 16: protective film

18: lower substrate 24: bulkhead

26 phosphor 100 plasma display panel

101: data driver 102: scan driver

In order to achieve the above object, the driving method of the PDP according to the present invention comprises the steps of: continuously supplying a DC voltage to the sustain electrode during the address period and the sustain period; And alternately supplying a positive sustain voltage and a negative sustain voltage having opposite polarities to the scan electrode adjacent to the sustain electrode in the sustain period.

The DC voltage is characterized in that any one of 0V and ground voltage (GND).

The driving method of the PDP according to the present invention supplies the rising ramp waveforms up to twice the sustain voltage to the scan electrodes during the set-up period, and then supplies the ramp ramps down to the negative sustain voltage to supply the discharge cells of the full screen. And further comprising initializing.

The rising ramp waveform is characterized by falling to a DC voltage after falling to a predetermined voltage between twice the sustain voltage and the double sustain voltage at twice the sustain voltage.

The falling ramp waveform is characterized by starting to fall at a predetermined voltage between twice the sustain voltage and the direct current voltage and down to the negative sustain voltage.

In the driving method of the PDP according to the present invention, a step of supplying a scan voltage to the scan electrode during the address period, and supplying a scan pulse that falls from the scan voltage to the negative sustain voltage to the scan electrode and at the same time orthogonal to the scan electrode And supplying a data pulse to cause an address discharge.

According to another aspect of the present invention, a PDP driving apparatus includes: a scan driving circuit for alternately supplying a positive sustain voltage and a negative sustain voltage having opposite polarities to a scan electrode during a sustain period; A DC voltage source for continuously supplying a DC voltage to the sustain electrode during the address period and the sustain period is provided.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 7.

Referring to FIG. 4, the driving apparatus of the PDP according to the present invention drives the PDP 100 in which m × n cells 30 are arranged in a matrix, and the scan electrodes Y1 to Ym of the PDP 100. And a data driver 101 for supplying data to the data electrodes X1 to Xn of the PDP 100.

The scan driver 102 scans the rising ramp waveform (Ramp-up), the falling ramp waveform (Ramp-down), scan pulse (-SCNP) and positive / negative sustain pulse (SUSP, -SUSP) as shown in FIG. Supply to the electrodes (Y) sequentially.

As illustrated in FIG. 5, the data driver 101 simultaneously supplies the data pulses DP synchronized with the scan pulse −SCNP to the data electrodes X1 to Xn.

The sustain electrodes Z are commonly connected to a base voltage source (not shown), and an OV or a base voltage GND is applied thereto.

Referring to FIG. 5, the PDP according to the present invention is driven by dividing into a setup period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the setup period, a rising ramp waveform Ramp-up, which rises to twice the sustain voltage 2Vs, is simultaneously applied to all the scan electrodes Y. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges and space charges in the cells. The double sustain voltage 2Vs is set smaller than the conventional setup voltage Vset_up. As a result, the rising time of the rising ramp waveform Ramp-up is smaller than that of the conventional one. In order to generate a double sustain voltage (2Vs), the scan driver 102 has a built-in capacitor for charging and discharging the sustain voltage (Vs) input from the outside. The sustain voltage Vs discharged from the capacitor and the sustain voltage Vs input from the outside are added and supplied to the scan electrodes Y at twice the sustain voltage 2Vs. Following the rising ramp waveform Ramp-up, a falling ramp waveform Ramp-down is applied to the scan electrodes Y, which falls to the negative sustain voltage -Vs. Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain. The negative sustain voltage (-Vs) is set larger than the conventional negative setdown voltage (-Vy). As a result, the falling time when the ramp ramp down to the negative sustain voltage (-Vs) becomes longer than before. Therefore, the set-up period may be longer than that of the falling ramp waveform, but the period of supply of the rising ramp waveform is shortened, which is almost the same as that of the conventional art.

In order to generate the negative sustain voltage (-Vs), the scan driver 102 includes an inverter for inverting the polarity of the sustain voltage Vs input from the outside.

In addition, since the voltage of the falling ramp waveform (Ramp-down) is set to the negative sustain voltage (-Vs) which is larger than the conventional negative set-down voltage (-Vy), the voltage of the rising ramp waveform (Ramp-up) is It can be lowered to twice the sustain voltage (2Vs) than the setup voltage (Vset-up).

The ramp waveform (Ramp-up, Ramp-down) is sustained from the sustain voltage (Vs) twice from the sustain voltage (2Vs) in the rising ramp waveform (Ramp-up) as shown in Figure 6a to prevent the stabilization of the discharge Alternatively, it may be dropped to 0 V or the ground voltage GND after a predetermined time at a time when it is dropped to several tens of V. In addition, as shown in FIG. 6B, the starting point of the ramp ramp down may be set to the sustain voltage Vs or several tens of volts.

In the address period, a negative scan pulse (-SCNP) that lowers the scan voltage Vsc to the negative sustain voltage (-Vs) is sequentially applied to the scan electrodes Y and simultaneously to the data electrodes X. A positive data pulse DP is applied. As the voltage difference between the scan pulse (-SCNP) and the data pulse (DP) and the wall voltage generated during the setup period are added, an address discharge is generated in the cell to which the data pulse (DP) is applied. Wall charges are generated in the cells selected by this address discharge.

In the sustain period, the positive sustain pulse (SUSP) and the negative sustain pulse (-SUSP) are alternately applied to the scan electrodes (Y). The cell selected by the address discharge has a surface discharge form between the scan electrode (Y) and the sustain electrode (Z) each time the sustain pulse (SUSP) is applied while the voltage difference between the wall voltage and the sustain pulse (SUSP) in the cell is added. This causes a sustain discharge.

The sustain electrode Z is continuously supplied with a DC voltage of 0 V or the ground voltage GND during the setup period, the address period and the sustain period.

In the scan driving IC according to the present invention, as shown in FIG. 7, a driving voltage (for example, + 5V and -15V) is supplied, and a scan voltage Vsc and a sustain voltage Vs are input as a driving voltage. The scan driving IC supplies only the driving waveforms necessary for the setup period, the address period and the sustain period to the k scan electrodes Y1 to Yk using only the scan voltage Vsc and the sustain voltage Vs. Since the number of input voltages is reduced in this way, the scan driver IC can reduce the number of internal switching elements, thereby simplifying the circuit. In particular, since only 0 V or the ground voltage GND is continuously supplied to the sustain electrode Z, a separate driving circuit is not required.

As described above, in the method and apparatus for driving a PDP according to the present invention, since the voltage supplied to the scan electrode is reduced to the scan voltage Vsc and the sustain voltage Vs, the driving circuit is simplified and, of course, 0 V or the sustain electrode. Since only the ground voltage GND is supplied, a circuit for driving the sustain electrode becomes unnecessary. Therefore, the driving circuit and method for driving the PDP according to the present invention are simplified. Furthermore, the PDP becomes thin due to the simplification of the driving circuit.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (13)

A plasma display panel driven by dividing into a setup period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell, Continuously supplying a DC voltage to the sustain electrode during the address period and the sustain period; And alternately supplying a positive sustain voltage and a negative sustain voltage having opposite polarities to the scan electrode adjacent to the sustain electrode during the sustain period. Way. The method of claim 1, And the DC voltage is any one of 0V and ground voltage (GND). The method of claim 1, During the set-up period, after supplying the rising ramp waveform rising to twice the sustain voltage to the scan electrode, supplying the falling ramp waveform falling to the negative sustain voltage and initializing the discharge cells of the full screen. Method of driving a plasma display panel comprising a. The method of claim 3, wherein And the rising ramp waveform is lowered to the DC voltage after the voltage is lowered from the double sustain voltage to a predetermined voltage between the double sustain voltage and the direct current voltage. The method of claim 3, wherein And wherein the falling ramp waveform starts to fall at a predetermined voltage between the double sustain voltage and the direct current voltage and falls to the negative sustain voltage. The method of claim 1, Supplying a scan voltage to the scan electrode during the address period; And supplying a scan pulse that falls from the scan voltage to the negative sustain voltage to the scan electrode and supplying a data pulse to a data electrode orthogonal to the scan electrode to cause an address discharge. A method of driving a plasma display panel. The method of claim 1, And the DC voltage is supplied to the sustain electrode during the setup period. A plasma display panel driven by dividing into a setup period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell, A scan driving circuit for alternately supplying a positive sustain voltage and a negative sustain voltage having opposite polarities to the scan electrodes during the sustain period; And a direct current voltage source for continuously supplying a direct current voltage to the sustain electrodes during the address period and the sustain period. The method of claim 8, And the DC voltage is any one of 0V and ground voltage (GND). The method of claim 8, During the set-up period, the scan driving circuit supplies a rising ramp waveform that rises to twice the sustain voltage to the scan electrode, and then a falling ramp waveform that falls to the negative sustain voltage to supply the discharge cells of the full screen. A drive device for a plasma display panel characterized by initializing. The method of claim 8, During the address period, the scan driving circuit supplies a scan voltage to the scan electrode, and supplies a scan pulse to the scan electrode that falls from the scan voltage to the negative sustain voltage. Device. The method of claim 11, And a data driving circuit for supplying a data pulse synchronized with the scan pulse to a data electrode orthogonal to the scan electrode. The method of claim 8, And the DC voltage source supplies the DC voltage to the sustain electrode during the setup period.