KR100330033B1 - Method for Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a driving method of a plasma display panel which enables high speed driving.

In the method of driving the plasma display panel of the present invention, surface discharge occurs between the scan / maintenance electrode and the common sustain electrode which are formed side by side on the first substrate in all the discharge cells, and simultaneously on the common sustain electrode and the second substrate. A priming discharge step of causing opposite discharges between the formed address electrodes to form wall charges having a first polarity at the scan / hold electrode and the address electrode, and wall charges having a second polarity at the common sustain electrode; A relatively short erase discharge is generated between the common sustain electrode and the address electrode, so that wall charges formed on the common sustain electrode and the address electrode are erased, so that a relatively small amount of wall charges whose polarities are reversed remain and the scan / hold electrode The wall charge formed in the device is characterized in that it comprises a reset step including an erase discharge step to increase the polarity without polarity inversion.

According to the present invention, high-speed addressing is possible because the scanning pulse can be shortened by forming a priming discharge including a surface discharge and a counter discharge in the reset period, and an erase discharge to generate a wall charge to assist subsequent address discharge. Done.

Description

Method for Driving Plasma Display Panel {Method for Driving Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving a plasma display panel, and more particularly, to a method for driving a plasma display panel that enables high speed driving.

Recently, a plasma display panel (hereinafter referred to as a 'PDP'), which is easy to manufacture a large panel, has attracted attention as a flat panel display device. As a PDP, a three-electrode AC surface discharge type PDP having three electrodes and driven by an alternating voltage is typical.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge type PDP is formed on a scan / hold electrode 12Y and a common sustain electrode 12Z formed on an upper substrate 10, and a lower substrate 18. An address electrode 20X is provided. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan / suspension electrode 12Y and the common sustain electrode 12Z side by side. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 14. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan / sustain electrode 12Y and the common sustain electrode 12Z. The partition wall 24 is formed in parallel with the address electrode 20 to prevent the ultraviolet rays and the visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower plates and the partition wall.

These discharge cells are arranged in the form of a matrix as shown in FIG. In FIG. 2, the discharge cells 1 are provided at the intersections of the scan / sustain electrode lines Y1 to Ym, the common sustain electrode lines Z1 to Zm, and the address electrode lines X1 to Xn. The scan / hold electrode lines Y1 to Ym are sequentially driven, and the common sustain electrode lines Z1 to Zm are commonly driven. The address electrode lines X1 to Xn are driven by being divided into odd-numbered lines and even-numbered lines.

The three-electrode AC surface discharge type PDP is driven by being divided into a plurality of subfields, and gray scale display is performed by emitting light a number of times proportional to the weight of video data in each subfield period. For example, when an image is displayed in 256 gray scales using 8-bit video data, one frame display period (for example, 1/60 second = about 16.7 msec) in each discharge cell 1 is shown in FIG. As shown in the figure, the data is divided into eight subfields SF1 to SF8. Each subfield SF1 to SF8 is further divided into a reset period, an address period, and a sustain period, and 1: 2: 4: 8:... The weight is given at the ratio of 128. Here, the reset period is a period for initializing the discharge cells, the address period is a period during which selective address discharge occurs according to the logic value of the video data, and the sustain period is such that discharge is maintained in the discharge cells in which the address discharge has occurred. It is a period. The reset period and the address period are equally assigned to each subfield period.

4, a driving waveform diagram supplied to the PDP shown in FIG. 2 during an arbitrary subfield period is shown according to the conventional PDP driving method. First, in the reset period, the supply pulses RPy and RPz are commonly supplied to the scan / hold electrode lines Y1 to Ym and the common sustain electrode lines Z1 to Zm to generate discharge in all discharge cells. All discharge cells are initialized. Following the reset period, in the address period, the scan pulse SP is sequentially supplied to the scan / sustain electrode lines Y1 to Ym, and the data pulse DP synchronized with the scan pulse SP is applied to the address electrode lines. Supplying to (X1 to Xn) causes selective address discharge to occur. Subsequently, in the discharge sustain period, the address discharge is generated by alternately supplying the sustain pulse SUSP to the scan / hold electrode lines Y1 to Ym and the common sustain electrode lines Z1 to Zm. The discharge in the cells is maintained for a predetermined period of time.

In such a subfield driving method, since the discharge sustain period is reduced by the time occupied by the reset period and the address period which do not contribute to the luminance, there is a problem of low luminance. For example, in the case of single scan of 480 scan lines, an address period required in one frame requires one line scan time (i.e., width of scan pulse) x 480 scan lines x 8 subfields. . When using a scanning pulse with a pulse width of about 3μs for sure address discharge, a total of 11.52ms is required for the address period and 13ms or more for including the reset period, which can be allocated to the discharge sustain period within one frame. The time is 16.67ms-13ms absolutely short, there is a problem that the brightness is low. Furthermore, when the conventional PDP driving method is used for a high-resolution PDP in which the number of scan lines is increased, the discharge sustaining period becomes shorter due to the increase in the address period, thereby making the display itself impossible. In this case, a method of reducing the width of the scanning pulse may be considered to shorten the address period. However, when the width of the scanning pulse is reduced to 2.5 μs or less, there is a possibility that erroneous discharge may occur due to the discharge delay phenomenon inherent to PDP.

In order to solve this problem of PDP, methods for reducing the address period by fast addressing have been proposed. Among the conventional high speed addressing methods, there is a method of dividing the panel up and down and simultaneously driving the address period by 1/2. However, in this screen division driving method, the scan / suspension electrode lines and the address electrode lines must be divided up and down to drive, so that the manufacturing cost of the PDP is increased by doubling the number of driving driver ICs.

Accordingly, it is an object of the present invention to provide a method of driving a PDP that enables high speed addressing.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge plasma display panel.

FIG. 2 is an overall electrode arrangement diagram of a plasma display panel including the discharge cells shown in FIG. 1.

3 is a frame configuration diagram for explaining a conventional subfield driving method.

4 is a driving waveform diagram of a conventional plasma display panel driving method.

5 is a driving waveform diagram in a plasma display panel driving method according to an embodiment of the present invention;

6A to 6E are diagrams showing the discharge mechanism according to the driving waveform shown in FIG.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y: scanning / holding electrode

12Z: common sustain electrode 14: upper dielectric layer

16: protective film 18: lower substrate

20X: address electrode 22: lower dielectric layer

24: partition 26: phosphor

1: discharge cell

In order to achieve the above object, the PDP driving method according to the present invention is a surface discharge between the scan / sustain electrode and the common sustain electrode formed side by side on the first substrate in the total discharge cells and at the same time A priming discharge step in which a counter discharge is generated between the address electrodes formed on the second substrate such that wall charges having a first polarity are formed at the scan / hold electrode and the address electrode and wall charges having a second polarity are formed at the common sustain electrode; ; A relatively short erase discharge is generated between the common sustain electrode and the address electrode, so that wall charges formed on the common sustain electrode and the address electrode are erased, so that a relatively small amount of wall charges whose polarities are reversed remain and the scan / hold electrode The wall charge formed in the device is characterized in that it comprises a reset step including an erase discharge step to increase the polarity without polarity inversion.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to FIGS. 5 to 6E.

5 is a driving waveform diagram of a PDP driving method according to an embodiment of the present invention. First, priming pulses PPx and PPy having positive voltages are simultaneously applied to the address electrode lines X1 to Xn and the scan / hold electrode lines Y1 to Ym in the reset period, and the common sustain electrode lines are simultaneously applied. The priming discharge is generated by applying the priming pulse PPz having a negative voltage to (Z1 to Zm). In this case, as the priming discharge, the surface discharge and the opposite discharge are simultaneously generated as shown in FIG. 6A. In other words, the surface discharge occurs between the scan / hold electrode line Y to which the positive voltage (100 V) is applied and the common sustain electrode line (Z) to which the negative voltage (-200 V) is applied. The opposite discharge occurs between the address electrode line X to which the voltage 100V is applied and the common sustain electrode line Z. Accordingly, more charged particles are generated inside the discharge cell. Subsequently, the charged particles generated by the priming discharge accumulate as wall charges as shown in FIG. 6B. Referring to FIG. 6B, electrons are accumulated on the dielectric layer where the address electrode line X and the scan / suspension electrode line Y, to which a positive voltage is applied, and the common sustain electrode line Z, to which a negative voltage is applied. On this dielectric layer, positive charges accumulate. Next, by applying the positive erase pulses EPy (100V) and EPz (200V) having a short width to the scan / hold electrode lines Y1 to Ym and the common sustain electrode lines Z1 to Zm, FIG. As shown in FIG. 2, erase discharge is generated only between the common sustain electrode line Z and the address electrode line X. FIG. The erase discharge causes the wall charges on the common sustain electrode line Z and the address electrode line X to be erased, and the charged particles generated by the erase discharge accumulate, and thus the common sustain electrode line Z as shown in FIG. 6D. ) And wall charges having a different polarity from the previous wall charges are formed on the address electrode line X. In this case, the previous wall charge amount is increased on the scan / hold electrode line Y. Referring to FIG. 6D, more electrons are accumulated on the scan / hold electrode line Y, negative wall charges are accumulated on the common sustain electrode line Z, and positive charges are accumulated on the address electrode line X. do. In this way, sufficient wall charges formed on the scan / sustain electrode line Y and the address electrode line X by priming discharge and erase discharge have the same polarity as the voltage supplied in the next address period, thereby easily causing the address discharge. To be. Specifically, in the address period, the scan pulse SP is sequentially supplied to the scan / suspension electrode lines Y1 to Ym, and the data pulse DP synchronized with the scan pulse SP is supplied to the address electrode lines X1. To Xn) to cause selective address discharge. In this case, as shown in FIG. 6E, the wall charges sufficiently formed by the priming discharge and the erase discharge are added to the address discharge voltage between the scan pulse SP (-100V) and the data pulse DP 100V. Certain address discharges occur. In other words, even when the width of the scanning pulse SP is made shorter than the conventional one by the sufficient wall charges, reliable address discharge occurs without erroneous discharge. Accordingly, high speed addressing is possible by reducing the width of the frequency pulse SP to reduce the address period. Subsequently, in the discharge sustain period, the address discharge is generated by alternately supplying the sustain pulse SUSP to the scan / hold electrode lines Y1 to Ym and the common sustain electrode lines Z1 to Zm. The discharge in the cells is maintained for a predetermined period of time.

As described above, in the PDP driving method of the present invention, a priming discharge and an erasure discharge are generated in the reset period, and a sufficient wall charge is provided to assist subsequent address discharges. Thus, even when a shorter scan pulse is applied, a reliable address can be obtained without false discharge. The discharge is generated, thereby enabling high speed addressing. In this case, a large amount of wall charges formed in the reset period adversely affects the contrast, so that proper wall charges are generated.

As described above, according to the PDP driving method according to the present invention, during the reset period, the scanning pulse is sufficiently formed by the priming discharge including the surface discharge and the opposite discharge, and the erasing discharge to sufficiently form the wall charge to assist the subsequent address discharge. It can be applied in a short time, thereby enabling high speed addressing. Accordingly, according to the PDP driving method according to the present invention, high-speed driving is possible with a single scan even in a high-resolution PDP in which an injection player is increased, thereby reducing manufacturing cost as compared to the conventional screen splitting method.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (3)

A reset step for initializing all of the discharge cells, an address step for selecting the discharge cells according to video data, and a discharge holding step for maintaining discharge in the selected discharge cells; In the reset step, In all discharge cells, surface discharge occurs between the scan / hold electrode and the common sustain electrode formed on the first substrate side by side, and at the same time, an opposite discharge occurs between the common sustain electrode and the address electrode formed on the second substrate. A priming discharge step of forming wall charges of a first polarity on the scan / hold electrode and the address electrode and forming wall charges of the second polarity on the common sustain electrode; A relatively short erase discharge is generated between the common sustain electrode and the address electrode, so that wall charges formed on the common sustain electrode and the address electrode are erased, and a relatively small amount of wall charges whose polarities are reversed remains. And a discharge discharge step of causing wall charges formed on the scan / hold electrode to be increased without polarity inversion. The method of claim 1, In the priming discharge step And a positive priming pulse applied to the scan / hold electrode and the address electrode and a negative priming pulse applied to the common sustain electrode for the surface discharge and the counter discharge. The method of claim 2, In the erase discharge step And a discharge pulse is generated between the common sustain electrode and the address electrode by applying a positive short erase pulse to the scan / sustain electrode and the common sustain electrode.