KR20030085694A - Plasma display panel and method of driving the same - Google Patents

Abstract

PURPOSE: A plasma display panel and a driving method thereof are provided to enhance the luminance and the discharging efficiency by obtaining the length of sustain electrodes. CONSTITUTION: A plasma display panel includes a plurality of address electrodes(64), a plurality of sustain electrodes(62), and a plurality of scanning electrodes(60). The address electrodes(64) are formed on an upper substrate in order to supply a sustain voltage when a sustain discharge process is performed. The sustain electrodes(62) are formed in parallel to the address electrodes(64) on the upper substrate. The scanning electrodes(60) are formed on a bottom substrate. The scanning electrode(60) and the address electrode(64) cross each other. Scan pulses are sequentially supplied to the scanning electrodes(60). An upper dielectric layer is formed on the upper substrate in order to store wall charges. A protective layer is formed on the upper dielectric layer. A bottom dielectric layer is formed on the bottom substrate. A delta type barrier rib(66) is formed on the bottom dielectric layer.

Description

Plasma display panel and its driving method {PLASMA DISPLAY PANEL AND METHOD OF DRIVING THE SAME}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a plasma display panel and a driving method thereof capable of improving luminance and discharge efficiency by securing lengths of sustain electrodes.

Recently, various flat panel displays have been developed to reduce weight and volume, which are disadvantages of cathode ray tubes. Such flat panel displays include Liquid Crystal Display (LCD), Field Emission Display (FED), Plasma Display Panel (PDP), and Electro-Luminescence (EL). And display devices. Among them, PDP has an advantage that it is easy to manufacture a large panel as a display device using gas discharge. As shown in FIG. 1, a three-electrode AC surface discharge type PDP having three electrodes and driven by an AC voltage is representative of the PDP.

Referring to FIG. 1, a discharge cell of a three-electrode alternating surface discharge PDP includes a pair of sustain electrodes 12Y and 12Z formed on an upper substrate 10 and an address electrode 12X formed on a lower substrate 18. Equipped.

The sustain electrode pairs 12Y and 12Z are constituted by the scan electrode 12Y and the sustain electrode 12Z, and the sustain electrode pairs 12Y and 12Z each consist of the transparent electrode 12a and the bus electrode 12b. The upper dielectric layer 14 and the passivation layer 16 are formed on the upper substrate 10 on which the sustain electrode pairs 12Y and 12Z are formed. The upper dielectric layer 14 accumulates wall charges generated during plasma discharge. The passivation layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 for wall charge accumulation is formed on the lower substrate 18 on which the address electrode 12X is formed. The partition wall 24 is formed on the lower dielectric layer 22, and the phosphor 20 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The partition wall 24 has a delta structure to prevent the ultraviolet rays and the visible rays generated by the discharge from leaking to the adjacent discharge cells. The phosphor 20 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The barrier rib 24 of the PDP has a stripe-type barrier rib structure to easily discharge discharge gas, but has a low luminance due to a small coating area of the phosphor 20.

In order to solve the problem of such a stripe-type partition wall, a delta-type partition structure as shown in FIG. 2 has been proposed.

The PDP having a delta partition wall extends from the first and second bus electrodes 32Y and 32Z, the first transparent electrode 34Y extending from the first bus electrode 32Y, and the second bus electrode 32Z. The second transparent electrode 34Z is provided. The first transparent electrode 34Y and the first bus electrode 32Y are used as scan electrodes, and the second transparent electrode 34Z and the second bus electrode 32Z are used as sustain electrodes.

The delta-type partition wall 42 intersects the plurality of first partition walls 36 formed in parallel with the first bus electrode 32Y and the first partition wall 36 to connect the first partition walls 36. The formed second partition 38 is provided. Here, the R, G, and B subpixels are arranged in a triangular shape by the delta partition.

In the PDP having the delta partition 42, the electrode electrode 30A is formed at a portion corresponding to the discharge space provided by the square delta partition 42 as shown in FIG. 3. In other areas, the width of the address electrode 30 is formed to be narrow. The narrow portion of the address electrode 30 is positioned under the rectangular delta partition 42 to prevent crosstalk with neighboring cells.

4 is a view showing a driving apparatus of a conventional three-electrode AC surface discharge type plasma display.

Referring to FIG. 4, in the driving apparatus of a conventional three-electrode AC surface discharge type PDP, m × n discharge cells 51 may include first electrode lines Y1 to Ym and second electrode lines Z1 to Zm. And a PDP 50 arranged in a matrix so as to be connected to the address electrode lines X1 to Xn, a scan / sustain driver 52 for driving the first electrode lines Y1 to Ym, and a second The common sustain driver 54 for driving the electrode lines Z1 to Zm, the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1 and the even-numbered address electrode lines X2. First and second address drivers 56A and 56B for dividing and driving .X4, ..., Xn-2, Xn are provided.

The scan / sustain driver 52 sequentially supplies scan pulses to the first electrode lines Y1 to Ym. In addition, the scan / sustain driver 52 supplies a sustain pulse to the first electrode lines Y1 to Ym in common. The common sustain driver 54 supplies a sustain pulse to all of the second electrode lines Z1 to Zm.

The first and second address drivers 56A and 56B supply image data to the address electrode lines X1 to Xn in synchronization with the scan pulse. The first address driver 56A supplies image data to the odd-numbered address electrode lines X1, X3, ..., Xn-3, Xn-1. The second address driver 56B supplies the image data to even-numbered address electrode lines X2, X4, ..., Xn-2, Xn.

Such a PDP is driven by dividing one frame into several subfields having different discharge times in order to express gray levels of an image. Each subfield is further divided into an initialization period for generating discharge uniformly, an address period for selecting discharge cells, and a sustain period for expressing gray levels according to the number of discharges.

For example, when displaying an image with 256 gray levels, a frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8 as shown in FIG. In addition, each of the eight subfields SF1 to SF8 is divided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period is 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. Is increased.

6 is a waveform diagram showing a driving method of a conventional three-electrode AC surface discharge type PDP.

Referring to FIG. 6, one subfield may include a reset period for initializing the entire screen, an address period for writing data while scanning the entire screen in a line-sequential manner, a sustain period for maintaining the light emission state of the cells in which the data is written, and the sustain. It is divided into an erasing period for erasing discharge.

First, in the reset period, the reset waveform RP is supplied to the scan electrode lines Y1 to Ym. When the reset waveform RP is supplied to the scan electrode lines Y1 to Ym, a reset discharge is generated between the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm to initialize the discharge cell.

In the address period, the scan pulse SP is sequentially applied to the scan electrode lines Y1 to Ym. The data pulse DP synchronized with the scan pulse SP is applied to the address electrode lines X1 through Xn. At this time, address discharge occurs in the discharge cells to which the data pulse DP and the scan pulse SP are applied.

In the sustain period, the first and second sustain pulses SUSPy and SUSPz are supplied to the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm. At this time, sustain discharge is generated in the discharge cells in which the address discharge is generated.

In the erase period, the erase pulse EP is supplied to the sustain electrode lines Z1 through Zm. When the erase pulse EP is supplied to the sustain electrode lines Z1 through Zm, the sustain discharge is erased.

The PDP driven as described above includes scan electrode lines Y1 to Ym and sustain electrode lines Z1 to Zm in left and right directions, and address electrode lines X1 to Xn in up and down directions. In order to maintain the plasma discharge stably, the lengths of the electrodes must be maintained to an appropriate level. In the conventional driving method, the lengths of the scan electrode lines Y1 to Ym and the sustain electrode lines Z1 to Zm are short. Therefore, it is not easy to produce an effective discharge. In other words, as the resolution of the PDP increases, the size of the discharge cells decreases, and the discharge cells including the delta-type barrier ribs have shorter lengths of upper and lower sides than left and right, and face the scan electrode lines Y1 to Ym facing in the direction perpendicular to the address electrode. The lengths of the sustain electrode lines Z1 to Zm become short. As a result, the luminance decreases as the driving voltage increases.

Accordingly, an object of the present invention relates to a plasma display panel and a driving method thereof capable of improving luminance and discharge efficiency by securing lengths of sustain electrodes.

1 is a cross-sectional view showing a conventional three-electrode AC surface discharge type plasma display panel.

2 is a plan view of a plasma display panel having a conventional delta partition.

FIG. 3 is a diagram illustrating an address electrode structure of a plasma display panel having a delta partition shown in FIG.

4 is a view showing a driving apparatus of a conventional plasma display.

5 shows one frame of a conventional plasma display panel.

6 is a drive waveform diagram supplied to one subfield of a conventional plasma display panel.

7 is a plan view illustrating a plasma display panel according to an exemplary embodiment of the present invention.

FIG. 8 is a sectional view of the plasma display panel shown in FIG. 7; FIG.

FIG. 9 is a driving waveform diagram of the plasma display panel shown in FIG. 7; FIG.

<Description of Symbols for Main Parts of Drawings>

10, 70: upper substrate 12X, 64: address electrode

12Y, 60 scan electrode 12Z, 62 sustain electrode

14, 22, 72, 78: dielectric layer 16, 74: protective film

18, 76: lower substrate 20, 80: phosphor

24, 42: partition 52: scan / sustain drive unit

54 common sustain driver 56 address driver

In order to achieve the above object, the plasma display panel according to the present invention is formed on the upper substrate and the address electrode to which the sustain voltage is supplied during the sustain discharge, the sustain electrode formed on the upper substrate in a direction parallel to the address electrode; And a scan electrode formed on the lower substrate in a direction crossing the address electrode and in which scan pulses are sequentially supplied in line to cause an address discharge with the address electrode.

An upper dielectric layer for accumulating wall charges on the upper substrate including the address electrode and the sustain electrode, a protective film formed on the upper dielectric layer, and a lower dielectric layer formed on the lower substrate including a scan electrode; And a delta-type partition wall formed on the lower dielectric layer.

In the method of driving a plasma display panel according to the present invention, a method of driving a plasma display panel including a scan electrode, a sustain electrode, and an address electrode is provided by supplying a reset pulse to the address electrode during a reset period of a subfield of one frame. Causing a reset discharge to occur between the scan electrodes, applying a scan pulse to the scan electrode and applying an address voltage to the address electrode after the reset discharge, and causing an address discharge; and after the address discharge, the address electrode And supplying sustain pulses to the sustain electrodes alternately to cause sustain discharge.

The reset discharge is performed by increasing the voltage in the form of a lamp in the setup of the reset pulse supplied to the address electrode to form a wall charge in the cell, and discharging the reset pulse. And partially erasing unnecessary down voltages, and supplying a positive DC voltage to the sustain electrode when the reset pulse is set down.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 to 9.

7 is a plan view illustrating a PDP according to a first embodiment of the present invention, and FIG. 8 is a cross-sectional view illustrating the PDP shown in FIG. 7.

7 and 8, a PDP according to the present invention includes an address electrode 60 and a sustain electrode 62 formed on an upper substrate (not shown), a scan electrode 64 formed on a lower substrate (not shown), and A delta partition 66 is provided.

The address electrode 60 is formed in the vertical direction of the discharge cell, and the address electrode 60 is supplied with the address voltage during the address period and causes sustain discharge with the sustain electrode 62 during the sustain period.

The sustain electrode 62 is formed in a direction parallel to the address electrode 60. The sustain electrode 62 maintains the DC voltage supplied in the reset period until the address period, and then sustain discharge with the address electrode 60 in the organic discharge period. Causes

An upper dielectric layer 72 and a passivation layer 74 are formed on the upper substrate 70 on which the address electrode 60 and the sustain electrode 62 are formed. The upper dielectric layer 72 accumulates wall charges generated during plasma discharge. The passivation layer 74 prevents damage to the upper dielectric layer 72 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 74, magnesium oxide (MgO) is usually used.

The scan electrode 54 is formed on the lower substrate in a direction crossing the address electrode 60 and the sustain electrode 62.

A lower dielectric layer 78 for wall charge accumulation is formed on the lower substrate 76 on which the scan electrodes 54 are formed. A delta partition wall 66 is formed on the lower dielectric layer 78, and a phosphor 80 is coated on the surfaces of the lower dielectric layer 78 and the delta partition wall 66. The delta partition 66 is a delta structure to prevent the ultraviolet and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor 80 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert gas for gas discharge is injected into the discharge space provided between the upper and lower substrates and the delta partition 66.

In comparison with the present invention and the conventional PDP, conventionally, the scan electrode and the sustain electrode are formed on the upper substrate and the address electrode is formed on the lower substrate, whereas in the present invention, the address electrode and the sustain electrode are formed on the upper substrate and Scan electrodes are formed on the substrate. Accordingly, in the related art, a sustain discharge occurs between the scan electrode and the sustain electrode, but in the present invention, a sustain discharge occurs between the address electrode and the sustain electrode.

In detail with reference to FIG. 8, one subfield may include a reset period for initializing the entire screen, an address period for writing data while scanning the entire screen in a linear sequential manner, and a light emission state of cells in which the data is written. It is divided into a sustain period for sustaining and an erase period for erasing sustain discharge.

First, the reset period is divided into a set-up period and a set-down period, and reset discharge is performed several times. In the setup period, the voltage increases in the form of a ramp ramp in which the ramp ramp waveform1 is continuous to the address electrodes A1 to An. In the set-down period, a falling ramp waveform ramp2 is provided in which the voltage decreases.

The rising ramp waveform ramp1 in the reset period causes a slight discharge between the address electrodes A1 to An and the sustain electrodes B1 to Bn. At this time, wall charges are accumulated on the upper dielectric layers on the address electrodes A1 to An and the sustain electrodes B1 to Bn.

Subsequently, the falling ramp waveform ramp2 in the set-down period is partially erased by appropriately erasing the wall charges in the discharge cell by the decreasing voltage, so that the wall charges are reduced to assist the next address discharge without causing an erroneous discharge. Done.

In order to reduce this wall charge, the positive DC voltage Vs is supplied to the sustain electrodes B1 to Bn during the setdown period. Since the falling ramp waveform ramp2 is gradually supplied to the positive DC voltage Vs, the address electrodes A1 to An are relative to the sustain electrodes B1 to Bn in the set-down period. The negative polarity (-), i.e., the polarity is reversed, reduces the wall charges generated during the setup period.

In the address period, a data pulse having a floating state for supplying voltages of positive and negative polarities is supplied according to the data signals supplied to the scan electrodes S1 to Sn. When the positive data pulse data is supplied, the scan pulses scn are sequentially supplied to the scan electrodes S1 to Sn in synchronization with the data pulse data. Then, the discharge cell to which the data pulse is supplied has an address discharge by adding the voltage corresponding to the voltage difference between the data pulse and the scan pulse scn and the internal wall voltage accumulated by the wall charge in the discharge cell. Is generated. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.

In the sustain period, sustain discharge is started in the discharge cells in which the wall pulses are sufficiently formed in the address period by supplying the triggering pulses TP to the address electrodes A1 to An at the beginning. Subsequently, sustain pulses SUSA and SUSB are alternately supplied to the address electrodes A1 to An and the sustain electrodes B1 to Bn to maintain sustain discharge during the sustain period. Then, the cells selected by the address discharge cause sustain discharge upon every sustain pulse (SUS) supply.

In the erase period, the discharge pulse EP is supplied to the sustain electrodes B1 to Bn to stop the discharge. The erasing pulse EP has a ramp wave shape in which the light emission size is small and has a short pulse width for discharging the discharge. The charged particles are erased by the short erase discharge by the erase pulse EP to stop the discharge.

As described above, in the PDP and the driving method thereof according to the present invention, the length of the scanning electrode is increased by arranging the scanning electrode at the position of the conventional address electrode and placing the address electrode at the position of the conventional scanning electrode. By changing the positions of the address electrode and the scan electrode as described above, address discharge is more likely to occur, thereby improving the address voltage margin, thereby improving luminance and discharge efficiency of sustain discharge after the address discharge. Here, in the PDP according to the present invention, sustain discharge is generated between the address electrode and the sustain electrode to which the sustain voltage is supplied.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (4)

An address electrode formed on the upper substrate and supplied with a sustain voltage during sustain discharge; A sustain electrode formed on the upper substrate in a direction parallel to the address electrode; And a scan electrode formed on a lower substrate in a direction crossing the address electrode and supplied with scan pulses sequentially in a line so as to cause an address discharge with the address electrode. The method of claim 1, An upper dielectric layer for accumulating wall charges on the upper substrate including the address electrode and the sustain electrode; A protective film formed on the upper dielectric layer; A lower dielectric layer formed on the lower substrate including the scan electrode; And a delta barrier rib formed on the lower dielectric layer. In a driving method of a plasma display panel including a scan electrode, a sustain electrode and an address electrode, Supplying a reset pulse to the address electrode during a reset period of a subfield period of one frame to cause a reset discharge to occur between the scan electrodes; Generating an address discharge by applying a scan pulse to the scan electrode and applying an address voltage to the address electrode after the reset discharge; And supplying sustain pulses to the address electrodes and sustain electrodes alternately after the address discharge to cause sustain discharge. The method of claim 3, wherein The reset discharge is Increasing the voltage in the form of a lamp when setting up the reset pulse supplied to the address electrode to form and discharge wall charges in the cell; Causing the voltage to decrease in the form of a lamp when the reset pulse is set down so that the unwanted down voltages are partially erased by wall charge; And supplying a positive DC voltage to the sustain electrode when the reset pulse is set down.