KR20060067277A - Method of driving plasma display panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel that can prevent cell erasing and prevent address mis-discharge.

A driving method of a plasma display panel according to the present invention includes a scan electrode, a sustain electrode, and an address electrode, and is divided into a reset period, an address period, and a sustain period. Sequentially applying negative scan voltages to the odd scan electrodes of the electrodes; And sequentially applying negative scan voltages to even-numbered scan electrodes of the scan electrodes.

According to this configuration, the present invention divides the scan electrodes into a radix group and an even group to sequentially apply negative scan pulses to the scan groups of any of the odd and even scan electrodes, and then the remaining scan electrodes. By sequentially applying negative scan pulses, the voltage difference between vertically adjacent cells can be maintained at least at least the scan voltage to prevent crosstalk between vertically adjacent cells. Accordingly, even if the address discharge is generated in the cell to which the scan pulse is applied, the erasure of the electrons can be prevented in the vertically adjacent cells, thereby preventing the address erroneous discharge due to the cell erase.

Description

Driving method of plasma display panel {METHOD OF DRIVING PLASMA DISPLAY PANEL}             

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 and 3 are cross-sectional views of the discharge cells shown in FIG.

4 is a diagram illustrating an example of a luminance weight value of a subfield included in one frame.

5 is a waveform diagram illustrating a method of driving a conventional plasma display panel.

FIG. 6 is a diagram illustrating electron erasure between cells vertically adjacent by the driving waveform shown in FIG. 5.

7 is a waveform diagram illustrating a method of driving a plasma display panel according to a first embodiment of the present invention.

8 is a waveform diagram illustrating a method of driving a plasma display panel according to a second embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

24: partition 26: phosphor layer

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel to prevent cell erasing and prevent address mis-discharge.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of an inert mixed gas such as He + Xe, Ne + Xe or He + Xe + Ne. An image containing graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type PDP.

Referring to FIG. 1, a discharge cell of a conventional three-electrode AC surface discharge type PDP includes a scan electrode Y and a sustain electrode Z formed on an upper substrate 10, and an address formed on a lower substrate 18. An electrode X is provided. Each of the scan electrode Y and the sustain electrode Z has a line width smaller than the line widths of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and is formed on one side edge of the transparent electrode 12Y and 12Z. 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 24 is formed in parallel with the address electrode X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

In the conventional three-electrode surface discharge type PDP, the scan electrode Y and the sustain electrode Z are alternately formed on the upper substrate 10 as shown in FIG. 2, or adjacent to each other as shown in FIG. 3. Scan electrodes Y and sustain electrodes Z are formed adjacent to each other between discharge cells. Here, the upper substrate 10 shown in FIGS. 2 and 3 is rotated 90 degrees for comparison with the lower substrate 18.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to realize grayscale of an image. Each subfield is divided into a reset period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray scale according to the number of discharges.

Here, the reset period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling lamp waveform is supplied. For example, when the image is to be displayed in 256 gray levels, as shown in FIG. 4, the frame period (16.67 ms) corresponding to 1/40 second is divided into eight subfields SF1 to SF8. Each of the eight subfields SF1 to SF8 is divided into a reset period, an address period and a sustain period as described above. The reset period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

5 is a waveform diagram showing a conventional method for driving a PDP.

Referring to FIG. 5, the conventional driving method of the PDP is divided into a reset period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the reset period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. During the set-down period, the rising ramp waveform (Ramp-up) is supplied, and then the falling ramp waveform (-) falls to the negative (-) at a positive sustain voltage lower than the peak voltage of the rising ramp waveform (Ramp-up). Ramp-down is simultaneously applied to the scan electrodes Y. Ramp-down generates weak erase discharges in the cells, eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing wall charges required for address discharges in the cells of the full screen. Will remain.

In the address period, the negative scan pulse Vscan is sequentially applied to the scan electrodes Y, and the positive data pulse Vd is applied to the address electrodes X. As the voltage difference between the scan pulse Vscan and the data pulse Vd and the wall voltage generated in the reset period are added, an address discharge is generated in the cell to which the data pulse Vd is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive pole DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, positive (+) sustain pulses (sus) are applied to the scan electrodes (Y) and the sustain electrodes (Z) alternately. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode (Y) and the sustain electrode (Z) whenever the sustain pulse (sus) is applied while the wall voltage and the sustain pulse (sus) in the cell are added. This will happen.

However, since the driving waveform of the PDP is sequentially applied from the top to the bottom of the negative scanning pulse (Vscan) to the scan electrodes (Y) in the scan electrodes (Y) formed vertically during the address discharge Due to the crosstalk, electrons disappear from the adjacent neighbor cell Cell2 as shown in FIG. 6. As a result, a cell erase phenomenon occurs in the adjacent cell Cell2, which causes an erroneous discharge upon address discharge.

Accordingly, an object of the present invention is to provide a method of driving a plasma display panel which can prevent cell erasing and prevent address mis-discharge.

In order to achieve the above object, a method of driving a plasma display panel according to the present invention includes a scan electrode, a sustain electrode, and an address electrode, and in the method of driving a plasma display panel divided into a reset period, an address period, and a sustain period. Sequentially applying negative scan voltages to the odd scan electrodes of the scan electrodes during the address period; And sequentially applying negative scan voltages to even-numbered scan electrodes of the scan electrodes.

The method of driving a plasma display panel according to the present invention further includes applying a positive DC voltage greater than a positive scan voltage to even-numbered scan electrodes when a negative scan voltage is applied to the odd scan electrodes. do.

The driving method of the plasma display panel according to the present invention further includes applying a positive DC voltage greater than the positive scan voltage to the odd scan electrodes when the negative scan voltage is applied to the even-numbered scan electrodes. Include.

The scan voltage may be a voltage greater than the voltage of the data pulses applied to the address electrodes during the address period and less than the maximum operating voltage of the scan driver generating the scan voltage.

The positive DC voltage is greater than the positive scan voltage and is less than twice the minimum sustain voltage supplied to the sustain electrode during the address period.

The driving method of the plasma display panel according to the present invention sequentially applies a rising ramp waveform and a falling ramp waveform falling to the negative polarity at a positive sustain voltage lower than the peak voltage of the rising ramp waveform to the scan electrodes in the reset period. And alternately applying sustain pulses to the scan electrodes and the sustain electrodes in the sustain period.

Other objects and features of the present invention in addition to the above object will be apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 7 and 8.

7 is a waveform diagram illustrating a method of driving a PDP according to a first embodiment of the present invention.

Referring to FIG. 7, the driving method of the PDP according to the first embodiment of the present invention is divided into a reset period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell. do.

In the reset period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. During the set-down period, the rising ramp waveform (Ramp-up) is supplied, and then the falling ramp waveform (-) falls to the negative (-) at a positive sustain voltage lower than the peak voltage of the rising ramp waveform (Ramp-up). Ramp-down is simultaneously applied to the scan electrodes Y. Ramp-down generates weak erase discharges in the cells, eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing wall charges required for address discharges in the cells of the full screen. Will remain.

In the address period, the negative scan pulse Vscan is sequentially applied to the odd-positioned scan electrodes Y, and then the negative-numbered scan electrodes Y are placed on the even-numbered scan electrodes Y. Scan pulses Vscan are sequentially applied. In other words, in the address period, all the scan electrodes Y are divided into odd group and even group, and the negative scan pulse Vscan is first applied to the odd scan electrodes Y. After the application, the negative scan pulse Vscan is applied to the even-numbered scan electrodes Y. Here, when a negative scan pulse Vscan is applied to the odd scan electrodes Y, the positive DC voltage of greater than the scan voltage Vsc is applied to the even scan electrodes Y. (Vb) is applied. At this time, the scan voltage Vsc is larger than the voltage value of the data pulse Vd and is smaller than the maximum operating voltage of the scan driver (not shown). In addition, a value of the positive DC voltage Vb is larger than the scan voltage Vsc and less than twice the minimum value of the sustain voltage Vs. When the negative scan pulse Vscan is applied to the scan electrodes Y, the data pulse Vd is applied to the address electrodes X. Accordingly, in the address period, the voltage difference between the scan pulse Vscan and the data pulse Vd and the wall voltage generated in the reset period are added, and an address discharge occurs in the cell to which the data pulse vd is applied. Wall charges are generated in the cell selected by.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode (Y) and the sustain electrode (Z) whenever the sustain pulse (sus) is applied while the wall voltage and the sustain pulse (sus) in the cell are added. Discharge occurs. Here, the number of sustain pulses (sus) supplied during the sustain period is set corresponding to the luminance weight of each frame.

As described above, in the driving method of the PDP according to the first embodiment of the present invention, the scan electrodes Y are divided into the odd group odd and the even group negative to the odd scan electrodes Y. ) Scan pulses (Vscan) are sequentially applied, and then negative scan pulses (Vscan) are sequentially applied to even-numbered scan electrodes (Y), and negative polarities are applied to odd scan electrodes (Y). When a negative scan pulse Vscan is applied, at least a scan is performed between vertically adjacent cells by applying a positive DC voltage Vb greater than the scan voltage Vsc to even-numbered scan electrodes Y. A voltage difference greater than or equal to the voltage Vsc is generated. As a result, when an address discharge occurs in a cell to which a scan pulse Vscan is applied, electrons do not move from the cell where the address discharge occurs to a vertically adjacent cell, that is, no crosstalk occurs. In the cell, cell erasure is prevented. As a result, erroneous discharges can be prevented during address discharge in vertically adjacent cells.

8 is a waveform diagram illustrating a method of driving a PDP according to a second embodiment of the present invention.

Referring to FIG. 8, the driving method of the PDP according to the second embodiment of the present invention is divided into a reset period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell. do.

Among these, since the reset period and the sustain period are the same as the driving method according to the first embodiment of the present invention described above, the detailed description will be replaced with the above description.

In the address period, the negative scan pulse Vscan is sequentially applied to the odd-positioned scan electrodes Y, and then the negative-numbered scan electrodes Y are placed on the even-numbered scan electrodes Y. Scan pulses Vscan are sequentially applied. At this time, when a negative scan pulse (Vscan) is applied to the odd scan electrodes (Y), a positive DC voltage of greater than the scan voltage (Vsc) is applied to the even scan electrodes (Y). When (Vb) is applied and the negative scan pulse (Vscan) is applied to the even-numbered scan electrodes (Y), the positive scan (Vsc) larger than the scan voltage (Vsc) is applied to the odd-numbered scan electrodes (Y). DC voltage Vb of +) is applied. Here, the scan voltage Vsc is larger than the voltage value of the data pulse Vd and smaller than the maximum operating voltage of the scan driver (not shown). In addition, a value of the positive DC voltage Vb is larger than the scan voltage Vsc and less than twice the minimum value of the sustain voltage Vs. When the negative scan pulse Vscan is applied to the scan electrodes Y, the data pulse Vd is applied to the address electrodes X. Accordingly, in the address period, the voltage difference between the scan pulse Vscan and the data pulse Vd and the wall voltage generated in the reset period are added, and an address discharge occurs in the cell to which the data pulse vd is applied. Wall charges are generated in the cell selected by.

As described above, in the driving method of the PDP according to the second embodiment of the present invention, the scan electrodes Y are divided into the odd group and the even group, which is one of the odd or even number scan electrodes Y. A negative scan pulse (Vscan) is applied to one group of scan electrodes (Y), and a positive DC voltage (Vb) is supplied to the other scan electrodes (Y). Therefore, a voltage difference of at least the scan voltage Vsc occurs between adjacent cells. As a result, when an address discharge occurs in a cell to which a scan pulse Vscan is applied, electrons do not move from the cell where the address discharge occurs to a vertically adjacent cell, that is, no crosstalk occurs. In the cell, cell erasure is prevented. As a result, erroneous discharges can be prevented during address discharge in vertically adjacent cells.

As described above, the driving method of the plasma display panel according to the present invention separates the scan electrodes into an odd group and an even group to apply negative scan pulses to the scans of any one of the odd and even scan electrodes. By sequentially applying negative scan pulses to the remaining scan electrodes, the voltage difference between vertically adjacent cells can be maintained at least at least the scan voltage, thereby preventing crosstalk between vertically adjacent cells. Accordingly, even if the address discharge is generated in the cell to which the scan pulse is applied, the erasure of the electrons can be prevented in the vertically adjacent cells, thereby preventing the address erroneous discharge due to the cell erase.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (6)

In a driving method of a plasma display panel having a scan electrode, a sustain electrode and an address electrode, the driving method is divided into a reset period, an address period and a sustain period. Sequentially applying negative scan voltages to odd-numbered scan electrodes of the scan electrodes during the address period; And sequentially applying negative scan voltages to even-numbered scan electrodes of the scan electrodes. The method of claim 1, And applying a positive DC voltage greater than the positive scan voltage to the even-numbered scan electrodes when the negative scan voltage is applied to the odd-numbered scan electrodes. . The method of claim 2, And applying a positive DC voltage greater than the positive scan voltage to the odd-numbered scan electrodes when the negative scan voltage is applied to the even-numbered scan electrodes. Way. The method of claim 1, And the scan voltage is greater than the voltage of the data pulses applied to the address electrodes during the address period and is less than the maximum operating voltage of the scan driver generating the scan voltage. The method of claim 1, And wherein the positive DC voltage is greater than the positive scan voltage and less than twice the minimum sustain voltage supplied to the sustain electrode during the address period. The method of claim 1, Sequentially applying a rising ramp waveform and a falling ramp waveform falling negatively at a positive sustain voltage lower than a peak voltage of the rising ramp waveform to the scan electrodes in the reset period; And alternately applying sustain pulses to the scan electrodes and the sustain electrodes during the sustain period.

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