KR100585528B1 - Driving Method of Plasma Display Panel - Google Patents

Abstract

The present invention relates to a plasma display panel driving method.

According to the present invention, when a plurality of subfields having different emission counts are divided into reset periods, address periods, and sustain periods to implement an image, a negative voltage (−) is applied to the scan electrode Y after sustain discharge of the first subfield. And discharging discharge by supplying a narrow pulse of positive voltage to the sustain electrode Z at the same time. After the erase discharge, the erase electrode is discharged to the scan electrode Y in the remaining subfields except for the first subfield. Supplying a rising ramp pulse, and supplying a scan pulse of a negative voltage after supplying a rising ramp pulse waveform to the scan electrode (Y) to perform addressing discharge.

Description

Driving Method of Plasma Display Panel {Driving Method of Plasma Display Panel}

1 is a perspective view showing the structure of a conventional three-electrode AC surface discharge type PDP.

2 is a diagram showing a method of expressing image gradation of a conventional PDP.

3 is a diagram illustrating a driving waveform of a PDP according to a conventional selective writing method.

4 is a view showing a driving waveform in accordance with the plasma display panel driving method of the present invention.

***** Explanation of symbols for the main parts of the drawing *****

10: upper substrate 11: scanning / sustaining electrode

12: common sustain electrode 13a, 13b: dielectric layer

14: protective film 20: lower substrate

21: partition 22: address electrode

23: phosphor layer

The present invention relates to a plasma display panel driving method, and more particularly to a plasma display panel driving method that can improve the contrast characteristics while ensuring a voltage margin.

In general, a plasma display panel (hereinafter referred to as "PDP") displays an image including a character or a graphic by emitting phosphors by 147 nm ultraviolet rays generated when a He + Xe or Ne + Xe inert mixed gas is discharged. Done.

1 is a perspective view showing the structure of a conventional three-electrode AC surface discharge type PDP. Referring to FIG. 1, the three-electrode AC surface discharge type PDP includes a scan / sustain electrode 11 and a common sustain electrode 12 formed on the upper substrate 10, and an address electrode formed on the lower substrate 20. 22). Each of the scan / sustain electrode 11 and the common sustain electrode 12 is formed of a transparent electrode, for example, indium-tin oxide (ITO, 11a, 12a). Each of the scan / sustain electrode 11 and the common sustain electrode 12 is formed with metal bus electrodes 11b and 12b for reducing resistance. An upper dielectric layer 13a and a passivation layer 14 are stacked on the upper substrate 10 having the scan / sustain electrode 11 and the common sustain electrode 12 formed thereon. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 13a. The protective layer 14 prevents damage to the upper dielectric layer 13a due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As the protective film 14, magnesium oxide (MgO) is usually used.

Meanwhile, the lower dielectric layer 13b and the partition wall 21 are formed on the lower substrate 20 on which the address electrode 22 is formed, and the phosphor layer 23 is formed on the surfaces of the lower dielectric layer 13b and the partition wall 21. Is applied. The address electrode 22 is formed in a direction crossing the scan / sustain electrode 11 and the common sustain electrode 12. The partition wall 21 is formed in parallel with the address electrode 22 to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 23 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 20 and the partition wall 21. A method of expressing image gradation of a conventional PDP having such a structure will be described with reference to FIG. 2.

2 shows a method of expressing image gradation of a conventional PDP. As shown, the image gradation of the PDP is driven by dividing one frame into several subfields having different number of emission times. Each subfield is divided into a reset period for uniformly generating a discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields. In addition, each of the eight subfields is divided into an address period and a sustain period. Here, the reset period and the address period of each subfield are the same for each subfield, while the sustain period increases at a rate of 2n (n = 0,1,2,3,4,5,6,7) in each subfield. do.

Such a driving method of the PDP is roughly divided into a selective writing method and a selective erasing method according to whether or not the discharge cells are lighted up by the address discharge in the address period. In the selective write driving method, the full screen is turned off in the reset period, and then the selected discharge cells are turned on in the address period. Subsequently, in the sustain period, an image is displayed by sustaining discharge cells selected by the address discharge. Looking at the driving method of the selective writing method in more detail as shown in FIG.

3 illustrates a driving waveform of a PDP according to a conventional selective writing method. Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing all screens, an address period for selecting cells, and a sustain period for maintaining discharge of the selected cells.

In the initialization period, the rising ramp waveform Ramp-up is simultaneously applied to all the scan electrodes Y in the setup period SU. This rising ramp waveform causes discharge to occur in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the address electrode X and the sustain electrode Z, and negative wall charges are accumulated on the scan electrode Y. During the set-down period SD, after the rising ramp waveform is supplied, the ramp ramp starts to fall from the positive voltage lower than the peak voltage of the rising ramp waveform and falls to the base voltage GND or a specific voltage level of the negative ramp. -down) causes a slight erase discharge in the cells, which partially erases the overcharged wall charge. By this set down discharge, the wall charges such that the address discharge can stably occur remain uniformly in the cells.

In the address period, the negative scan pulse Scan is sequentially applied to the scan electrodes Y, and the positive data pulse data is applied to the address electrodes X in synchronization with the scan pulse. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges are formed such that a discharge can occur when a sustain voltage is applied. The sustain electrode Z is supplied with a positive polarity DC voltage Zdc during the set down period and the address period so as to reduce the voltage difference with the scan electrode Y so that an erroneous discharge with the scan electrode Y does not occur.

In the sustain period, a sustain pulse Su is applied to the scan electrodes Y and the sustain electrodes Z alternately. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge occurs between the scan electrode Y and the sustain electrode Z every time the sustain pulse is applied.

After the sustain discharge is completed, a ramp waveform (Ramp-ers) having a small pulse width and a low voltage level is supplied to the sustain electrode Z to erase the wall charge remaining in the cells of the full screen.

However, the conventional PDP driven by the above method has a problem in that the contrast characteristic is degraded by the light generated in the initialization period of each subfield. In addition, there is a problem in that the efficiency of the driving voltage margin decreases when a high voltage is applied in order to accumulate wall charges in the initialization period of each subfield, that is, the setup period.

Accordingly, an object of the present invention is to provide a plasma display panel driving method capable of improving contrast characteristics and driving voltage margin in a plasma display panel having a selective writing method.

The present invention provides a plasma display panel driving method in which a plurality of subfields having different emission counts are divided into an initialization period, an address period, and a sustain period to implement an image. Supplying a negative (-) voltage to the scan electrode (Y) and simultaneously supplying a narrow pulse waveform of a positive (+) voltage to the sustain electrode (Z) to perform an erase discharge, after the erase discharge, the first sub Supplying a rising ramp pulse waveform to the scan electrode (Y) in the remaining subfields except the field, and supplying a rising pulse pulse waveform to the scan electrode (Y), and then supplying a scan pulse waveform of negative voltage (-). And performing addressing discharge.

The width of the last sustain pulse in the sustain period of the subfield is larger than the width of the other sustain pulses.

In the sub-fields other than the first subfield, a discharge is not generated between the scan electrode Y and the sustain electrode Z in the step of supplying the rising ramp pulse waveform to the scan electrode Y.

The negative voltage (−) supplied to the scan electrode Y may be greater than or equal to -100V and less than 0V.

The positive voltage (+) supplied to the sustain electrode Z is characterized in that the sustain voltage (Vs).

The narrow pulse width of the positive voltage (+) supplied to the sustain electrode (Z) is less than 10 Hz.

The peak voltage of the rising ramp pulse supplied to the scan electrode (Y) is a sustain voltage (Vs).

The negative voltage of the scan pulse supplied to the scan electrode Y is -150 V or more and less than 0 V.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

4 is a view showing a driving waveform in accordance with the plasma display panel driving method of the present invention. Referring to FIG. 4, the plasma display panel driving method of the present invention includes a scan waveform supplied in an initialization period of a first subfield and a scan waveform supplied in an address period and a scan waveform and an address period of an initialization period of remaining subfields. The waveforms are supplied with different settings.

First, in the initialization period of the first subfield, the rising ramp waveform Ramp-up is simultaneously supplied to all the scan electrodes Y during the setup period SU, and the falling ramp waveform (the falling-down waveform SD) is applied to the set down SD. Ramp-down is supplied to cause a slight erase discharge in the cells, thereby partially erasing the excessively formed wall charge.

As in the conventional case, the address period of the first susfield is also sequentially applied to the scan electrodes Y and the negative data pulse data is applied to the address electrodes X in synchronization with the scan pulses. Is applied. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied.

In the sustain period of the first subfield, after the sustain discharge between the scan electrode Y and the sustain electrode Z is completed, the erase ramp waveform Ramp-ers having a small pulse width and voltage level is supplied to the conventional sustain electrode Z. Instead, a negative voltage (−) is supplied to the scan electrode Y, and a narrow pulse of positive voltage is supplied to the sustain electrode Z to completely erase wall charges formed in the discharge cell.

On the other hand, the width of the last sustain pulse during the sustain period of the subfield is larger than the width of the other sustain pulses so that the wall charges formed in the discharge cells during erasing discharge can be completely erased.

At this time, the negative (-) voltage supplied to the scan electrode (Y) may vary depending on the width of the last sustain pulse, but in consideration of the width of the general sustain pulse is more than -100V ~ less than 0V.

In addition, the positive (+) voltage of the narrow pulse supplied to the sustain electrode Z is a sustain voltage, which uses the voltage value of the sustain pulse used in the sustain discharge. However, the width of the sustain pulse is less than 10 ms by adjusting the timing signal of the pulse.

Looking at the state of the wall charge from the sustain period to the erase discharge in the sustain period, first, as the width of the last sustain pulse is widened on the scan electrode (Y) after the sustain discharge is completed, more negative wall charges are accumulated, Subsequently, when an erase voltage is applied by applying a negative voltage to the scan electrode Y and a narrow pulse of positive voltage to the sustain electrode Z, the wall charge of the selected discharge cell is almost completely erased during the sustain discharge. do. At this time, space charges exist in the cell space instead of wall charges.

Subsequently, during the initialization period of the second subfield, a rising ramp waveform is supplied to the scan electrode Y to form wall charge by using the space charge in the discharge cell in which the wall charge is completely erased after the sustain discharge of the first subfield. do. That is, the peak voltage of the rising ramp waveform supplied to the scan electrode Y in the initialization period is not accumulated by supplying a voltage higher than the sustain voltage in the initialization period in every subfield in the related art, and sustain voltage Vs. Only up to maintains the space charge existing in the discharge cell space as the wall charge.

As described above, if the wall charge in the discharge cell is completely erased after the sustain discharge in the first subfield, and the wall charge is formed using the space charge in the discharge cell space, the wall charge in the entire discharge cell space becomes uniform. There is no need to supply a falling ramp waveform for weakly erasing and uniformly discharging the wall charge of the time discharge cell.

In addition, since the setup discharge does not occur in the initialization period of the remaining subfields except the first subfield, the black luminance value of the plasma display panel is very low, thereby improving contrast characteristics.

In addition, the conventional falling ramp waveform is supplied, thereby eliminating the set-down period that causes the erase discharge, thereby improving driving margin.

Thereafter, in the address period of the second subfield, a scan pulse of negative voltage is sequentially supplied to the scan electrode Y and a positive data pulse is applied to the address electrode Z at the same time. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied.

At this time, since the wall voltage generated in the initialization period is lower than the wall voltage generated in the initialization period of the first subfield, sufficient address discharge may occur between the scan electrode Y and the address electrode Z in the address period. The voltage of the scan pulse supplied to the scan electrode Y is supplied at -150V or more to less than 0V. That is, the potential difference between the scan electrode Y and the address electrode Z is increased to allow smooth address discharge.

As described above, it will be understood by those skilled in the art that the above-described technical configuration may be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, the above-described embodiments are to be understood as illustrative and not restrictive in all respects, and the scope of the present invention is indicated by the appended claims rather than the detailed description, and the meaning and scope of the claims and All changes or modifications derived from the equivalent concept should be interpreted as being included in the scope of the present invention.

As described above, the present invention has the effect of securing the driving margin and improving the contrast characteristics by changing the plasma display panel driving method.

Claims (8)

A method of driving a plasma display panel in which a plurality of subfields having different emission counts are divided into an initialization period, an address period, and a sustain period to implement an image. After the sustain discharge of the first subfield, supplying a negative voltage (−) to the scan electrode (Y) and simultaneously supplying a narrow pulse waveform of positive voltage (+) to the sustain electrode (Z) to perform an erase discharge; Supplying a rising ramp pulse waveform to the scan electrode (Y) in the remaining subfields other than the first subfield after the erase discharge; And After supplying a rising ramp pulse waveform to the scan electrode (Y), supplying a scan pulse waveform of a negative voltage (-) to the addressing discharge Plasma display panel driving method comprising a. The method of claim 1, And the width of the last sustain pulse is greater than the width of the other sustain pulses during the sustain period of the subfield. The method of claim 1, The plasma display panel is characterized in that no discharge occurs between the scan electrode (Y) and the sustain electrode (Z) in the step of supplying the rising ramp pulse waveform to the scan electrode (Y) in the remaining subfields other than the first subfield. Driving method. The method of claim 1, The negative polarity (−) voltage supplied to the scan electrode (Y) is -100V or more to less than 0V. The method of claim 1, The positive polarity (+) voltage supplied to the sustain electrode (Z) is a sustain display voltage (Vs). The method according to claim 1 or 5, And a width of the narrow pulse waveform of the positive voltage (+) supplied to the sustain electrode (Z) is less than 10 Hz. The method of claim 1, The peak voltage of the rising ramp pulse waveform supplied to the scan electrode (Y) is a sustain voltage (Vs). The method of claim 1, The negative polarity (-) voltage of the scan pulse supplied to the scan electrode (Y) is -150V or more ~ less than 0V.

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