KR100488457B1 - Method for Driving Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel that can improve contrast.

In the driving method of the plasma display panel of the present invention, a rising ramp waveform is supplied to a plurality of scan electrodes during a setup period, a falling ramp waveform is supplied to a plurality of scan electrodes during a set-down period after the setup period, and a setup period. And applying a positive pulse to a plurality of address electrodes formed in a direction crossing the scan electrode for a period of time.

Description

Driving Method for Plasma Display Panel {Method for Driving Plasma Display Panel}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel to improve contrast.

Plasma Display Panel (hereinafter referred to as "PDP") is an ultraviolet light generated when an inert mixed gas such as He + Xe, Ne + Xe, He + Xe + Ne, etc. discharges to display an image by emitting phosphors. do. Such PDPs are not only thin and large in size, but also have improved in image quality due to recent technology development.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode 30Y and a sustain electrode 30Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. 20X).

Each of the scan electrode 30Y and the sustain electrode 30Z has a line width smaller than that of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and the metal bus electrodes 13Y, which are formed at one edge of the transparent electrode, respectively. 13Z). The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (ITO). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance.

The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode 30Y and the sustain electrode 30Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used.

The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode 20X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode 20X is formed in the direction crossing the scan electrode 30Y and the sustain electrode 30Z. The partition wall 24 is formed in parallel with the address electrode 20X to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. Inert mixed gas is injected into the discharge space provided between the upper and lower substrates 10 and 18 and the partition wall 24.

The PDP is time-divisionally driven by dividing one frame into several subfields having different number of emission times in order to implement grayscale of an image. Each subfield is divided into an initialization period for initializing the full screen, an address period for selecting a scan line and selecting a cell in the selected scan line, and a sustain period for implementing gray levels according to the number of discharges. Here, the initialization period is divided into a setup period in which the rising ramp waveform is supplied and a set down period in which the falling lamp waveform is supplied.

For example, when the image is to be displayed with 256 gray levels, as shown in FIG. 2, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. As described above, each of the eight subfields SF1 to SF8 is divided into an initialization period, an address period, and a sustain period. The initialization period and the address period of each subfield are the same for each subfield, while the sustain period is increased at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. .

3 shows driving waveforms of a PDP supplied to two subfields.

In Fig. 3, Y represents a scan electrode and Z represents a sustain electrode. And X represents an address electrode.

Referring to FIG. 3, the PDP is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Ramp-up) causes a slight discharge in the cells of the full screen to generate wall charges in the cells. The rising ramp waveform Ramp-up rises from the sustain voltage Vs to the sum of the setup voltage Vsetup and the sustain voltage Vs.

During the set down period, the rising ramp waveform Ramp-up is supplied, and then the falling ramp waveform Ramp-down falling from the positive voltage Vs lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes ( Is simultaneously applied to Y). Ramp-down generates weak erase discharges in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by setup discharges, and uniformly distributing the wall charges required for address discharges in the cells of the full screen. Will remain. In practice, the falling ramp waveform (Ramp-down) is lowered from the sustain voltage (Vs) to the negative voltage (-Vy) so that the desired wall charges can remain during the setdown period.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

In the conventional PDP initialization period driven as described above, the discharge cells must be kept uniform in wall charge regardless of whether the previous sustain period is discharged or not. In addition, the wall charge necessary for the address discharge must be uniformly formed during the initialization period. To this end, a rising ramp waveform Rmap-up having a high voltage value is applied during the initialization period. However, if a rising ramp waveform having a high voltage value is applied during the initialization period, a strong initialization discharge occurs, thereby causing a problem of lowering the contrast. In other words, a large amount of light is generated by the strong initialization discharge, and the light is emitted to the outside to lower the contrast of the PDP.

Accordingly, it is an object of the present invention to provide a method of driving a plasma display panel which can improve contrast.

In order to achieve the above object, the driving method of the plasma display panel according to the present invention includes supplying a ramp ramp waveform to a plurality of scan electrodes during a setup period, and supplying a ramp ramp waveform to a plurality of scan electrodes during a set down period after the setup period. And applying a positive pulse to a plurality of address electrodes formed in a direction crossing the scan electrodes during a part of the setup period.

The positive pulse is applied at the same time as the rising ramp waveform and held for the early part of the setup period.

The positive pulse is applied before the rising ramp waveform and is maintained for the first half of the setup period.

And applying a negative pulse to the address electrode for a part of the set down period.

The negative pulse is applied at a time when the falling ramp waveform changes from positive polarity to negative polarity.

At least one of the positive pulse and the negative pulse is applied with different widths for each phosphor.

At least one of the positive and negative pulses is applied at a first width in a phosphor having a high dielectric constant and a second width wider than the first width at a phosphor having a low dielectric constant.

At least one or more of the positive pulse and the negative pulse are applied at different voltages for each phosphor.

At least one of the positive and negative pulses is applied as a first absolute voltage value in a phosphor having a high dielectric constant and a second absolute voltage value higher than the first absolute voltage in a phosphor having a low dielectric constant.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4 to 5.

4 is a waveform diagram illustrating a method of driving a plasma display panel according to an embodiment of the present invention.

Referring to FIG. 4, the PDP according to the embodiment of the present invention is driven by being divided into an initialization period for initializing the full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Rmap-up) causes a weak setup discharge in the cells of the full screen to form wall charges in the cells. The rising ramp waveform Ramp-up is raised to a voltage higher than the sustain voltage Vs.

During the set-down period, after the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y. It is applied at the same time. Ramp-down generates a weak setdown discharge in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges, and uniformly distributing the wall charges required for the address discharges in the cells of the full screen. Will remain. In practice, the ramp down ramps down to a negative voltage so that the desired wall charges remain in the discharge cells.

On the other hand, a positive pulse SP is applied to the address electrode X during the setup period. Such a positive pulse SP lowers the voltage difference between the address electrode X and the scan electrode Y during the setup period, thereby preventing a strong setup discharge between the address electrode X and the scan electrode Y. In general, light that inhibits contrast is produced by early discharging during the setup period. Therefore, the positive pulse SP applied to the address electrode X is applied at the same time as the rising ramp waveform Ramp-up applied to the scan electrode Y. As such, when the positive pulse SP is applied at the same time as the rising ramp waveform Ramp-up applied to the scan electrode Y, the amount of light emitted to the outside from the discharge cells is minimized at the beginning of the setup period. Therefore, contrast can be improved.

Here, the positive pulse SP applied to the address electrode X is applied to a width smaller than the rising ramp waveform Ramp-up, preferably only at the beginning of the setup period. As such, the positive pulse SP is applied only at the beginning of the setup period, so that sufficient wall charges may be formed in the discharge cells during the setup period. In other words, sufficient wall charges can be formed in the discharge cells by minimizing the amount of light emitted to the outside during the early part of the setup period, and then forming wall charges in the discharge cell during the second part of the setup period.

Meanwhile, in the present invention, the positive pulse SP may be applied before the rising ramp waveform Ramp-up. In other words, the positive pulse SP may be applied from before the rising ramp-up setup period up to the beginning of the setup period so as to overlap the application time of the rising ramp waveform Ramp-up.

In the address period, a negative scan pulse scan is sequentially applied to the scan electrodes Y, and a positive data pulse data is applied to the address electrodes X. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated in the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. Wall charges are generated in the cells selected by the address discharge.

On the other hand, the positive electrode DC voltage of the sustain voltage level Vs is supplied to the sustain electrodes Z during the set down period and the address period.

In the sustain period, sustain pulses sus are alternately applied to the scan electrodes Y and the sustain electrodes Z. FIG. Then, the cell selected by the address discharge is sustained in the form of surface discharge between the scan electrode Y and the sustain electrode Z each time the sustain pulse sus is applied while the wall voltage and the sustain pulse sus in the cell are added. Discharge occurs. Finally, after the sustain discharge is completed, an erase ramp waveform (erase) having a small pulse width is supplied to the sustain electrode Z to erase wall charges in the cell.

The PDP of the present invention driven as described above is controlled by generating a fine setup discharge between the scan electrode Y and the address electrode X by applying a positive pulse SP to the address electrode X during the setup period (actually It is possible to control the discharge from being generated between the scan electrode Y and the address electrode X by the voltage of the polarity pulse SP.) Contrast can be improved. In addition, sufficient wall charge can be formed in the discharge cells by applying the positive pulse SP only at the beginning of the setup period.

5 is a view showing a method of driving a plasma display panel according to another embodiment of the present invention.

Referring to FIG. 5, a PDP according to another embodiment of the present invention is driven by being divided into an initialization period for initializing a full screen, an address period for selecting a cell, and a sustain period for maintaining discharge of the selected cell.

In the initialization period, the rising ramp waveform Ramp-up is applied to all the scan electrodes Y simultaneously. This rising ramp waveform (Rmap-up) causes a weak setup discharge in the cells of the full screen to form wall charges in the cells. The rising ramp waveform Ramp-up is raised to a voltage higher than the sustain voltage Vs.

During the set-down period, after the rising ramp waveform Ramp-up is supplied, the falling ramp waveform Ramp-down falling at the positive voltage lower than the peak voltage of the rising ramp waveform Ramp-up is applied to the scan electrodes Y. It is applied at the same time. Ramp-down generates a weak setdown discharge in the cells, thereby eliminating unnecessary charges during wall charges and space charges generated by the setup discharges, and uniformly distributing the wall charges required for the address discharges in the cells of the full screen. Will remain. In practice, the ramp down ramps down to a negative voltage so that the desired wall charges remain in the discharge cells.

On the other hand, the positive pulse SP1 is applied to the address electrode X during the setup period. The positive pulse SP1 lowers the voltage difference between the address electrode X and the scan electrode Y during the setup period, thereby preventing a strong setup discharge between the address electrode X and the scan electrode Y. In general, light that inhibits contrast is produced by early discharging during the setup period. Therefore, in order to improve the contrast, the positive pulse SP1 is applied at the same time as the rising ramp waveform Ramp-up applied to the scan electrode Y. As such, when the positive pulse SP1 is applied at the same time as the rising ramp waveform Ramp-up applied to the scan electrode Y, the amount of light emitted to the outside from the discharge cells is minimized at the beginning of the setup period. Therefore, contrast can be improved.

Here, the positive pulse SP1 applied to the address electrode X is applied to a width smaller than the rising ramp waveform Ramp-up, preferably only at the beginning of the setup period. As such, the positive pulse SP1 is applied only at the beginning of the setup period, so that sufficient wall charges may be formed in the discharge cells during the setup period. In the present invention, the positive pulse SP1 may be applied before the rising ramp waveform Ramp-up. In other words, the positive pulse SP1 may be applied before the rising ramp waveform setup period up to the beginning of the setup period so that the positive pulse SP1 may be applied in an overlapping manner when the rising ramp waveform Ramp-up is applied. .

In addition, a negative pulse SP2 is applied to the address electrode X during the set-down period. In practice, the negative pulse SP2 applied to the address electrode X is applied at the time when the falling ramp waveform Ramp-down falls to the negative voltage. Such a negative pulse SP2 lowers the voltage difference between the address electrode X and the scan electrode Y during the set down period, thereby preventing a strong setdown discharge between the address electrode X and the scan electrode Y. . Therefore, in the present invention, the amount of light emitted during the setdown period can be minimized, thereby improving the contrast.

In the present invention, the widths of the positive pulse SP1 and / or the negative pulse SP2 can be set differently for each phosphor R, G, and B. FIG. In other words, the narrow width of the positive pulse SP1 and / or the negative pulse SP2 is set in the phosphor having a high dielectric constant, and the positive pulse SP1 and / or in the phosphor having a relatively low dielectric constant. By setting the width of the negative pulse SP2 wide, it is possible to ensure uniformity between the discharge cells.

In other words, the R and B phosphors generally have a higher permittivity than the G phosphors. Accordingly, a positive pulse SP1 having a first width and / or a negative pulse SP2 is applied to the R and B phosphors, and a positive pulse SP1 having a second width wider than the first width is applied to the G phosphor. ) And / or a negative pulse SP2 may be applied.

In addition, in the present invention, the uniformity between the discharge cells can be ensured by using the voltages of the positive pulse SP1 and / or the negative pulse SP2. In other words, a low voltage positive pulse SP1 and / or a negative pulse SP2 is applied to a phosphor having a high dielectric constant, and a high voltage positive pulse SP1 is applied to a phosphor having a relatively low dielectric constant. And / or uniformity between the discharge cells can be secured by applying the negative pulse SP2. In other words, the R and B phosphors generally have a higher permittivity than the G phosphors. Therefore, the positive pulse SP1 and / or the negative pulse SP2 having the first voltage are applied to the R and B phosphors, and the second phosphor value having an absolute voltage value higher than the first voltage is applied to the G phosphor. Positive pulse SP1 and / or negative pulse SP2 can be applied.

As described above, according to the driving method of the plasma display panel according to the present invention, the amount of light generated in the initialization period is minimized by applying the positive and / or negative pulses to the address electrode during the setup period and / or the set down period. It is possible to improve the contrast. In addition, since the positive and / or negative pulses are applied only to a part of the setup period and / or the set down period, sufficient wall charges necessary for the address period can be formed in the discharge cells.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 shows one frame of a typical plasma display panel.

3 is a waveform diagram showing a driving method of a conventional plasma display panel.

4 is a waveform diagram showing a method of driving a plasma display panel according to an embodiment of the present invention;

5 is a waveform diagram illustrating a method of driving a plasma display panel according to another embodiment of the present invention;

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 12Y, 12Z: transparent electrode

13Y, 13Z: bus electrode 14, 22: dielectric layer

16: protective film 18: lower substrate

20X: address electrode 24: partition wall

26: phosphor layer

Claims (9)

The rising ramp waveform is supplied to the plurality of scan electrodes during the setup period; Supplying a falling ramp waveform to the plurality of scan electrodes during the set-down period after the setup period; And applying a positive pulse to a plurality of address electrodes formed in a direction crossing the scan electrode during a part of the setup period. The method of claim 1, And the positive pulse is applied at the same time as the rising ramp waveform and held for the first half of the setup period. The method of claim 1, And wherein the positive pulse is applied before the rising ramp waveform to be maintained for the first half of the setup period. The method of claim 1, And applying a negative pulse to the address electrode during a part of the set down period. The method of claim 4, wherein And the pulse of negative polarity is applied at a time when the falling ramp waveform changes from positive polarity to negative polarity. delete delete delete delete