KR100625537B1 - Driving Method for Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel.

In the present invention, a method of driving a plasma display panel in which a plurality of subfields having different number of emission times is divided into a reset period, an address period, and a sustain period, and a predetermined voltage is applied to the X, Y, and Z electrodes in each period. In the resetting period of any one of the subfields, a first surface discharge step of applying a ramp waveform rising to the Y electrode to discharge between the Y electrode and the Z electrode, and applying a ramp waveform falling to the Y electrode to Y Any one of the first reset period and the subfield in which the second surface discharge step discharged between the electrode and the Z electrode and the opposite discharge step discharged between the Y electrode and the X electrode are sequentially performed by applying a ramp waveform falling to the Y electrode The reset section of the other subfields except for the subfield is configured to apply a ramp waveform that rises to the Z electrode to generate a first surface discharge step between the Y electrode and the Z electrode, and to descend to the Y electrode. And a second reset section in which an opposite discharge step occurring between the Y electrode and the X electrode is sequentially generated by applying the ramp waveform.

Plasma display panel, address discharge, jitter characteristic, driving method, reset section, subfield, driving waveform

Description

Driving method for plasma display panel {Driving Method for Plasma Display Panel}

1 is a perspective view showing the structure of a conventional three-electrode AC surface discharge type plasma display panel.

2 is a diagram illustrating a method of expressing image gradation of a conventional plasma display panel.

3 is a view illustrating a driving waveform according to a driving method of a conventional plasma display panel.

4 is a view showing another driving waveform in accordance with a conventional method for driving a plasma display panel.

5 is a view showing a driving waveform according to the driving method of the plasma display panel of the present invention.

6 is a view showing the amount of dark luminance generated in the reset section when driving the plasma display panel of the present invention.

7 is a view showing a comparison of the wall voltage state in the cell after the reset discharge according to the drive waveform of the present invention and the wall voltage state in the cell after the reset discharge according to the conventional drive waveform.

<Explanation of symbols for the main parts of the drawings>

10: upper substrate 11: scanning electrode

12: sustain electrode 13a, 13b: dielectric layer

14: protective film 20: lower substrate

21: partition 22: address electrode

23: phosphor layer

The present invention relates to a method for driving a plasma display panel, and more particularly, to a method for driving a plasma display panel which improves a contrast characteristic and a driving margin by improving a driving waveform supplied in a reset section of each subfield. .

In general, a plasma display panel emits a phosphor by ultraviolet rays of 147 nm generated when a discharge of He + Xe or Ne + Xe inert gas is emitted, thereby displaying an image including text or graphics.

1 is a perspective view showing the structure of a conventional three-electrode AC surface discharge type plasma display panel. As shown, the three-electrode alternating surface discharge type PDP includes a scan electrode (hereinafter, abbreviated as 'Y electrode') and a sustain electrode (hereinafter, abbreviated as 'Z electrode') formed on the upper substrate 10. And an address electrode 22 (hereinafter, abbreviated as 'X electrode') formed on the lower substrate 20. Each of the Y electrode 11 and the Z electrode 12 is formed of a transparent electrode, for example, indium tin oxide (ITO, 11a, 12a). Bus electrodes 11b and 12b are formed in each of the Y electrode 11 and the Z electrode 12 to reduce resistance. An upper dielectric layer 13a and a passivation layer 14 are stacked on the upper substrate 10 on which the Y electrode 11 and the Z electrode 12 are formed. Wall charges generated during plasma discharge are accumulated in the upper dielectric layer 13a. The protective layer 14 prevents damage to the upper dielectric layer 13a due to sputtering generated during plasma discharge, and increases emission efficiency of secondary electrons. As the protective film 14, magnesium oxide (MgO) is usually used.

Meanwhile, the lower dielectric layer 13b and the partition wall 21 are formed on the lower substrate 20 on which the X electrode 22 is formed, and the phosphor layer 23 is formed on the surfaces of the lower dielectric layer 13b and the partition wall 21. Is applied. The X electrode 22 is formed in the direction crossing the Y electrode 11 and the Z electrode 12. The partition wall 21 is formed in parallel with the X electrode 22 to prevent ultraviolet rays and visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 23 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe or Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 20 and the partition wall 21. A method of expressing image gradation of a conventional plasma display panel having such a structure will be described with reference to FIG. 2.

2 is a diagram illustrating a method of expressing image gray scale of a conventional plasma display panel. As shown, the image gradation of the plasma display panel is driven by dividing one frame into several subfields having different emission counts. Each subfield is divided into a reset section for uniformly generating a discharge, an address section for selecting a discharge cell, and a sustain section for implementing gray levels according to the number of discharges. For example, when displaying an image with 256 gray levels, a frame section (16.67 ms) corresponding to 1/60 second is divided into eight subfields. In addition, each of the eight subfields is divided into an address period and a sustain period. Here, the reset section and the address section of each subfield are the same for each subfield, while the sustain section increases at a rate of 2n (n = 0,1,2,3,4,5,6,7) in each subfield. do. Referring to the driving waveform according to the driving method of the plasma display panel as shown in FIG.

3 is a view illustrating a driving waveform according to a driving method of a conventional plasma display panel. As shown, the plasma display panel includes a reset section for initializing the entire screen, an address section for selecting a cell to be discharged, a sustain section for maintaining the discharge of the selected cell, and an erasing section for erasing wall charges in the discharged cell. Driven by dividing into.

In the reset section, the rising ramp waveform Ramp-up is simultaneously applied to all the Y electrodes (scan electrodes) in the setup section. This rising ramp waveform causes discharge to occur in the cells of the full screen. By this setup discharge, positive wall charges are accumulated on the X electrode (address electrode) and Z electrode (sustain electrode), and negative wall charges are accumulated on the Y electrode. During the set-down period, after the rising ramp waveform is supplied, the ramp ramp starts to fall from the positive voltage lower than the peak voltage of the rising ramp waveform and falls to a specific voltage level below the ground (GND) level voltage. By causing a slight erase discharge in the cells, the overcharged wall charge is sufficiently erased. By this set-down discharge, the wall charges such that the address discharge can be stably generated remain uniformly in the cells.

In the address period, the negative scan pulse Scan is sequentially applied to the Y electrodes, and the positive data pulse data is applied to the X electrode in synchronization with the scan pulse. As the voltage difference between the scan pulse and the data pulse and the wall voltage generated during the initialization period are added, an address discharge is generated in the cell to which the data pulse is applied. In the cells selected by the address discharge, wall charges such that discharge can occur when the sustain voltage Vs is applied are formed. The positive electrode voltage Vz is supplied to the Z electrode so as to reduce the voltage difference between the Y electrode during the set-down period and the address period so as to prevent erroneous discharge from the Y electrode.

In the sustain period, a sustain pulse Su is alternately applied to the Y electrode and the Z electrodes. In the cell selected by the address discharge, as the wall voltage and the sustain pulse in the cell are added, a sustain discharge, that is, a display discharge occurs between the Y electrode and the Z electrode every time the sustain pulse is applied.

After the sustain discharge is completed, a voltage of an erase ramp waveform (Ramp-ers) having a small pulse width and a low voltage level is supplied to the Z electrode to erase the wall charge remaining in the cells of the full screen.

The driving method of the plasma display panel to which the conventional driving waveform is applied has a problem in that a dark luminance is relatively high during driving, thereby deteriorating the contrast ratio of the panel. In order to solve such a problem, conventionally, the contrast of the driving waveform is supplied to improve the contrast. Referring to FIG.

4 is a view illustrating another driving waveform in accordance with a conventional method for driving a plasma display panel. Referring to FIG. 4, another driving waveform according to the driving method of the conventional plasma display panel may not be supplied with the erase pulse in the erase period. That is, the waveform supplied in the reset section of the first subfield is the same as the waveform supplied in the conventional reset section of FIG. However, the waveform supplied from the reset section except for the first subfield has a sinusoidal waveform, not a rising ramp waveform, rises to a predetermined value and starts to fall from a positive voltage lower than the peak voltage of the sinusoidal waveform to a falling ramp waveform. The waveform falls to a specific voltage level below the ground (GND) level voltage.

Such driving waveforms conventionally eliminate the wall charges in the cells sustained in the previous sustain period even when the erase pulses are not applied to the Z electrodes in the erasing section in order to equalize the distribution of the wall charges of the respective discharge cells. The wall charges of the cells that do not participate in the discharge are maintained in the interval, so that the wall charges in the entire discharge cells are uniformly distributed.

As a result, the dark brightness of the plasma display panel may be improved due to the discharge in the reset section, thereby improving the contrast characteristic.

On the other hand, in recent years, in order to increase the discharge efficiency of the plasma display panel, the content ratio of xenon (Xe) in the discharge cell is further increased. In this case, if the driving waveform according to the driving method of the conventional plasma display panel is applied, the interference of the X electrode with respect to the discharge between the Y electrode and the Z electrode is increased, thereby increasing the reset voltage during the discharge. In the case of applying to a large screen, there is a problem that the driving margin of the panel is deteriorated.

In addition, when the content ratio of xenon (Xe) in the discharge cell is further increased, the address jitter characteristic is deteriorated, which causes a problem that the sustain discharge becomes unstable in the subsequent sustain section.

In order to solve the above problems, the present invention provides a method of driving a plasma display panel which can improve driving margin of a panel by suppressing an increase of a reset voltage during discharge even if the content ratio of xenon (Xe) filled in a discharge cell is increased. The purpose is to provide.

Another object of the present invention is to provide a method of driving a plasma display panel in which the address discharge is stabilized to improve the jitter characteristic, and thus, the sustain discharge can be stably generated.

In order to achieve the above object, the present invention is characterized in that a plurality of subfields having different emission counts are divided into a reset section, an address section, and a sustain section, and in each section, a plasma expressing an image by applying a predetermined voltage to the X, Y, and Z electrodes. In the driving method of the display panel, the reset period of any one of the subfields is the first surface discharge step of discharging between the Y electrode and the Z electrode by applying a rising ramp waveform to the Y electrode, and the Y A second surface discharge step of discharging between the Y electrode and the Z electrode by applying a ramp waveform falling to the electrode; and an opposite discharge step of discharging between the Y electrode and the X electrode by applying a ramp waveform falling to the Y electrode; The first reset period and sequentially reset intervals of any other subfield except one of the subfields are raised to the Z electrode. The first surface discharge step is generated between the Y electrode and the Z electrode by applying a waveform, and the opposite discharge step is generated sequentially between the Y electrode and the X electrode by applying a ramp waveform falling to the Y electrode. And a second reset period.
The first reset period is a first subfield, and the second reset period is a second or subsequent subfield.
In the first reset period, a first surface discharge step and a first surface are discharged between the Y electrode and the Z electrode by applying a first rising lamp to the Y electrode and applying a ground (GND) level voltage to the Z electrode. After the discharging step, a second surface discharge step is applied to the Y electrode and the first falling lamp is lowered from a predetermined voltage value, and a sustain voltage Vs is applied to the Z electrode to discharge between the Y electrode and the Z electrode. After the two-surface discharge step, a second falling lamp is applied to the Y electrode which is maintained at a ground level voltage and is lowered after a predetermined point in time. A voltage lower than the sustain voltage Vs is applied to the Z electrode so that the Y electrode and A counter discharge step of discharging between the X electrodes.
The lowest value of the first falling lamp applied to the Y electrode in the second surface discharge step is characterized in that the negative voltage.
The lowest value of the second falling lamp applied to the Y electrode in the opposite discharge step is characterized in that the negative voltage lower than the lowest value of the first falling lamp supplied in the second surface discharge step.
The voltage below the sustain voltage Vs applied to the Z electrode in the opposite discharge step may include a voltage at the ground (GND) level.
In the second reset period, a ground level voltage is applied to the Y electrode, and a second rising lamp voltage having a smaller magnitude than that of the first rising ramp in the first reset period is applied to the Y electrode, thereby providing the Y electrode. After the first surface discharge step and the first surface discharge step discharged between the Z electrode and the first surface discharge step, a third falling lamp is applied to the Y electrode from the voltage value of the ground (GND) level and ground (GND) is applied to the Z electrode. And a counter discharge step in which a voltage of a level is applied and discharged between the Y electrode and the X electrode.
The second ramp lamp voltage applied to the Z electrode during the first surface discharge is a sustain voltage.
The lowest voltage value of the third falling lamp applied to the Y electrode during the first opposite discharge is a negative voltage of the second falling lamp in the first subfield.
In the first surface discharge step of the first reset section, the voltage of the ground (GND) level is applied to the Z electrode.
In the second surface discharge step of the first reset period, a sustain voltage Vs is applied to the Z electrode.
In the opposite discharge step of the first reset section, the second electrode is applied to the Y electrode at a ground level voltage, and a second falling lamp that falls after a predetermined time point is applied to the Z electrode, and a voltage lower than the sustain voltage Vs is applied to the Z electrode. It is characterized by.
In the first surface discharge step of the second reset section, a voltage of a ground (GND) level is applied.
In the opposite discharge step of the second reset section, a third falling lamp descending to the Y electrode is applied, and a voltage of ground (GND) level is applied to the Z electrode.

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Hereinafter, a method of driving a plasma display panel of the present invention will be described in detail with reference to the accompanying drawings.

5 is a view showing a driving waveform in accordance with the plasma display panel driving method of the present invention. First, the driving method of the plasma display panel according to the present invention supplies a predetermined driving waveform to a reset section for initializing the entire screen, an address section for selecting a cell to be discharged, and a sustain section for maintaining the discharge of the selected cell. Driven.

Accordingly, in the plasma display panel driving waveform of the present invention, different reset waveforms are supplied in the reset periods of the first subfield and the remaining subfields. That is, in the set-up period (SU) during the reset period of the first subfield, the voltage of the first ramp-up waveform is supplied to the Y (scan) electrode and set-down period (SD). The voltages of the first and second ramp-down waveforms are supplied to the first and second ramp-down waveforms. In addition, a sustain voltage is supplied to the Z (sustain) electrode in synchronization with a first falling ramp waveform applied to the Y (scan) electrode in a set down period (SD).

As such, the first rising ramp waveform supplied to the setup section SU in the first subfield causes a first surface discharge between the Y electrode and the Z electrode, and the first falling ramp waveform supplied during the setdown SD period is also Y electrode. A second surface discharge is caused between the and Z electrodes, and then, the supplied second falling ramp waveform causes the first opposite discharge between the Y electrode and the X electrode.

During the set-up period (SU ') in the reset period of the remaining subfields except the first subfield, a voltage of ground (GND) level is supplied to the Y (scan) electrode, and a second rise is performed to the Z (sustain) electrode. The voltage of the ramp waveform is supplied. In the Set Down (SD ') period, the voltage of the third ramp-down waveform is supplied to the Y (scan) electrode, and Y is set in the Set Down (SD') period of the Z (sustain) electrode. The voltage of the ground (GND) level is supplied in synchronization with the third falling ramp waveform applied to the (scanning) electrode.

As such, the second rising ramp waveform supplied during the setup (SU) period in the remaining subfields except for the first subfield causes the first surface discharge between the Y electrode and the Z electrode, and the third falling supply supplied in the setdown period (SD). The ramp waveform causes opposite discharge between the Y electrode and the X electrode.

The driving waveforms of the reset period in the remaining subfields except the first subfield and the first subfield described above will be described in more detail as follows.

<1st subfield>

When driving the plasma display panel according to the present invention, the first rising ramp waveform Ramp-up is simultaneously applied to all the Y electrodes Y1 to Yn during the setup period during the reset period of the first subfield, and the Z electrode The ground (GND) level voltage is applied to and maintained during the setup (SU) period. At this time, the first surface discharge is generated between the Y electrode and the Z electrode in the cells of the full screen by the first rising ramp waveform.

In the set down (SD) period, the first and second falling ramp waveforms are supplied to all the Y electrodes Y1 to Yn, and the square waves of a predetermined voltage are supplied to the Z electrodes Z1 to Zn in synchronization with the first falling lamp. Supplied.

The first falling ramp waveform begins to fall at a positive voltage lower than the peak voltage Vry of the first rising ramp waveform and falls to a specific voltage level (-Vmy) below the ground GND level. At this time, the lowest voltage value, which is the specific voltage level (-Vmy) of the first falling lamp, preferably has a negative voltage value so that sufficient surface discharge can occur between the Y electrode and the Z electrode. In addition, a predetermined voltage is applied to the Z electrode to be maintained during the set-down (SD1) period during which the voltage of the first falling lamp is supplied to generate a weak second surface discharge between the Y electrode and the Z electrode. The formed wall charges are partially erased. In this case, the predetermined voltage applied to the Z electrode is preferably a sustain voltage (Vs) for causing surface discharge by providing a sufficient potential difference between the Y electrode and the Z electrode.

The second falling ramp waveform rises from the end of the first falling ramp waveform, i.e., at a specific voltage level (-Vmy) to the ground (GND) level, maintains the ground (GND) level for a predetermined time, and then returns to the ground (GND) level. A voltage (-Vny) having a magnitude smaller than the following specific voltage level (-Vmy) is lowered. At this time, the lowest voltage value, which is the voltage of the second falling lamp (-Vny), is greater than the lowest value of the first falling lamp supplied at the time of the second surface discharge so that sufficient opposite discharge occurs between the Y electrode and the X electrode to completely eliminate the wall charge. It is desirable to have a lower negative voltage. In addition, a voltage smaller than a specific voltage (-Vmy) that was applied during the set-down SD1 period during which the first falling ramp waveform is applied to the Z electrode is applied to generate a counter discharge between the Y electrode and the X electrode in the cells. At this time, the voltage applied to the Z electrode may be a voltage of the ground GND level or a predetermined positive voltage Vz.

As a result, the distribution of the wall charges in the discharge cells is even, thereby enabling stable address discharge in the address period thereafter.

On the other hand, the reason why the second falling ramp waveform applied to the Y electrode is rapidly raised to the ground (GND) level at the end of the first falling ramp waveform and then supplied is due to the sudden drop in the voltage applied to the Z electrode. This is to prevent the instantaneous drop in the voltage of the Y electrode due to the coupling between the Y electrode and the Z electrode when the applied voltage is continuously dropped.

<Subfields other than the first subfield>

When driving the plasma display panel according to the present invention, the driving waveform supplied to the reset period of the remaining subfields except for the first subfield is first applied to all the Y electrodes Y1 to Yn in the setup period SU '. The voltage of the ground GND level is supplied and maintained, and the voltage Ve of the second rising ramp waveform smaller than the first rising ramp waveform supplied to the reset period of the first subfield is applied to the Z electrode. At this time, the cells not participating in the discharge in the sustain period of the first subfield are maintained without any discharge, and the cells participating in the discharge in the sustain period of the first subfield are the Y electrode and the Z electrode by the second rising ramp waveform. The first surface discharge is generated between them and the wall charge between the Y electrode and the Z electrode is erased to some extent.

On the other hand, although the voltage Ve of the second rising ramp waveform may be a voltage capable of causing surface discharge between the Y electrode and the Z electrode, the sustain voltage Vs is preferably supplied. This is to use the same voltage source used for sustain discharge.

In the set-down period SD ', the third falling ramp waveform is supplied to all the Y electrodes Y1 to Yn, and the Z electrodes Z1 to Zn maintain the ground GND.

The third falling ramp waveform starts to fall at the ground (GND) level and falls to a specific voltage level (-Vny) below the ground (GND) level. At this time, it is preferable that the lowest voltage value, which is the specific voltage level (-Vny) of the third falling lamp, has a negative voltage value that can sufficiently eliminate wall charges by generating sufficient counter discharge between the Y electrode and the X electrode. That is, it has the same value as the negative voltage of the second falling lamp in the first subfield.

As described above, when the plasma display panel is driven according to the present invention, by supplying a predetermined reset driving waveform in the reset section of all the subfields, the wall charges accumulated on the electrodes can be made uniform, thereby enabling stable discharge in the address section. .

Meanwhile, in the plasma display panel driving method according to the present invention, the dark luminance generated in the reset section is as follows.

FIG. 6 is a diagram illustrating an amount of dark luminance generated in a reset section when driving the plasma display panel of the present invention. FIG. 6 (a) shows the dark luminance amount in the reset section of the first subfield, and FIG. 6 (b) shows the dark luminance amount in the reset section of the remaining subfields except for the first subfield. As shown, the dark luminance amount in the reset section of the first subfield is similar to the dark luminance amount according to the conventional driving waveform, but the dark luminance amount in the reset section of the remaining subfields except the first subfield is equal to the first subfield. It can be seen that the dark intensity characteristics are smaller than when a high voltage rising ramp waveform is supplied. That is, the plasma display panel of the present invention reduces the amount of dark brightness during driving, thereby improving contrast characteristics.

Figure 7 compares the wall voltage state in the cell after the reset discharge according to the drive waveform of the present invention and the wall voltage state in the cell after the reset discharge according to the conventional drive waveform. Referring to FIG. 7, (a) the cell voltage (Vc, zy) between the Y electrode and the Z electrode after the reset discharge according to the conventional driving waveform satisfies the sustain surface discharge voltage (Vf, zy), and the cell between the Y electrode and the X electrode The voltages Vc and xy form wall voltages that satisfy the addressing counter discharge voltages Vf and xy. On the contrary, (b) after the reset discharge according to the driving waveform of the present invention, the cell voltage (Vc, xy) between the Y electrode and the X electrode has a wall voltage satisfying the addressing opposing discharge voltage (Vf, xy), but the Y electrode and Z The inter-electrode cell voltages Vc and zy are formed at a voltage smaller than the sustain surface discharge voltage Vf and zy.

On the other hand, since the cell voltages Vc and zy are before the specific voltage Vz is applied in the address period, the cell voltages Vc and zy are smaller than the sustain surface discharge voltages Vf and zy by the specific voltage Vz, thereby providing a margin equal to the specific voltage Vz. Secured. The specific voltage Vz is determined differently according to the characteristics of the panel, but preferably has a value of 0V to sustain voltage Vs.

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive.

The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

As described above, the driving method of the plasma display panel according to the present invention improves the driving waveform supplied to the reset section of each subfield, makes the wall charge uniform, thereby improving the jitter characteristic in the address section, and at the same time, a high driving margin. There is an effect that can be secured.

Claims (14)

A method of driving a plasma display panel in which a plurality of subfields having different emission counts are divided into a reset period, an address period, and a sustain period, and a predetermined voltage is applied to the X, Y, and Z electrodes in each period. The reset period of any one of the subfields is A first surface discharge step of discharging between the Y electrode and the Z electrode by applying a ramp waveform rising to the Y electrode, and a discharge of the discharge between the Y electrode and the Z electrode by applying a ramp waveform falling to the Y electrode; A first reset section in which a two-side discharge step and a counter-discharge step discharged between the Y electrode and the X electrode are sequentially generated by applying a ramp waveform falling to the Y electrode; The reset section of the other subfield except one of the subfields is A first surface discharge step generated between the Y electrode and the Z electrode by applying a ramp waveform rising to the Z electrode, and a counter discharge generated between the Y electrode and the X electrode by applying a ramp waveform falling to the Y electrode; And a second reset section in which steps occur sequentially. The method of claim 1, And the first reset section is a first subfield, and the second reset section is a second and subsequent subfields. The method of claim 2, The first reset period is A first surface discharge step of discharging between the Y electrode and the Z electrode by applying a first rising lamp to the Y electrode and applying a ground (GND) level voltage to the Z electrode; After the first surface discharge step, a first lowering lamp is applied to the Y electrode to lower the voltage from a predetermined voltage value, and a sustain voltage (Vs) is applied to the Z electrode to discharge the second surface discharge between the Y electrode and the Z electrode. step; And After the second surface discharge step, a second falling lamp that is maintained at a ground level voltage is applied to the Y electrode and is lowered after a predetermined point of time, and a voltage less than the sustain voltage Vs is applied to the Z electrode so that the Y is applied. Opposite discharge step discharged between electrode and X electrode Method of driving a plasma display panel comprising a. The method of claim 3, wherein And the lowest value of the first falling lamp applied to the Y electrode in the second surface discharge step is a negative voltage. The method of claim 3, wherein The lowest value of the second falling lamp applied to the Y electrode in the opposite discharge step is a negative voltage lower than the lowest value of the first falling lamp supplied in the second surface discharge step. . The method of claim 3, wherein And a voltage below the sustain voltage (Vs) applied to the Z electrode in the opposite discharge step comprises a voltage at ground (GND) level. The method of claim 2, The second reset period is A voltage of ground (GND) level is applied to the Y electrode, and a second rising lamp voltage having a magnitude smaller than that of the first rising ramp in the first reset period is applied to the Z electrode to discharge between the Y electrode and the Z electrode. A first surface discharge step; After the first surface discharge step, a third falling lamp is applied to the Y electrode, which is lowered from the voltage value of the ground (GND) level, and a voltage of the ground (GND) level is applied to the Z electrode, thereby providing the Y electrode and the X. Opposite discharge step discharged between electrodes Method of driving a plasma display panel comprising a. The method of claim 7, wherein And the second rising ramp voltage applied to the Z electrode during the first surface discharge is a sustain voltage. The method of claim 7, wherein And the lowest voltage value of the third falling lamp applied to the Y electrode during the first opposite discharge is a negative voltage of the second falling lamp in the first subfield. The method of claim 1, And a ground (GND) level voltage is applied to the Z electrode during the first surface discharge step of the first reset section. The method of claim 1, And a sustain voltage (Vs) is applied to the Z electrode during the second surface discharge step of the first reset section. The method of claim 1, In the opposite discharge step of the first reset section, the Y electrode maintains the ground level voltage, and a second falling lamp that descends from a predetermined time point is applied, and a voltage lower than the sustain voltage Vs is applied to the Z electrode. A driving method of a plasma display panel, characterized in that. The method of claim 1, And a ground (GND) level voltage is applied during the first surface discharge step of the second reset section. The method of claim 1, And a third falling lamp applied to the Y electrode and a voltage of ground (GND) level is applied to the Z electrode during the opposite discharge step of the second reset section.

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