KR100493617B1 - Method of driving plasma display panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel that can shorten an address period.

According to an exemplary embodiment of the present invention, a method of driving a plasma display panel includes supplying a first driving waveform to scan electrodes during a first address period of at least one subfield positioned at an initial portion of a frame, and performing at least one subfield. And supplying a second driving waveform different from the first driving waveform to the scan electrodes during the second address period of the remaining subfields except the field. The first driving waveform includes scan pulses simultaneously supplied to at least two scan electrodes during the first address period and alternately supplied in subfields positioned at the beginning.

Description

Driving method of plasma display panel {METHOD OF DRIVING PLASMA DISPLAY PANEL}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method of driving a plasma display panel that can shorten an address period.

Plasma Display Panels (hereinafter referred to as "PDPs") are characterized by emitting phosphors by 147 nm ultraviolet rays generated during discharge of inert mixed gases such as He + Xe, Ne + Xe and He + Ne + Xe. An image containing graphics is displayed. Such a PDP is not only thin and easy to enlarge, but also greatly improved in quality due to recent technology development. In particular, the three-electrode AC surface discharge type PDP has advantages of low voltage driving and long life because wall charges are accumulated on the surface during discharge and protect the electrodes from sputtering caused by the discharge.

Referring to FIG. 1, a discharge cell of a three-electrode AC surface discharge type PDP includes a scan electrode Y and a sustain electrode Z formed on the upper substrate 10, and an address electrode formed on the lower substrate 18. X). Each of the scan electrode Y and the sustain electrode Z has a line width smaller than that of the transparent electrodes 12Y and 12Z and the transparent electrodes 12Y and 12Z, and the metal bus electrode 13Y is formed at one edge region of the transparent electrode. , 13Z).

The transparent electrodes 12Y and 12Z are usually formed on the upper substrate 10 by indium tin oxide (hereinafter, referred to as “ITO”). The metal bus electrodes 13Y and 13Z are usually formed of metals such as chromium (Cr) and formed on the transparent electrodes 12Y and 12Z to reduce voltage drop caused by the transparent electrodes 12Y and 12Z having high resistance. The upper dielectric layer 14 and the passivation layer 16 are stacked on the upper substrate 10 having the scan electrode Y and the sustain electrode Z side by side. In the upper dielectric layer 14, wall charges generated during plasma discharge are accumulated. The protective layer 16 prevents damage to the upper dielectric layer 14 due to sputtering generated during plasma discharge and increases emission efficiency of secondary electrons. As the protective film 16, magnesium oxide (MgO) is usually used. The lower dielectric layer 22 and the partition wall 24 are formed on the lower substrate 18 on which the address electrode X is formed, and the phosphor layer 26 is coated on the surfaces of the lower dielectric layer 22 and the partition wall 24. The address electrode X is formed in the direction crossing the scan electrode Y and the sustain electrode Z. The partition wall 24 is formed in parallel with the address electrode X to prevent the 1 ultraviolet ray and the visible light generated by the discharge from leaking to the adjacent discharge cells. The phosphor layer 26 is excited by ultraviolet rays generated during plasma discharge to generate visible light of any one of red, green, and blue. An inert mixed gas such as He + Xe, Ne + Xe, and He + Ne + Xe for discharging is injected into the discharge space of the discharge cells provided between the upper and lower substrates 10 and 18 and the partition wall 24.

These discharge cells are arranged in the form of a matrix as shown in FIG. In FIG. 2, the discharge cell 1 is provided at the intersection of the scan electrode lines Y1 to Ym, the sustain electrode line Z, and the address electrode lines X1 to Xn. The scan lines Y1 to Ym are sequentially driven, and the sustain electrode line Z is commonly driven. The address electrode lines X1 to Xn are driven by being divided into odd-numbered lines and even-numbered lines to increase driving characteristics.

As a driving device for driving the PDP, a scan (Y) driver 32 for driving the scan electrode lines Y1 to Ym and a sustain (Z) driver 34 for driving the sustain electrode line Z are provided. And an address X driver 36 for driving the address electrode lines X1 to Xn.

The three-electrode AC surface discharge type PDP is driven by dividing one frame into several subfields having different emission counts in order to realize gray levels of an image. Each subfield is further divided into a reset period for uniformly generating discharge, an address period for selecting a discharge cell, and a sustain period for implementing gray levels according to the number of discharges. For example, when the image is to be displayed with 256 gray levels, the frame period (16.67 ms) corresponding to 1/60 second is divided into eight subfields SF1 to SF8. In addition, each of the eight subfields SF1 to SF8 is divided into a reset and an address period and a sustain period. Here, the reset and address periods of each subfield are the same for each subfield, while the sustain period increases at a rate of 2 ⁿ (n = 0,1,2,3,4,5,6,7) in each subfield. do. As described above, since the sustain period is changed in each subfield, gray levels of an image can be realized.

The first subfield SF1 included in one frame shown in FIG. 3 sustains discharge cells other than the discharge cells selected by the reset period, the address period for turning off the selected discharge cell, and the address discharge. It is divided into sustain periods. The second to eighth subfields SF2 to SF8 are address periods for turning off selected discharge cells without a full writing period (reset period) in which the full screen is lit, and discharge cells selected by address discharge. The cells are divided into sustain periods for sustain discharge of discharge cells other than these.

4 is a waveform diagram illustrating a method of driving a plasma display panel according to the related art.

Referring to FIG. 4, the first subfield SF1 included in one frame of the PDP is divided into a reset period RPD, an address period APD, and a sustain period SPD.

In the reset period RPD, the reset pulse RP is supplied to the scan electrode Y. The reset pulse RP has a form of ramp wave in which the voltage increases when set up and the voltage decreases when set down. In the set-up, reset discharge is generated to form wall charge in the upper dielectric layer 14. Subsequently, the charged voltage is partially erased by the decreasing voltage during set down so that the wall charge is reduced enough to help the next address discharge without causing an erroneous discharge. In order to reduce the wall charge, a positive DC voltage is supplied to the sustain electrode Z when the reset pulse RP is set down. Since the reset pulse RP is supplied in a gradually decreasing form with respect to the positive DC voltage, the scan electrode Y becomes a negative polarity relative to the sustain electrode Z at the time of set down, that is, the polarity is reduced. This inversion reduces the wall charges generated during set-up.

In the address period APD, a scan pulse having a negative scan voltage Vy is supplied to the scan electrode Y, and a data pulse data is supplied to the address electrode X. Discharge will occur. The wall charge formed by this address discharge is maintained for the period during which the other discharge cells are addressed.

In the sustain period SPD, the triggering pulse TP is supplied to the scan electrode Y at the start so that the sustain discharge is started in the discharge cells 1 in which the wall charges are sufficiently formed in the address period APD. Subsequently, sustain pulses SUSPz and SUSPy corresponding to the sustain voltage Vs are alternately supplied to the sustain electrode Z and the scan electrode Y to maintain the sustain discharge during the sustain period SPD.

In the erase period EPD subsequent to the sustain period SPD, the discharge pulse EP is supplied to the sustain electrode Z to stop the discharge. The erasing pulse EP has a ramp wave shape so that the light emission size is small, or a short pulse width of about 1 ms for the discharge erasing. The charged particles are erased by the short erase discharge by the erase pulse EP to stop the discharge.

In the driving method of the plasma display panel as described above, the scan pulse supplied to the scan electrode Y should have a pulse width of approximately 3 mu s or more to form sufficient wall charge in the discharge cell.

If the PDP has a resolution of VGA (Video Graphics Array), it has a total of 480 scan lines. Therefore, when the selective writing method includes eight subfields within one frame period (16.67 ms), the total required address period (APD) in one frame requires 11.52 ms. In contrast, the sustain period SPD is allocated 3.05 ms in consideration of the vertical synchronization signal Vsync. Here, the address period APD is calculated at 3 mu s (pulse width of scan pulse) x 480 lines x 8 (number of subfields) per frame. The sustain period (SPD) is an address period (APD) of 11.52 ms, a one-time reset period (RPD) of 0.3 ms, an erasing period (EPD) of 100 μs × 8 subfields, and 1 ms vertical synchronization at one frame time (16.67 ms). It is 3.05ms which is the remaining period minus the signal (Vsync) margin (16.67ms-11.52ms-0.3ms-1ms-0.8ms).

As such, sufficient sustain period (SPD) cannot be secured, which makes it difficult to express gray scales. That is, in the driving method of the plasma display panel according to the related art, an address discharge occurs in one cell at a time because negative scan pulses (-) are supplied sequentially according to the scan electrode lines (Y1 to Ym). do. Therefore, the address period APD is too long, making it difficult to secure a sufficient sustain period SPD for expressing gray scale.

Accordingly, it is an object of the present invention to provide a method of driving a PDP that can shorten an address period.

According to an exemplary embodiment of the present invention, a method of driving a PDP may include supplying a first driving waveform to scan electrodes during a first address period of at least one subfield located at the beginning of a frame, and supplying the at least one subfield. And supplying a second driving waveform different from the first driving waveform to the scan electrodes during the second address period of the remaining subfields. The first driving waveform includes scan pulses simultaneously supplied to at least two scan electrodes during the first address period and alternately supplied in subfields positioned at the beginning.

The first driving waveform is supplied during the first address period of the first to third subfields. Scan pulses are sequentially supplied to the scan electrodes during the second address period during which the second driving waveform is supplied.

The first driving waveform is supplied during the first address period of the first and second subfields.

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During the first address period of the first subfield, scan pulses are simultaneously supplied to the nth (n is odd) and n + 1th scan electrodes.

During the first address period of the second subfield, scan pulses are simultaneously supplied to the n + 1 (n is odd) and n + 2 th scan electrodes.

The scan pulse is simultaneously supplied to the n + 1 th (n is a multiple of 3 including 0) th and n + 2 th scan electrodes during the first address period of the first subfield. Pulses are supplied.

The n + 4th scan electrode after a scan pulse is simultaneously supplied to the n + 2 (n is a multiple of 3 including 0) th and n + 3 th scan electrodes during the first address period of the second subfield. Scan pulses are supplied.

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Scan pulses are simultaneously supplied to the n th (n is odd) th and n + 1 th scan electrodes during the first address period of the first subfield of the j (j is a natural number) th frame.

During the first address period of the second subfield, scan pulses are simultaneously supplied to the n + 1th (n is odd) and nth + 2th scan electrodes.

Scan pulses are simultaneously supplied to the n + 1 (n is odd) and n + 2 th scan electrodes during the first address period of the first subfield of the j + 1 (j is natural number) frame.

During the first address period of the second subfield, scan pulses are simultaneously supplied to the nth (n is odd) and n + 1th scan electrodes.

Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 5 to 9.

5 is a diagram illustrating a method of driving one subfield included in one frame according to the first embodiment of the present invention.

Referring to FIG. 5, the first subfield SF1 included in one frame of the PDP according to the first embodiment of the present invention is divided into a reset period RPD, an address period APD, and a sustain period SPD. do.

In the reset period RPD, the reset pulse RP is supplied to the scan electrode Y. The reset pulse RP has a form of ramp wave in which the voltage increases when set up and the voltage decreases when set down. In the set-up, reset discharge is generated to form wall charge in the upper dielectric layer 14. Subsequently, the charged voltage is partially erased by the decreasing voltage during set down so that the wall charge is reduced enough to help the next address discharge without causing an erroneous discharge. In order to reduce the wall charge, a positive DC voltage is supplied to the sustain electrode Z when the reset pulse RP is set down. Since the reset pulse RP is supplied in a gradually decreasing form with respect to the positive DC voltage, the scan electrode Y becomes a negative polarity relative to the sustain electrode Z at the time of set down, that is, the polarity is reduced. This inversion reduces the wall charges generated during set-up.

In the address period APD, a scan pulse is simultaneously supplied to two or more scan lines Y, and a data pulse data synchronized with the scan pulse is supplied to the address electrode X. In detail, the first scan line Y1, the second scan line Y2, the third scan line Y3, and the fourth scan during the address period APD of at least one subfield located at the beginning of the frame. Scan pulses are simultaneously supplied in the order of the line Y4, the fifth scan line Y5 and the sixth scan line Y6. The scan pulses are sequentially supplied to the scan electrodes Y during the address period APD of the remaining subfields except for at least one subfield. As a result, the entire address period APD of one frame can be shortened by shortening the address period APD of the subfield located at the beginning of the frame. That is, during the address period APD of at least one subfield located at the beginning of one frame, scan pulses are simultaneously supplied to the nth (n is odd) and nth + 1th scan electrodes Y, thereby providing overall The address period APD can be shortened.

In the sustain period SPD, the triggering pulse TP is supplied to the scan electrode Y at the start so that the sustain discharge is started in the discharge cells 1 in which the wall charges are sufficiently formed in the address period APD. Subsequently, sustain pulses SUSPz and SUSPy corresponding to the sustain voltage Vs are alternately supplied to the sustain electrode Z and the scan electrode Y to maintain the sustain discharge during the sustain period SPD.

In the erase period EPD subsequent to the sustain period SPD, the discharge pulse EP is supplied to the sustain electrode Z to stop the discharge. The erasing pulse EP has a ramp wave shape so that the light emission size is small, or a short pulse width of about 1 ms for the discharge erasing. The charged particles are erased by the short erase discharge by the erase pulse EP to stop the discharge.

FIG. 6 is a waveform diagram illustrating driving waveforms between the subfields shown in FIG. 5 and adjacent subfields.

Referring to FIG. 6, a subfield included in one frame of the PDP according to the first embodiment of the present invention is driven by being divided into a reset period RPD, an address period APD, and a sustain period SPD.

In the reset period RPD, the reset pulse RP is supplied to the scan electrode Y. The reset pulse RP has a form of ramp wave in which the voltage increases when set up and the voltage decreases when set down. In the set-up, reset discharge is generated to form wall charge in the upper dielectric layer 14. Subsequently, the charged voltage is partially erased by the decreasing voltage at set-down so that the wall charge is reduced enough to help the next address discharge without causing an erroneous discharge.

In the address period APD, a scan pulse is simultaneously supplied to two or more scan lines Y, and a data pulse data synchronized with the scan pulse is supplied to the address electrode X. That is, by shortening the address period APD of the subfield located at the beginning of the frame, the entire address period APD of one frame can be shortened.

In the sustain period SPD, sustain pulses SUSPz and SUSPy corresponding to the sustain voltage Vs are alternately supplied to the sustain electrode Z and the scan electrode Y so that the sustain discharge is maintained during the sustain period SPD. do.

In the erase period EPD subsequent to the sustain period SPD, the discharge pulse EP is supplied to the sustain electrode Z to stop the discharge.

Meanwhile, a scan pulse is simultaneously supplied to two or more scan lines Y in the address period APD, and a data pulse data synchronized with the scan pulse is supplied to the address electrode X. That is, in the first subfield SF1, the first scan line Y1, the second scan line Y2, the third scan line Y3, the fourth scan line Y4, and the fifth scan line Y5 At the same time in the order of the sixth scan line (Y6), scan pulses falling down to the negative scan voltage (-Vye) are supplied, and data synchronized with the scan pulses are provided to the address electrodes (X). Pulse data is supplied. At this time, when one scan pulse of negative polarity (-) is supplied, two scan lines are turned on, so that the same data is simultaneously supplied to each of the two scan lines. That is, since one scan pulse is simultaneously supplied to two scan lines, the address period APD can be reduced. However, since the same data is supplied every two scan lines, the image quality may be degraded. Therefore, in the second subfield SF2, the second scan line Y2, the third scan line Y3, the fourth scan line Y4, and the fifth scan line Y5 are staggered from the first subfield SF2. ), The sixth scan line Y6 and the seventh scan line Y7 are simultaneously supplied with a scan pulse that drops to the negative scan voltage (-Vye) and the address electrodes X The data pulse (data) synchronized with the scan pulse (scan) is supplied to. That is, the first subfield SF1 and the scan line are staggered so that they are simultaneously scanned. In other words, data of the second scan line Y2 of the first subfield SF1 and data of the second scan line Y2 of the second subfield SF2 are supplied differently. In more detail, during the address period APD of the first subfield SF1 of one frame, a scan pulse is simultaneously supplied to the nth (n is odd) and the n + 1th scan electrodes Y. The scan pulse is simultaneously supplied to the n + 1th and n + 2th scan electrodes Y of the address period APD of the second subfield SF2. Scan pulses are sequentially supplied to the scan electrodes Y during the address period APD of the subfield after the second subfield SF2. Accordingly, not only the overall address period APD of one frame is shortened, but also the scan pulses are alternately supplied to the scan electrodes Y for each subfield, thereby preventing deterioration in image quality due to data sharing.

FIG. 7 is a diagram illustrating that data is shared by being alternately addressed for each subfield according to the driving waveform of FIG. 6 of the present invention.

Referring to FIG. 7, data is alternately supplied in the same scan line of the N + 1 th subfield SF _{N +1} and the next subfield, the N + 2 th subfield SF _{N +2} . It is done. That is, the N + 1 th subfield SF _{N +1} is addressed so that data is simultaneously input in two lines in the order of Ym and Ym + 1, Ym + 2 and Ym + 3. At this time, since Ym shares data of "1A" with Ym + 1, the resolution is degraded because the two lines have no luminance difference. In the next subfield, the N + 2th subfield SF _{N +2} , Ym + 1 and Ym + 2, Ym + 3, and Ym + 4 are staggered from the N + 1th subfield SF _{N +1} . To address two lines of data at the same time. At this time, Ym + 1 shares data of “2A” with Ym + 2. Accordingly, the data of the Ym + 1 th scan line of the first subfield SF1 becomes "1A", and the data of the Ym + 1 th scan line of the second subfield SF2 becomes "2A". That is, since data is shared alternately with two lines for each subfield, data errors due to line sharing can be distributed up and down, thereby reducing image quality deterioration caused by simultaneously scanning a plurality of lines with the same data.

For example, when the PDP is VGA resolution, the number of scan lines is 480 lines. According to the present invention, since one data is simultaneously input to two scan lines, the number of lines in the VGA class has 240 lines, which is half of them. That is, they are simultaneously scanned in the order of Y1 and Y2, Y3 and Y4, Y5 and Y6. Therefore, since the two lines share one data, the resolution is lowered than the 480 lines, and the image quality is deteriorated. Therefore, the next subfield is simultaneously scanned in the order Y1, Y2 and Y3, and Y4 and Y5. In other words, the address is crossed between the lines in the previous subfield. Therefore, since two scan lines are scanned at the same time, the address period APD is reduced, and the scan lines are alternately addressed for each subfield, thereby reducing the image quality deterioration caused when two lines are simultaneously scanned with the same data.

8 (a) and (b) are diagrams illustrating a driving method for each frame according to the second embodiment of the present invention.

8 (a) and (b), the first subfield SF1 included in the first frame of the PDP according to the second embodiment of the present invention includes a reset period RPD, an address period APD, and The driving is divided into the sustain period SPD.

In the reset period RPD, the reset pulse RP is supplied to the scan electrode Y. The reset pulse RP has a form of ramp wave in which the voltage increases when set up and the voltage decreases when set down. In the set-up, reset discharge is generated to form wall charge in the upper dielectric layer 14. Subsequently, the charged voltage is partially erased by the decreasing voltage at set-down so that the wall charge is reduced enough to help the next address discharge without causing an erroneous discharge.

In the address period APD, a scan pulse is simultaneously supplied to two or more scan lines Y, and a data pulse data synchronized with the scan pulse is supplied to the address electrode X. That is, by shortening the address period APD of the subfield located at the beginning of the frame, the entire address period APD of one frame can be shortened.

In the sustain period SPD, sustain pulses SUSPz and SUSPy corresponding to the sustain voltage Vs are alternately supplied to the sustain electrode Z and the scan electrode Y so that the sustain discharge is maintained during the sustain period SPD. do.

In the erase period EPD subsequent to the sustain period SPD, the discharge pulse EP is supplied to the sustain electrode Z to stop the discharge.

Meanwhile, in the address period APD, as shown in FIG. 8A, the first subfield SF11 of the first frame includes the first scan line Y1, the second scan line Y2, and the third scan line. Scan pulses falling to the negative scan voltage (-Vye) at the same time in the order of (Y3), the fourth scan line (Y4), the fifth scan line (Y5), and the sixth scan line (Y6). Is supplied. The second subfield SF12 has a second scan line Y2, a third scan line Y3, a fourth scan line Y4, and a fifth scan line Y5 so as to cross the first subfield SF11. ), The sixth scan line Y6 and the seventh scan line Y7 are simultaneously supplied with a scan pulse that drops to the negative scan voltage -Vye. From the subsequent subfields, scan pulses are sequentially supplied to the scan lines. Therefore, the address period APD can be reduced by a subfield in which one scan pulse is simultaneously supplied for two initial scan lines. However, resolution is reduced because the two lines share data. Accordingly, as shown in FIG. 8B, the first subfield SF21 of the second frame is staggered from the second scanline Y2 and the third scanline so as to cross the first subfield SF11 of the first frame. (Y3), the fourth scan line (Y4) and the fifth scan line (Y5), the sixth scan line (Y6) and the seventh scan line (Y7) simultaneously to the negative scan voltage (-Vye) A descending scan pulse is supplied. The second subfield SF22 of the second frame is intersected with the second subfield SF12 of the first frame and the first subfield SF21 of the second frame by the first scan line Y1 and the second. Scan voltage of negative polarity (-) at the same time in order of scan line Y2, third scan line Y3 and fourth scan line Y4, fifth scan line Y5, and sixth scan line Y6 The scan pulse descending to Vye is supplied. Subsequently, a scan pulse is sequentially supplied to the scan line Y from the subfield. In other words, during the address period APD of the first subfield SFj1 of the jth frame (j is a natural number), scan pulses are applied to the nth (n is odd) th and n + 1th scan electrodes Y. ) Are supplied simultaneously, and the scan pulse is applied to the n + 1th and n + 2th scan electrodes Y so as to cross the first subfield SFj1 during the address period APD of the second subfield SFj2. (scan) is supplied at the same time. The n + 1 th (n is an odd number) th and the n + 2 th scans during the address period APD of the first subfield SF1 of the j th frame of the j th frame are staggered from the j th frame. The scan pulses are simultaneously supplied to the electrode Y, and the nth and n + 1th scan electrodes are crossed with the first subfield SF1 during the address period APD of the second subfield SF2. Scan pulses are simultaneously supplied to (Y). Therefore, not only the overall address period APD of one frame can be shortened, but also the scan pulses are alternately supplied to the scan electrodes Y for each frame, thereby preventing deterioration in image quality due to data sharing. .

9 is a diagram illustrating a method of driving a plasma display panel according to a third embodiment of the present invention.

Referring to FIG. 9, a subfield included in one frame of the PDP according to the third embodiment of the present invention is driven by being divided into a reset period RPD, an address period APD, and a sustain period SPD.

In the reset period RPD, the reset pulse RP is supplied to the scan electrode Y. The reset pulse RP has a form of ramp wave in which the voltage increases when set up and the voltage decreases when set down. In the set-up, reset discharge is generated to form wall charge in the upper dielectric layer 14. Subsequently, the charged voltage is partially erased by the decreasing voltage at set-down so that the wall charge is reduced enough to help the next address discharge without causing an erroneous discharge.

In the address period APD, a scan pulse is simultaneously supplied to two or more scan lines Y, and a data pulse data synchronized with the scan pulse is supplied to the address electrode X. That is, by shortening the address period APD of the subfield located at the beginning of the frame, the entire address period APD of one frame can be shortened.

In the sustain period SPD, sustain pulses SUSPz and SUSPy corresponding to the sustain voltage Vs are alternately supplied to the sustain electrode Z and the scan electrode Y so that the sustain discharge is maintained during the sustain period SPD. do.

In the erase period EPD subsequent to the sustain period SPD, the discharge pulse EP is supplied to the sustain electrode Z to stop the discharge.

Meanwhile, in the first subfield SF1 in the address period APD, the first scan line Y1, the second scan line Y2, the third scan line Y3, the fourth scan line Y4 and the fifth Scan pulses falling to the scan voltage (-Vye) of negative polarity (-) at the same time in the scan line (Y5), the sixth scan line (Y6), the seventh scan line (Y7), and the eighth scan line (Y8). scan is supplied, and data pulses synchronized with the scan pulse are supplied to the address electrodes X. The second subfield SF2 has the first scan line Y1, the second scan line Y2, the third scan line Y3, and the fourth scan line Y4 so as to cross the first subfield SF1. ), The fifth scan line (Y5), the sixth scan line (Y6), and the seventh scan line (Y7) are simultaneously supplied with a scan pulse that drops to the negative scan voltage (-Vye). do. From the subsequent subfields, scan pulses are sequentially supplied to the scan line (Y). In other words, during the address period APD of the first subfield of the frame, a scan pulse is simultaneously supplied to the nth (n is a multiple of 3 including 0) and the n + 1th scan electrodes Y, The scan pulse is supplied to the n + 2th scan electrode Y. The nth + 1th (n is a multiple of 3 including 0) th and nth + 2nd scan electrodes during the address period APD of the second subfield SF2 so as to cross the first subfield SF1. The scan pulse scan is simultaneously supplied to Y) and the scan pulse scan is supplied to the n + 3 th scan electrode Y. Therefore, not only the overall address period APD of one frame can be shortened, but also the scan pulses are alternately supplied to the scan electrodes Y for each frame, thereby reducing image quality deterioration due to data sharing.

On the other hand, the present invention can not only share the scan line (Y) for each subfield, but also share the scan line (Y) for each frame alternately as in the third embodiment.

As described above, the driving method of the PDP according to the present invention can reduce the address period by addressing two scan lines at the same time by sharing two data lines, and alternately alternate the scan lines for each subfield and frame. It can reduce the resolution and image quality deterioration caused by sharing.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

1 is a perspective view showing a discharge cell structure of a conventional three-electrode AC surface discharge type plasma display panel.

FIG. 2 is a layout view of electrodes of the plasma display panel shown in FIG. 1. FIG.

3 is a diagram showing a frame structure of an 8-bit default code for implementing 256 gray scales.

4 is a waveform diagram showing a driving waveform of a subfield shown in FIG. 3;

5 is a waveform diagram illustrating driving waveforms of a plasma display panel according to a first exemplary embodiment of the present invention.

FIG. 6 is a waveform diagram illustrating two subfields of the driving waveform shown in FIG. 5; FIG.

FIG. 7 is a diagram illustrating that data is shared by being alternately addressed for each subfield according to the driving waveform of FIG. 6; FIG.

8A and 8B are waveform diagrams illustrating driving waveforms of a plasma display panel according to a second exemplary embodiment of the present invention.

Fig. 9 is a waveform diagram showing driving waveforms of the plasma display panel according to the third embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

10: upper substrate 18: lower substrate

Y: scan electrode Z: sustain electrode

X: address electrode 12Y, 12Z: transparent electrode

13Y, 13Z: metal bus electrode 14: upper dielectric layer

16: protective film 22: lower dielectric layer

24: partition 26: phosphor layer

32: scan driver 34: sustain driver

36: address driver

Claims (13)

In one frame driven by dividing into multiple subfields, Supplying a first driving waveform to scan electrodes during a first address period of at least one subfield positioned at the beginning of the frame; Supplying a second driving waveform different from the first driving waveform to scan electrodes during a second address period of the remaining subfields other than the at least one subfield; And the first driving waveform includes scan pulses simultaneously supplied to at least two scan electrodes during the first address period and alternately supplied in subfields positioned at the beginning. The method of claim 1, The first driving waveform is, Supplied during the first address period of the first to third subfields; And scan pulses sequentially supplied to scan electrodes during the second address period. The method of claim 1, And the first driving waveform is supplied during the first address period of the first and second subfields. delete The method of claim 1, And a scan pulse is simultaneously supplied to the nth (n is odd) and n + 1th scan electrodes during the first address period of the first subfield. The method of claim 5, And a scan pulse is supplied simultaneously to the n + 1 (n is odd) and n + 2 th scan electrodes during the first address period of the second subfield. The method of claim 1, The n + 3 th scan electrode after a scan pulse is simultaneously supplied to the n + 1 (n is a multiple of 3 including 0) th and n + 2 th scan electrodes during the first address period of the first subfield. And a scan pulse is supplied to the plasma display panel. The method of claim 7, wherein The n + 4th scan electrode after a scan pulse is simultaneously supplied to the n + 2 (n is a multiple of 3 including 0) th and n + 3 th scan electrodes during the first address period of the second subfield. And a scan pulse is supplied to the plasma display panel. delete The method of claim 1, Wherein the scan pulse is simultaneously supplied to the nth (n is odd) and n + 1th scan electrodes during the first address period of the first subfield of the j (j is a natural number) frame How to drive the display panel. The method of claim 10, And a scan pulse is simultaneously supplied to the n + 1 (n is odd) and n + 2 th scan electrodes during the first address period of the second subfield. The method of claim 10, Scan pulses are simultaneously supplied to the n + 1 (n is odd) and n + 2 th scan electrodes during the first address period of the first subfield of the j + 1 (j is a natural number) frame. A method of driving a plasma display panel. The method of claim 12, And a scan pulse is simultaneously supplied to the nth (n is odd) and n + 1th scan electrodes during the first address period of the second subfield.