JP2004302480A - Method and apparatus for driving plasma display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and an apparatus for driving a plasma display for improving a drive voltage margin when the plasma display is driven. <P>SOLUTION: In the method for driving a plasma display panel, an image of one frame is constituted of n pieces of subfields and each subfield has a reset period for causing erase discharge, an address period and a sustain discharge period. First erase discharge caused by narrow-width pulse of a pulse width of ≤2 μs and second erase discharge caused by erase pulse which continuously changes the applied voltage are included in the reset period. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  In recent years, in various display devices, information to be displayed and installation conditions have been remarkably used, and a large screen and high definition have been remarkable. Therefore, display devices such as plasma display panels (PDPs), CRTs, LCDs, ELs, fluorescent display tubes, and light emitting diodes used for these devices are required to improve display quality in order to cope with these trends. ing.

  Among the above display devices, PDPs have been actively developed recently because they have excellent features such as no flicker, easy enlargement of screen, and high luminance and long life. PDPs include a two-electrode type that performs selective discharge (address discharge) and sustain discharge using two electrodes, and a three-electrode type that performs address discharge using a third electrode.

  In a color PDP for performing gradation display, a phosphor formed in a discharge cell is excited by ultraviolet rays generated by discharge. However, this phosphor is vulnerable to the impact of positively charged ions simultaneously generated by discharge. There are drawbacks. In the above-mentioned two-electrode type, since the phosphor directly hits the ions, the life of the phosphor may be shortened.

  As a color PDP that can avoid this problem, a three-electrode structure using surface discharge is generally known. Further, in this three-electrode type, the third electrode may be formed on the substrate on which the first and second electrodes for performing the sustain discharge are disposed, or may be disposed on another opposing substrate. Further, even when the above-mentioned three types of electrodes are formed on the same substrate, there is a case where the third electrode is arranged on the two electrodes for performing the sustain discharge, and a case where the third electrode is arranged thereunder. .

  Further, there are a case where visible light emitted from the phosphor is viewed through the phosphor (transmission type) and a case where reflection from the phosphor is viewed (reflection type). In addition, a cell that performs a discharge is disconnected from a neighboring cell by a barrier (also referred to as a rib or a barrier). This barrier is provided in four directions so as to surround the discharge cell and is completely sealed. In another case, the barrier is provided only in one direction and the other direction is broken by optimizing the gap (distance) between the electrodes. There is.

  The present invention relates to a method of driving the above-described various types of PDPs.

  In this specification, in a panel in which a third electrode is formed on a substrate opposite to a substrate on which sustain discharge is performed, a barrier is provided in a vertical direction (that is, orthogonal to the first electrode and the second electrode, (Parallel to the electrode), and a description will be given based on an example of a reflection type in which a part of the sustain electrode is formed of a transparent electrode.

  FIG. 1 is a schematic plan view of the above-described three-electrode / surface-discharge / AC-type PDP. FIG. 2 is a schematic sectional view of the three-electrode / surface-discharge / AC-type PDP in the vertical direction. Similarly, FIG. 3 is a schematic sectional view of the three-electrode / surface-discharge / AC-type PDP in the horizontal direction. . 2 and 3 show one discharge cell.

  A PDP is basically composed of two glass substrates. The front glass substrate 18 includes an X electrode 13 and a Y electrode 14 which are parallel sustain electrodes 19, and these electrodes are constituted by a transparent electrode 19a and a bus electrode 19b. Since the transparent electrode 19a has a role of transmitting reflected light from the phosphor 17, the transparent electrode 19a is formed of ITO (a transparent conductive film mainly containing indium oxide). The bus electrode 19b needs to be formed with low resistance in order to prevent a voltage drop due to electrode resistance, and is formed of Cr or Cu.

  Further, they are covered with a dielectric layer (glass) 20 and an MgO (magnesium oxide) film 21 is formed on the discharge surface as a protective film. On the rear glass substrate 16 facing the front glass substrate 18, the address electrodes 15 are formed so as to be orthogonal to the sustain electrodes 19. A barrier 11 is formed between the address electrodes 15, and a phosphor 17 having red, green, and blue emission characteristics is formed between the barriers 11 so as to cover the address electrode 15. Two glass substrates are assembled so that the ridge of the barrier 11 and the MgO 21 surface are in close contact with each other.

  FIG. 4 is a driving waveform diagram showing a conventional technique, and shows a method for driving the PDP shown in FIGS. Here, one subfield period in a so-called conventional “address / sustain discharge period separated type (ADS) / write address system” is shown. In this example, one subfield is divided into a reset period, an address period, and a sustain discharge period. In the reset period, for example, first, all the Y electrodes are set to the 0V level, and at the same time, the entire surface write pulse consisting of the voltage Vs + Vw (about 330 V) is applied to the X electrodes. As a result, discharge is performed in all cells of all display lines regardless of the previous display state. The address electrode potential at this time is about 100 V (Vaw).

  Next, the potentials of the X electrode and the address electrode become 0 V, and the voltage of the wall charge itself exceeds the discharge start voltage in all the cells, and discharge is started. In this discharge, since there is no potential difference between the electrodes, no wall charge is formed, and the space charge is self-neutralized to terminate the discharge. This is a so-called self-erasing discharge. By this self-erasing discharge, the state of all cells in the panel becomes a uniform state without wall charges. This reset period has the effect of setting all cells to the same state regardless of the lighting state of the previous subfield, and the next address (write) discharge can be performed stably.

  Next, in the address period, an address discharge is performed line-sequentially in order to turn on / off the cell according to the display data. First, a scan pulse of -Vy level (approximately -150 V) is applied to the Y electrode, and an address electrode of a voltage Va (approximately 50 V) is applied to a cell that causes a sustain discharge in the address electrode, that is, an address electrode corresponding to a cell to be turned on. A pulse is selectively applied.

  As a result, a discharge occurs between the address electrode and the Y electrode of the cell to be lit, and this is used as a priming (seeding) to immediately shift to a discharge between the X electrode (voltage Vx = 50 V) and the Y electrode. The former discharge is called "priming address discharge" and the latter is called "main address discharge". As a result, an amount of wall charges capable of sustaining discharge is accumulated on the MgO surface on the X and Y electrodes of the selected cell of the selected line.

  Hereinafter, the same operation is sequentially performed on other display lines, and new display data is written on all display lines.

  After that, in the sustain discharge period, a sustain pulse composed of the voltage Vs (about 180 V) is alternately applied to the Y electrode and the X electrode to perform the sustain discharge, and one sub-field image is displayed. In the “address / sustain discharge separation type / write address method”, the brightness is determined by the length of the sustain discharge period, that is, the number of sustain pulses.

  FIG. 5 is a time chart of the address / sustain discharge separation type / write address system, and shows a driving method in the case of performing 16-gradation display as an example of multi-gradation display. In this example, one frame is divided into four subfields (SF1, SF2, SF3, SF4). In these subfields SF1 to SF4, the reset period and the address period have the same length. The length of the sustain discharge period is, for example, a ratio of 1: 2: 4: 8. Therefore, by selecting the subfield to be turned on, 16-level gradation display from 0 to 15 can be performed.

  In the above-described driving method, each subfield has a reset period, and in each subfield, a full write discharge is performed by applying a full write pulse. For this reason, light emission during the reset period that does not originally contribute to video display occurs in each subfield, which is one of the causes of lowering the contrast of the displayed image.

In order to solve this problem, the present applicant has invented a new driving method that achieves high contrast by reducing the number of times of the full-area writing discharge per frame, and has already filed an application (Patent Document 1). In this method, the full-area write discharge in the reset period is performed only in some subfields, and in the other subfields, only the erase discharge is performed in the reset period. By reducing the number of times of full-area writing discharge, high-contrast driving in which light emission that does not contribute to image display is suppressed can be performed.
JP-A-5-313598

  There is an allowable range of the voltage values of various pulses for realizing the driving in which the ON cell is turned on correctly and the OFF cell is not turned on. Here, the voltage range from the minimum value to the maximum value is referred to as a driving voltage margin.

  First, a first problem regarding the drive voltage margin will be described. In narrow pulse erasing at the counter electrode of a simple matrix panel (double pole), most of the charged particles generated during the discharge remain in the discharge cell space because the externally applied voltage is stopped during discharge formation, and the panel dielectric It is attracted to the wall charges on the layer by electrostatic attraction and recombines on the wall to be erased. On the other hand, in a three-electrode panel having a surface discharge electrode, since the narrow pulse erasing operation is performed on the surface discharge electrode on the same substrate, the charged particles in the discharge cell space are affected by the potential on the counter electrode.

  FIG. 6 is a diagram 1 showing the residual wall charge, and shows the residual wall charge when the counter electrode is at Va during the neutralizing discharge of the narrow erase in the reset period. In this case, a large amount of negative-polarity charge is accumulated on the counter electrode, resulting in erasure failure.

  On the other hand, FIG. 7 is a diagram 2 showing the residual wall charge, and shows the residual wall charge when the counter electrode is at GND during the neutralization discharge of the narrow erase in the reset period. In this case, a large amount of positive charge is accumulated on the counter electrode, resulting in erasure failure.

  In these cases, it has been found that this erasing failure hinders the selective formation of wall charges in the next address period, resulting in a deterioration in the drive voltage margin.

  Next, a second problem regarding the drive voltage margin will be described. When the narrow erase discharge is performed during the reset period, if the discharge start is earlier than expected due to non-uniformity of pixels or changes in temperature conditions, not only the necessary wall charge cannot be erased, but also the wall charge before erase There is a possibility that a wall charge having an inversion polarity with respect to the state may be formed, which leads to a reduction in a drive voltage margin.

  Next, a third problem regarding the drive voltage margin will be described. FIG. 8 is a diagram showing the effect of the weak discharge, in which discharge light emission pulses (light) are shown together with A (address), X, and Y electrode pulses. When observing this discharge light emission pulse, weak light emission exists in the gap between the sustain discharge pulse and the next sustain discharge pulse. Since the weak discharge has little effect on the next sustain discharge itself, the sustain discharge can be normally repeated.

  However, it has been found that this weak discharge has a great effect on the erasing discharge (a narrow discharge is used in FIG. 8) during the reset period. Specifically, the weak discharge reduces wall charges formed by the sustain discharge, hinders normal erase discharge, and results in wall charge erasure failure. This leads to a reduction in the drive voltage margin.

  Next, a fourth problem regarding the drive voltage margin will be described. This problem is particularly problematic in the high contrast driving described above. The high-contrast drive described above performs only the erase discharge during the reset period except for some subfields. When an erasing pulse for erasing only the cell illuminated in the immediately preceding subfield is applied as the erasing discharge, the residual wall on the counter electrode (address electrode) is compared with the case where the entire-program / self-erasing pulse is used. It has been found that the charge erasing ability is weakened.

  Further, the residual wall charges on the opposite electrode, which cannot be reset, continue to accumulate every time the subfields are overlapped, so that the burden on the entire-frame write discharge of the next frame becomes very heavy. For this reason, the potential distribution of each cell does not become uniform even after the entire write discharge, or the subsequent address discharge is adversely affected. As a result, the drive voltage margin is reduced.

  Next, a fifth problem regarding the drive voltage margin will be described. FIG. 5 is a time chart of the address / sustain discharge separation type / write address system, showing a reset period, an address period, a sustain discharge period, and a pause period. The rest period fluctuates due to the fluctuation of the total time of the driving period due to the fluctuation of the number of times of the discharge sustaining voltage pulse, and the discharge state fluctuates due to the voltage pulse applied after the pause period due to the fluctuation, and as a result, the reset must be performed. The wall charge amount fluctuated, resulting in a reduction in the drive voltage margin.

  Next, a sixth problem regarding the drive voltage margin will be described. This problem is particularly problematic in high contrast driving. The high-contrast drive performs only the erase discharge during the reset period except for some subfields. In this high-contrast drive, the probability of resetting the charge is small if only one voltage pulse is used to perform the erase discharge. Since it is low, erasure failure occurs. This has led to a reduction in drive voltage margin.

  Further, in the wall charge erasing by the erasing pulse for continuously changing the voltage value, a non-linear waveform determined by the resistor and the panel capacitance is used for simplicity of the circuit. In the case of such a non-linear waveform, there is a problem that an erasing failure occurs when discharging is performed at a place where the erase waveform has a steep slope.

  The present invention has been made in view of the above points, and has as its object to provide a driving method and a driving apparatus of a plasma display capable of improving a driving voltage margin when driving the plasma display.

  Therefore, in order to solve the above-mentioned problem, the invention according to claim 1 forms a video of one frame by n subfields, and each of the subfields includes a reset period for performing an erase discharge, an address period, and And a sustain discharge period, wherein during the reset period, a first erase discharge by a narrow pulse having a pulse width of 2 μs or less and an erase pulse for continuously changing an applied voltage value are provided. And a second erasing discharge according to

  As described above, by performing the erasing discharge a plurality of times during the reset period, the wall charges having the inverted polarity can be erased.

  The invention according to claim 2 is characterized in that an interval between the narrow pulse and the erase pulse is set to 10 μs or more.

  As described above, by setting the interval between the first erasing discharge by the narrow pulse and the second erasing discharge by the erasing pulse to be 10 μs or more, the fluctuation of the wall charge amount can be reduced. Accordingly, the probability of resetting increases, the unstable wall charges generated by the first erasing discharge by the narrow pulse become stable, and the erasing can be reliably performed by the second erasing discharge.

  In addition, as the second erase discharge, the wall charge erase amount is smaller than the narrow erase and is not sufficient. However, since there is no possibility of charge inversion unlike the erase discharge by the narrow pulse, the applied voltage value is continuously changed. It is suitable to use changing SEP (Slope Erase Pulse) erasure.

  In the invention according to claim 3, the first and second electrodes are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. 3. The plasma display panel according to claim 1, wherein the third electrode is arranged so as to intersect the first and second electrodes, wherein the erasing pulse for continuously changing an applied voltage value is applied to the second electrode. In this case, a voltage pulse is also applied to the third electrode.

  As described above, when the erase pulse is applied to the second electrode, the voltage pulse is also applied to the third electrode, so that the residual charge can be erased more completely.

  According to a fourth aspect of the present invention, an image of one frame is composed of n subfields, and each of the subfields is maintained by repeatedly applying a reset period, an address period, and a sustain discharge pulse. In the method for driving a plasma display panel having a sustain discharge period for performing a discharge, in the reset period, a subfield A in which both a full write discharge and an erase discharge are performed, and in the reset period, without performing a full write discharge A sub-field B for performing an erasing discharge, and in a sub-field arranged immediately before the sub-field B, a pulse width of the last sustain discharge pulse in the last sustain discharge period is increased. And

  As described above, since the pulse width of the last sustain discharge pulse is sufficiently wide, most of the charged particles generated by the sustain discharge pulse become wall charges, and the priming effect due to space charges is reduced. Thus, it is possible to prevent a weak discharge from occurring after the application of the last sustain discharge pulse.

  According to a fifth aspect of the present invention, the first and second electrodes are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. 3. The plasma display panel, wherein the third electrode is disposed so as to intersect the first and second electrodes, wherein the sustain discharge pulse is applied to the first and second electrodes during the sustain discharge period. When the voltage is repeatedly applied, the potential of the third electrode is equal to the potential applied to the third electrode during the address period.

  As described above, when the sustain discharge pulse is repeatedly applied to the first and second electrodes during the sustain discharge period, the potential of the third electrode may be equal to the potential during the address period.

  In the invention according to claim 6, one frame image is composed of n subfields, and each of the subfields has a reset period for performing erase discharge, an address period, and a sustain discharge period. In the method for driving a plasma display panel, a pulse for performing an erasing discharge in the reset period is changed from a last sustain discharge pulse in the sustain discharge period of a subfield arranged immediately before the sustain discharge pulse in the sustain discharge period. It is characterized by including at least a subfield applied at an interval substantially equal to the interval between the sustain discharge pulses.

  In this way, a weak discharge is temporarily generated by applying a pulse for performing the reset discharge at an interval substantially equal to the interval of the sustain discharge pulse from the last sustain discharge pulse in the sustain discharge period of the immediately preceding subfield. Even in this case, the erasing discharge can be prevented from being affected.

  The invention according to claim 7 is characterized in that, in the reset period, a subfield A in which both a full write discharge and an erase discharge are performed, and a subfield in which an erase discharge is performed without performing a full write discharge in the reset period. B, and an erasing pulse applied for performing the erasing discharge in the reset period of the subfield B, and the last of the last subfield in the sustain discharge period of the subfield arranged immediately before the erasing pulse. The interval between the sustain discharge pulse and the sustain discharge pulse is substantially equal to the interval between the sustain discharge pulses during the sustain discharge period.

  As described above, from the last sustain discharge pulse in the sustain discharge period of the immediately preceding subfield, a pulse for performing a reset discharge at an interval substantially equal to the interval of the sustain discharge pulse is applied to the subfield B. Even if a weak discharge occurs in the field B, the erasing discharge can be prevented from being affected by the weak discharge.

  The invention according to claim 8 is characterized in that the interval between the erase pulse in the subfield B and the sustain discharge pulse at the end of the immediately preceding subfield is set to 2 μs or less.

  By setting the interval between the erase pulse in subfield B and the last sustain discharge pulse in the immediately preceding subfield to be 2 μs or less, immediately after the last sustain discharge pulse is applied, At the same interval as the interval between the pulses, the erasing discharge of the next subfield B is performed, and a particularly remarkable effect can be obtained.

  According to a ninth aspect of the present invention, the first and second electrodes are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. 3. The plasma display panel, wherein the third electrode is disposed so as to intersect the first and second electrodes, wherein the sustain discharge pulse is applied to the first and second electrodes during the sustain discharge period. When the voltage is repeatedly applied, the potential of the third electrode is equal to the potential applied to the third electrode during the address period.

  As described above, when the sustain discharge pulse is repeatedly applied to the first and second electrodes during the sustain discharge period, the potential of the third electrode may be equal to the potential during the address period.

  Further, according to a tenth aspect of the present invention, the first substrate and the second electrode are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. 3 electrodes are arranged so as to intersect the first and second electrodes, and one frame image is formed by a reset period, an address period, and a sustain discharge pulse with respect to the first and second electrodes. And a sustain discharge period in which a sustain discharge is performed by repeatedly applying a voltage during the sustain discharge period, while maintaining the potential of the third electrode during the sustain discharge period and at the end of the sustain discharge period. The voltage pulse applied to the third electrode falls simultaneously with the fall of the sustain discharge pulse.

  As described above, by dropping the voltage pulse applied to the third electrode at the same time as the trailing edge of the last sustain discharge pulse in the sustain discharge period, the wall charges on the third electrode in the sustain discharge period are reduced. The reset operation is made uniform and reliable.

  The invention according to claim 11 is characterized in that an interval between the sustain discharge pulses in the sustain discharge period is set to 1 μs or less.

  By setting the interval of the sustain discharge pulse in the sustain discharge period to 1 μs or less, the next sustain discharge can be performed before the space charge due to the weak discharge converges as the wall charge. , The wall charges on the electrodes are reduced, and the load of the erase discharge during the reset period can be reduced.

  According to a twelfth aspect of the present invention, the first electrode and the second electrode are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. 3 electrodes are arranged so as to intersect the first and second electrodes. One frame of video is composed of n subfields, and each of the subfields comprises a reset period and an address period. And a driving method for a plasma display panel having a sustain discharge period, wherein in the reset period, a subfield A in which both a full write discharge and an erase discharge are performed, and in the reset period, erasure is performed without performing a full write discharge. And a sub-field B for performing a discharge. During the reset period in the sub-field A, an erasing discharge is further performed before the entire-area writing discharge is performed. Characterized in that it.

  As described above, during the reset period of the subfield A, the state of the residual wall charges before the full-area write discharge can be made substantially the same by performing the erase discharge before performing the full-area write discharge. Discharge load can be reduced. Therefore, the charge accumulated on the counter electrode can be more completely erased.

  According to a thirteenth aspect of the present invention, in the erasing discharge performed before the entire writing discharge, any one of a narrow pulse having a pulse width of 2 μs or less and an erasing pulse for continuously changing an applied voltage value is applied. The erase discharge is performed a plurality of times by applying the erase discharge or both.

  As described above, the erasing discharge to be performed before the entire-area writing discharge is performed by performing the erasing discharge by applying any one of the narrow pulse and the erasing pulse, or by performing the erasing discharge a plurality of times by applying both of them. In addition, the state of the residual wall charges before the full-area write discharge can be made substantially the same, and the burden of the full-area write discharge can be reduced. Therefore, the charge accumulated on the counter electrode can be more completely erased.

  The invention according to claim 14 is characterized in that the erase pulse for continuously changing an applied voltage value is applied to the second electrode, and at that time, a voltage pulse is also applied to the third electrode. And

  As described above, when the erase pulse is applied to the second electrode, a voltage pulse may be applied to the third electrode.

  According to a fifteenth aspect of the present invention, in the reset period, before performing the full-area write discharge, when performing an erase discharge further, the voltage applied to the third electrode at that time is set to 0V. It is characterized by.

  As described above, by further performing the erase discharge before performing the full-area write discharge and setting the voltage applied to the third electrode to 0 V at that time, the load of the full-area write discharge can be reduced. Therefore, the charge accumulated on the counter electrode can be more completely erased.

  According to a sixteenth aspect of the present invention, the first and second electrodes are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. The three electrodes are arranged so as to intersect the first and second electrodes, and one frame of video has a reset period for performing full-area write discharge and erase discharge, an address period, and a sustain discharge period. In the method for driving a plasma display panel, a narrow pulse having a pulse width of 2 μs or less is applied to the third electrode after a fall of a full write pulse for performing the full write discharge during the reset period. And

  As described above, in the reset period, after the fall of the entire write pulse, the narrow pulse having a pulse width of 2 μs or less is applied to the third electrode, thereby completely erasing the charge accumulated on the counter electrode. To make the wall charges uniform.

  The invention according to claim 17 is characterized in that, during the reset period, a narrow pulse having a pulse width of 2 μs or less is applied to the third electrode within 10 μs after the fall of the entire write pulse. I do.

  As described above, in the reset period, by applying the narrow pulse to the third electrode within 10 μs after the fall of the entire write pulse, the charge accumulated on the counter electrode is more completely erased, Particularly remarkable effects can be obtained.

  The invention according to claim 18 is characterized in that, in the reset period, an erase pulse for continuously changing an applied voltage value is applied to the second electrode after the fall of the entire write pulse.

  As described above, in the reset period, after the fall of the entire write pulse, by applying the erase pulse for continuously changing the applied voltage value to the third electrode, the charge accumulated on the counter electrode can be erased more. Completely, it is possible to make the wall charge uniform.

  According to a nineteenth aspect of the present invention, one frame of video is composed of n subfields each having a predetermined weight and a pause period during which no drive waveform is output, and each of the subfields is a reset period. And a driving method of a plasma display panel having an address period and a sustain discharge period, wherein a sub-field A in which both a full write discharge and an erase discharge are performed in the reset period, and a full write discharge is realized in the reset period And a sub-field B for performing an erasing discharge without performing the erasing discharge, and the pause period is a self-erasing period after application of an entire writing pulse for performing a full writing discharge.

  As described above, by making the idle period a self-erasing period after application of the entire write pulse, it is possible to reduce fluctuations in the drive voltage margin due to the length of the idle period.

  According to a twentieth aspect of the present invention, the first electrode and the second electrode are arranged in parallel on the first substrate, and the first substrate or the second substrate opposed to the first substrate is provided with a second electrode. 3 electrodes are arranged so as to intersect the first and second electrodes. One frame of video is composed of n subfields, and each of the subfields comprises a reset period and an address period. And a sustaining discharge period, a first step of applying a narrow pulse having a pulse width of 2 μs or less during the reset period, and continuously applying a voltage value in the positive direction. A second step of applying an erase pulse to be changed, and a third step of applying an erase pulse for continuously changing an applied voltage value in a negative direction or an erase pulse in a negative direction. .

  Thus, during the reset period, a first narrow pulse is applied to the first electrode, and a second erase pulse that continuously changes the applied voltage value in the positive direction is applied to the second electrode. Third, an address selection discharge is performed by applying an erasing pulse for continuously changing the applied voltage value in the negative direction or an erasing pulse in the negative direction to the second electrode and combining a plurality of erasing pulses. The probability of resetting the previous residual wall charge can be increased, and the drive voltage margin can be increased.

  The invention according to claim 21 further includes a fourth step of applying an erase pulse for continuously changing the applied voltage value in the positive direction during the reset period.

  As described above, when a plurality of erasing pulses are applied during the reset period, a fourth erasing pulse that continuously changes the applied voltage value in the positive direction is applied to the second electrode, so that the address selection discharge is performed. , The probability of resetting the residual wall charge is increased, and a particularly remarkable effect can be obtained.

  The invention according to claim 22 is characterized in that the (n + 1) th positive erase pulse is made longer than the nth positive erase pulse.

  As described above, when a plurality of erase pulses for continuously changing the applied voltage value are applied during the reset period, the address selective discharge is performed by making the (n + 1) th positive erase pulse longer than the nth positive erase pulse. , The probability of resetting the residual wall charge before performing is increased, and a particularly remarkable effect can be obtained.

  According to a twenty-third aspect of the present invention, the first and second electrodes are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. 3 electrodes are arranged so as to intersect the first and second electrodes. One frame of video is composed of n subfields, and each of the subfields comprises a reset period and an address period. And a sustaining discharge period, a first step of applying a narrow pulse having a pulse width of 2 μs or less during the reset period, and continuously applying a voltage value in the positive direction. The method includes a second step of applying a first erase pulse to be changed, and a third step of applying a second erase pulse to continuously change an applied voltage value in a positive direction.

  As described above, when a plurality of erase pulses for continuously changing the applied voltage value are applied during the reset period, the narrow pulse is applied first to the first electrode, and the applied voltage value is applied second in the positive direction. Is applied to the second electrode, and thirdly, an erase pulse for continuously changing the applied voltage value in the positive direction is applied to the first electrode, thereby performing the address selection discharge. The probability of resetting the previous residual wall charge can be increased, and the drive voltage margin can be increased.

  According to a twenty-fourth aspect of the present invention, the first electrode and the second electrode are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. In a method for driving a plasma display panel in which three electrodes are arranged so as to intersect with the first and second electrodes, an image of one frame is composed of n subfields, and each of the subfields is , A reset period, an address period, and a sustain discharge period. In the reset period, the voltage applied to the electrode is continuously changed, and discharge is performed at a potential close to the discharge start voltage. A plurality of reset pulses for erasing wall charges are applied.

  As described above, by continuously applying a plurality of reset pulses to any one of the electrodes, the wall charges of each cell having a different discharge start voltage are stably and reliably erased at a voltage close to the discharge start voltage (reset). )can do.

  The invention according to claim 25 is characterized in that the plurality of reset pulses are applied to a second electrode, and the potential of the first electrode is set to a different value for each reset pulse.

  As described above, since the maximum potential difference between the first and second electrodes is set to be different, the wall charge of each cell having a different firing voltage is more stably and reliably erased at a voltage close to the firing voltage ( Reset).

  The invention according to claim 26 is characterized in that the plurality of reset pulses are applied to a second electrode, and the potential of the third electrode has a different value for each reset pulse.

  As described above, since the maximum potential difference between the first and third electrodes is set to be different, the wall charge of each cell having a different firing voltage is more stably and reliably erased at a voltage close to the firing voltage ( Reset).

  The invention according to claim 27 is characterized in that the plurality of reset pulses have the same voltage gradient.

  Thus, a circuit for generating a reset pulse can be easily configured.

  Also, in the invention according to claim 28, for the plurality of reset pulses, the maximum potential difference between the first electrode and the second electrode of the (n + 1) th reset pulse is larger than the maximum potential difference in the nth reset pulse. It is characterized by being large.

  In this way, cells having a relatively low firing voltage can be reset first, and then cells having a relatively high firing voltage can be reset.

  Also, in the invention according to claim 29, for the plurality of reset pulses, the maximum potential difference between the second electrode and the third electrode of the (n + 1) th reset pulse is larger than the maximum potential difference in the nth reset pulse. It is characterized by being large.

  In this way, cells having a relatively low firing voltage can be reset first, and then cells having a relatively high firing voltage can be reset.

  According to a thirtieth aspect of the present invention, at least one of the potentials of the first electrode which is set to a different value for each reset pulse is equal to the potential applied to the first electrode during the address period. Features.

  Thus, a circuit for controlling the first electrode potential can be easily configured.

  The invention according to claim 31 is that at least one of the potentials of the third electrode, which is set to a different value for each reset pulse, is equal to the potential applied to the third electrode during the address period. Features.

  Thus, a circuit for controlling the third electrode potential can be easily configured.

  In the invention according to claim 32, the first and second electrodes are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. A plasma display panel in which three electrodes are arranged so as to intersect with the first and second electrodes, and one frame of video is composed of n subfields, each of which has a reset period; A first control unit for driving the plasma display panel including an address period and a sustain discharge period; and a voltage applied to the electrodes is continuously changed during the reset period to discharge at a potential close to a discharge start voltage. And a second control unit for applying a plurality of reset pulses for erasing wall charges by performing the above operation.

  As described above, by continuously applying a plurality of reset pulses to any one of the electrodes, the wall charges of each cell having a different discharge start voltage are stably and reliably erased at a voltage close to the discharge start voltage (reset). )can do.

  In the invention according to claim 33, the first electrode and the second electrode are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. 3 electrodes are arranged so as to intersect the first and second electrodes. One frame of video is composed of n subfields, and each of the subfields comprises a reset period and an address period. And a sustain discharge period in which a sustain discharge is performed by repeatedly applying a sustain discharge pulse to the first and second electrodes. The subfield has both a subfield A for performing a discharge together and a subfield B for performing an erase discharge without performing a full write discharge in the reset period. In the sub-field positioned immediately before the de B, and characterized in that a longer pulse width of the last of the sustain discharge pulse to the second electrode in the sustain discharge period.

  As described above, since the pulse width of the last sustain discharge pulse is sufficiently wide, most of the charged particles generated by the sustain discharge pulse become wall charges, and the priming effect due to space charges is reduced. Thus, it is possible to prevent a weak discharge from occurring after the application of the last sustain discharge pulse.

  The invention according to claim 34 is characterized in that during the sustain discharge period, the potential of the third electrode is equal to the potential applied to the third electrode during the address period.

  Thus, during the sustain discharge period, the potential of the third electrode may be equal to the potential during the address period.

  According to a thirty-fifth aspect of the present invention, an image of one frame is composed of n subfields, and each of the subfields is maintained by repeatedly applying a reset period, an address period, and a sustain discharge pulse. A sustain discharge period for performing a discharge, wherein the pulse width of the last sustain discharge pulse at the end of the sustain discharge period of the predetermined sub-field is increased, and In the reset period of the subfield, an erase discharge is performed by a narrow pulse having a pulse width of 2 μs or less.

  As described above, since the last sustain pulse has a sufficiently wide pulse width, most of the charged particles generated by the sustain discharge pulse become wall charges, the priming effect due to space charges is reduced, and a large amount of residual charges is generated.安定 安定 安定 を な く 安定 な く.

  According to a thirty-sixth aspect of the present invention, there is provided a method for driving a plasma display panel, wherein one frame of video has a reset period, an address period and a sustain discharge period in which a sustain discharge is performed by repeatedly applying a sustain discharge pulse. The pulse widths of the first and last sustain discharge pulses in the sustain discharge period are increased.

  As described above, since the pulse widths of the first and last sustain discharge pulses are sufficiently wide, most of the charged particles generated by the sustain discharge pulse become wall charges, and the priming effect due to space charges is reduced. Thus, it is possible to prevent a weak discharge from occurring after the application of the last sustain discharge pulse.

  In the invention according to claim 37, the first and second electrodes are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. 3 electrodes are arranged so as to intersect the first and second electrodes, and one frame image is formed by a reset period, an address period, and a sustain discharge pulse with respect to the first and second electrodes. And a sustain discharge period in which a sustain discharge is performed by repeatedly applying a voltage, while maintaining the potential of the third electrode during the sustain discharge period, and maintaining the potential of the second electrode during the sustain discharge period. The voltage pulse applied to the third electrode falls simultaneously with the fall of the last sustain discharge pulse to the third electrode.

  As described above, by dropping the voltage pulse applied to the third electrode at the same time as the trailing edge of the last sustain discharge pulse in the sustain discharge period, the wall charges on the third electrode in the sustain discharge period are reduced. The reset operation is made uniform and reliable.

  In the invention according to claim 38, the first and second electrodes are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. 3 electrodes are arranged so as to intersect the first and second electrodes, and one frame of the image is composed of a reset period in which both full write discharge and erase discharge are performed, an address period, and a sustain discharge period. In the method for driving a plasma display panel having the above, a narrow pulse having a pulse width of 2 μs or less is applied to the first electrode during the reset period before performing the full-area write discharge, and the applied voltage value is continuously set. By applying an erasing pulse to the second electrode, the erasing discharge is further performed.

  As described above, by performing the erasing discharge a plurality of times during the reset period, the wall charges having the inverted polarity can be erased.

  The invention according to claim 39 is characterized in that, when the erase pulse for continuously changing the applied voltage value is applied to the second electrode, a voltage pulse is also applied to the third electrode. I do.

  As described above, when the erase pulse is applied to the second electrode, the voltage pulse is also applied to the third electrode, so that the residual charge can be erased more completely.

  Further, in the invention according to claim 40, in the reset period, before performing the full-area write discharge, when performing an erase discharge further, the voltage applied to the third electrode at that time is set to 0V. It is characterized by.

  As described above, by further performing the erase discharge before performing the full-area write discharge and setting the voltage applied to the third electrode to 0 V at that time, the load of the full-area write discharge can be reduced. Therefore, the charge accumulated on the counter electrode can be more completely erased.

  Also, in the invention according to claim 41, an image of one frame is composed of n subfields, and each of the subfields has a reset period, an address period, and a sustain discharge period. In the driving method, the reset period includes both a subfield A for performing both a full-area write discharge and an erase discharge, and a subfield B for performing an erasure discharge without performing a full-area write discharge during the reset period. A first step of applying an erase pulse for continuously changing the applied voltage value in the positive direction during the reset period of the subfield B, and an erase pulse for continuously changing the applied voltage value in the negative direction, or A second step of applying an erase pulse in a negative direction, and a third step of applying an erase pulse for continuously changing an applied voltage value in a positive direction. Characterized in that it comprises a step.

  Thus, during the reset period, a first narrow pulse is applied to the first electrode, and a second erase pulse that continuously changes the applied voltage value in the positive direction is applied to the second electrode. Third, an address selection discharge is performed by applying an erasing pulse for continuously changing the applied voltage value in the negative direction or an erasing pulse in the negative direction to the second electrode and combining a plurality of erasing pulses. The probability of resetting the previous residual wall charge can be increased, and the drive voltage margin can be increased.

  Also, in the invention according to claim 42, a video of one frame is composed of n subfields, and each of the subfields has a reset period, an address period, and a sustain discharge period. In the driving method, during the reset period, a first erase discharge by a narrow pulse having a pulse width of 2 μs or less and a second erase discharge by a rising of an erase pulse for continuously changing a voltage value applied in a positive direction. And a third erasing discharge caused by a falling edge of an erasing pulse that continuously changes the applied voltage value in the negative direction.

  As described above, when a plurality of erase pulses for continuously changing the applied voltage value are applied during the reset period, the narrow pulse is applied first to the first electrode, and the applied voltage value is applied second in the positive direction. Is applied to the second electrode, and thirdly, an erase pulse for continuously changing the applied voltage value in the positive direction is applied to the first electrode, thereby performing the address selection discharge. The probability of resetting the previous residual wall charge can be increased, and the drive voltage margin can be increased.

  Further, according to the invention of claim 43, an image of one frame is composed of n subfields, and each of the subfields has a reset period, an address period, and a sustain discharge period. In the driving method, the reset period includes both a subfield A for performing both a full-area write discharge and an erase discharge, and a subfield B for performing an erasure discharge without performing a full-area write discharge during the reset period. In the reset period of the subfield B, a reset pulse for continuously changing the voltage applied to the electrode is applied.

  As described above, by continuously applying a plurality of reset pulses to any one of the electrodes, the wall charges of each cell having a different discharge start voltage are stably and reliably erased at a voltage close to the discharge start voltage (reset). )can do.

  Further, in the invention according to claim 44, the first and second electrodes are arranged in parallel on the first substrate, and the first substrate or the second substrate facing the first substrate is provided with a second electrode. 3. The plasma display panel, wherein the third electrode is arranged to intersect the first and second electrodes, wherein the reset pulse for continuously changing an applied voltage value is applied to the second electrode. In this case, a voltage pulse is also applied to the third electrode.

  As described above, when the erase pulse is applied to the second electrode, the voltage pulse is also applied to the third electrode, so that the residual charge can be erased more completely.

  Also, in the invention according to claim 45, an image of one frame is composed of n subfields, and each of the subfields has a reset period, an address period, and a sustain discharge period. In the driving method, the reset period includes both a subfield A for performing both a full-area write discharge and an erase discharge, and a subfield B for performing an erasure discharge without performing a full-area write discharge during the reset period. In the reset period of the subfield B, a plurality of reset pulses for continuously changing the voltage applied to the electrodes are applied.

  As described above, by continuously applying a plurality of reset pulses to any one of the electrodes, the wall charges of each cell having a different discharge start voltage are stably and reliably erased at a voltage close to the discharge start voltage (reset). )can do.

  As described above, according to the present invention, in high contrast driving in which only an erasing discharge is performed during a reset period except for some subfields, erasing is performed by erasing only cells lit in the immediately preceding subfield due to erasing discharge. Even when a narrow pulse is applied as a pulse, a wide drive voltage margin can be obtained.

  More specifically, accumulation of a large amount of negative (or positive) polarity charge due to the influence of the counter electrode potential is avoided, and more complete erasing becomes possible.

  Alternatively, in the erasing operation in the reset period, almost complete erasing operation can be realized without causing erasing failure.

  Alternatively, it is possible to prevent the erasing operation failure during the reset period due to the weak discharge after the trailing edge of the last sustain discharge pulse.

  Alternatively, even if a weak discharge occurs after the trailing edge of the last sustain discharge pulse, the subsequent narrow discharge can be performed normally.

  Alternatively, it is possible to more completely erase the charge on the counter electrode by the entire surface writing / self-erasing pulse during the reset period.

  Alternatively, the effect of the residual wall charge accumulated on the counter electrode during the sustain discharge period can be minimized, and the next erasing operation can be performed more completely.

  Further, by continuously applying a plurality of reset pulses to any one of the electrodes, wall charges of each cell having a different discharge start voltage are stably and reliably erased (reset) at a voltage close to the discharge start voltage. be able to.

  Alternatively, since the maximum potential difference between the first and second or third electrodes is set to be different, wall charges of each cell having a different firing voltage are more stably and reliably erased at a voltage close to the firing voltage. (Reset).

  Alternatively, a circuit for generating a reset pulse can be simply configured.

  Alternatively, cells having a relatively low firing voltage can be reset first, and then cells having a relatively high firing voltage can be reset.

  Alternatively, a circuit for controlling the second or third electrode potential can be simply configured.

  Next, the best mode for carrying out the present invention will be described based on the following embodiments with reference to the drawings.

  9 and 10 are driving waveform diagrams showing the first and second embodiments, respectively, in which the present embodiment is applied to the high contrast driving method. That is, in the subfield SFn + 1, the entire-area write discharge is not performed, and the wall charge is erased by applying an erase pulse composed of a narrow pulse (for example, a pulse width of 2 μs or less) to the X electrode. The narrow pulse terminates the application of the pulse voltage immediately after the discharge is formed. Most of the charged particles generated at the time of the discharge remain in the discharge cell space and are statically charged by the wall charges on the panel dielectric layer. It is adsorbed by the electro-gravitational force and recombined on the wall to be erased. This is common to the following embodiments.

  It is known that the panel operates stably by setting the counter electrode potential during the sustain discharge period of a three-electrode structure panel to an intermediate value of the potential difference between the sustain discharge electrodes. Therefore, during the sustain discharge period, the counter electrode is maintained at the positive potential. The same applies to an erasing discharge by a narrow pulse (for example, a pulse width of 2 μs or less).

  For this reason, in the present embodiment, the potential of the counter electrode when the wall charges are formed by performing the erase discharge by applying the narrow pulse is set to the potential difference Va between the sustain discharge electrodes. Then, the falling of the counter electrode potential Va is made coincident with the rising of the narrow pulse, and the potential at the time of neutralization discharge generated by the falling of the narrow pulse is set to GND, whereby the narrow erase discharge is performed. The influence of the potential of the common electrode at the time is avoided.

  The second embodiment shown in FIG. 10 is a modification of the first embodiment shown in FIG. The waveforms themselves applied to the X and Y electrodes are different from those of the first embodiment shown in FIG. 9, but the potential difference between the X and Y electrodes is the same as that of the first embodiment shown in FIG. It can be said that the driving is substantially the same.

  According to the above-described first and second embodiments, more complete erasing can be performed by avoiding accumulation of a large amount of negative (or plus) polarity charge due to the influence of the counter electrode potential, and the driving voltage margin is improved.

  In the present embodiment, the description is made based on the high contrast driving method. However, the principle of the present embodiment is not necessarily limited to the high contrast driving method. For example, in a case where the entire-area writing / narrow erasing discharge is performed during the reset period of all subfields, the same effect as that of the present embodiment can be expected. Conversely, it is also effective in a case where a narrow erase discharge is performed without performing a full-area write discharge during the reset period of all subfields.

  FIG. 11 is a driving waveform diagram showing the third embodiment, and shows high contrast driving. The cell that has undergone the final sustain discharge in the n-th subfield SFn stores a positive charge on the X electrode and a negative charge on the Y electrode. FIG. 3 conceptually shows an approximate wall charge amount on the X and Y electrodes. In SFn + 1 as the next subfield, the entire-area write discharge is not performed, and the wall charge is erased by applying a narrow pulse as the first erase pulse to the X electrode.

  At this time, if the start of discharge is earlier than expected due to non-uniformity of pixels or changes in temperature conditions, wall charges having polarities opposite to the wall charges before erasing are accumulated in both X and Y. . In the example shown in the figure, although the number is smaller than before the application of the erasing pulse, wall charges are accumulated on the X and Y electrodes, resulting in an erasing failure state.

  However, in the present embodiment, the state of the erasure failure is made closer to the state of complete erasure by the second erase pulse SEP (Slope Erase Pulse) arranged next. Note that the SEP is desirably provided at an interval of 10 μs or more from the narrow pulse which is the first erase pulse. This is because if the interval between the SEP and the narrow pulse as the first erase pulse is 10 μs or less, the erase operation is performed while the charge state is unstable.

  In the example of FIG. 11, after the erasing operation by the second erasing pulse, the wall charges remaining on the X and Y electrodes are extremely small, and such residual charges have an adverse effect on the subsequent address period. I will not give.

  As the second erasing pulse, the amount of wall charge erasure is smaller than that of the narrow width erasure, which is not sufficient. However, it is preferable to use SEP because there is no possibility of charge inversion unlike the narrow width. The SEP is a pulse that rises with a gentle slope, and discharge is performed sequentially from the cell in which the rising pulse voltage reaches the discharge voltage. Therefore, each cell substantially has an optimum voltage (a voltage substantially equal to the discharge start voltage). ) Is applied. Therefore, the charge whose polarity has been inverted does not remain in the cell.

  According to the third embodiment, in the erasing operation in the reset period, almost complete erasing operation can be realized without causing erasing failure, and the driving voltage margin is improved. It should be noted that the present embodiment is effective even in the case where the narrow erase discharge is performed without performing the full-area write discharge even in the reset periods of all the subfields. As a plurality of erasing discharges, in addition to the combination of the narrow width / SEP, for example, a combination of the narrow width / narrow width, SEP / SEP, SEP / narrow width, and the like are also possible.

  FIG. 12 is a driving waveform diagram showing the fourth embodiment, in which this embodiment is applied to a high contrast driving method. That is, in the subfield SFn + 1, the entire-area write discharge is not performed, and the wall charge is erased by applying an erase pulse composed of a narrow pulse to the X electrode. As described with reference to FIG. 8, the weak discharge occurs after the fall of each sustain pulse in the sustain discharge period, and in particular, the weak discharge generated after the fall of the last sustain discharge pulse is performed thereafter. This had an adverse effect on the erase discharge.

  However, in this embodiment, the pulse width of the last sustain discharge pulse is longer than the pulse widths of the other sustain discharge pulses. As a result, in the present embodiment, a weak discharge does not occur after the trailing edge of the last sustain discharge pulse having a longer pulse width, and the subsequent narrow discharge can be normally performed. It has been experimentally confirmed that the pulse width of the last sustain discharge pulse needs to be at least 3 μs or more in order to prevent weak discharge.

  According to the above-described fourth embodiment, it is possible to prevent the erasing operation failure in the reset period due to the weak discharge after the trailing edge of the last sustain discharge pulse, and the driving voltage margin is improved.

  In the present embodiment, the description is made based on the high contrast driving method. However, the principle of the present embodiment is not necessarily limited to the high contrast driving method. The same effect as that of the present embodiment can be expected even with a driving method in which a full write discharge is performed during the reset period of all subfields. Conversely, it is also effective in a case where a narrow erase discharge is performed without performing a full-area write discharge during the reset period of all subfields.

  FIG. 13 is a driving waveform diagram showing the fifth embodiment, in which this embodiment is applied to a high contrast driving method. That is, in the subfield SFn + 1, the entire-area write discharge is not performed, and the wall charge is erased by applying an erase pulse composed of a narrow pulse to the X electrode. In the present embodiment, the interval between the last sustain discharge pulse and the narrow pulse applied in the reset period in the subfield in which the subsequent full-field discharge is not performed is set to the sustain discharge pulse in the sustain discharge period of the same subfield. The distance between them is as narrow as the interval between them.

  As described with reference to FIG. 8, a weak discharge was generated after the trailing edge of the last sustain discharge pulse, which had an adverse effect on normal erase discharge. However, as described above, it has been found that this weak discharge has almost no effect on the continuously applied sustain pulse. It is considered that the reason that the weak discharge does not affect each sustain discharge is that the next pulse is applied immediately after the generation of the weak discharge.

  In the present embodiment, taking this point into consideration, the interval between the last sustain discharge pulse and the narrow pulse during the reset period in the subsequent subfield (without performing the full-area write discharge) is defined as the interval between the sustain discharge pulses. It was as narrow as. This interval is suitably set to 2 μs or less.

  As described above, according to the fifth embodiment, as can be seen from the light pulse in FIG. 11, although the weak discharge occurs after the trailing edge of the last sustain discharge pulse, the subsequent narrow discharge can be performed normally, and the driving voltage is reduced. Margins are improved.

  In the present embodiment, the description is made based on the high contrast driving method. However, the principle of the present embodiment is not necessarily limited to the high contrast driving method. The same effect as that of the present embodiment can be expected even with a driving method in which a full write discharge is performed during the reset period of all subfields. In this case, the interval between the last sustain discharge pulse and the entire write pulse during the reset period in the subsequent subfield is set to be as narrow as the interval between the sustain discharge pulses. Conversely, it is also effective in a case where an erasing discharge (for example, narrow-width erasing) is performed without performing a full-area writing discharge during the reset period of all subfields.

  FIG. 14 is a drive waveform diagram showing the sixth embodiment, which is a combination of the fourth and fifth embodiments. That is, in the present embodiment, the pulse width of the last sustain discharge pulse is longer than the pulse widths of the other sustain discharge pulses. Further, the interval between the last sustain discharge pulse and the narrow pulse during the reset period in the next subfield (without performing the full address discharge) is the same as the interval between the sustain discharge pulses in the sustain discharge period. It is narrow enough.

  Since the present embodiment includes the contents of the fourth embodiment, a weak discharge should not occur when the last sustain discharge pulse falls. However, this embodiment further adds the contents of the fifth embodiment so that normal narrow erasing can be realized even if a weak discharge is generated due to a variation in panel conditions or the like. Thus, in this embodiment, the erasing discharge is made more reliable.

  According to the sixth embodiment described above, it is possible to prevent the erasing operation failure during the reset period caused by the weak discharge after the trailing edge of the last sustain discharge pulse, and the drive voltage margin is improved. In addition, the present invention is not limited to the high contrast driving method shown in FIG.

  FIG. 15 is a driving waveform diagram showing the seventh embodiment. In subfield SFn + 1, a wall charge is erased by applying a full-surface writing / self-erasing pulse to the X electrode.

  In the present embodiment, the falling of the last sustain discharge pulse and the falling of the common electrode potential Va are simultaneously performed, so that the wall charges on the address electrode serving as the common electrode are made uniform. It has been confirmed that the interval of the sustain discharge pulse in the sustain discharge period is desirably 1 μs or less in order to reduce the wall charge on the third electrode due to the weak discharge.

  According to the seventh embodiment, the wall charges on the address electrode as the counter electrode can be made uniform, the erasing operation failure during the reset period can be prevented, and the drive voltage margin can be improved. In addition, the present embodiment is not limited to the driving method shown in the figure, and may be effective in, for example, a high contrast driving method.

  Next, FIGS. 16, 17, and 18 are drive waveform diagrams showing the eighth, ninth, and tenth embodiments, respectively, showing examples applied to a high contrast driving method. In these embodiments, a pulse having an erasing function, for example, a narrow pulse, an SEP, or both, is applied immediately before a subfield in which a full-area write discharge is performed. By applying the erase pulse, it is possible to reduce the load on the few whole-area writing discharges. In other words, the state of the residual wall charges before the full-field write discharge can always be kept the same regardless of the lighting state of the immediately preceding subfield, so that the residual wall charges on the counter electrode can be erased more completely. it can.

  The eighth embodiment is an example in which the erase pulse in the reset period of the sub-field SFn + 1 is set as the entire write / self-erase pulse, and a narrow pulse is arranged next to the sustain discharge period of the immediately preceding sub-field SFn.

  Further, the ninth embodiment is an example in which the erase pulse in the reset period of the subfield SFn + 1 is set as the entire write / self erase pulse, and the narrow width and SEP are arranged next to the sustain discharge period of the immediately preceding subfield SFn.

  Further, the tenth embodiment is an example in which the erase pulse in the reset period of the subfield SFn + 1 is set as the entire write / self erase pulse, and the narrow pulse and the SEP are arranged next to the sustain discharge period of the immediately preceding subfield SFn.

  With these pulses, the state of the residual wall charge before the full-area write discharge can be made substantially the same regardless of the lighting state of the immediately preceding subfield.

  According to the eighth, ninth, and tenth embodiments described above, the opposite-side charge can be more completely erased by the entire-surface write / self-erase pulse during the reset period, and the drive voltage margin is improved.

  Although the present embodiment is described based on the high contrast driving method, the principle of the present embodiment is not necessarily limited to the high contrast driving method. The same effect as that of the present embodiment can be expected even if the driving method is such that the entire surface write discharge is performed in the reset periods of all the subfields.

  FIG. 19 is a driving waveform diagram showing the eleventh embodiment, showing an example applied to a high contrast driving method. In this embodiment, before performing the entire-area writing discharge, an erasing discharge is further performed, and the voltage applied to the address electrode serving as the third electrode at that time is set to 0V. As described above, by setting the voltage applied to the address electrode at the time of the erasing discharge to 0 V, the state of the residual wall charge before the entire-area write discharge can always be made the same state. It can be done in a more complete way.

  According to the eleventh embodiment, the opposite-side charge can be erased more completely by the entire-surface write / self-erase pulse during the reset period, and the drive voltage margin is improved.

  Although the present embodiment is described based on the high contrast driving method, the principle of the present embodiment is not necessarily limited to the high contrast driving method. The same effect as that of the present embodiment can be expected even if the driving method is such that the entire surface write discharge is performed in the reset periods of all the subfields.

  FIG. 20 is a driving waveform diagram showing the twelfth embodiment, in which the present embodiment is applied to a high contrast driving method. In the present embodiment, in the reset period, before performing the full-area write discharge, an erasure discharge is further performed, and after the fall of the full-area write pulse for performing the full-area write discharge, a narrow pulse is applied to the address electrode as the third electrode. Is being applied. As a result, even if residual wall charges remain after the entire surface write discharge, the erasure of the residual wall charges on the address electrodes can be performed in a more complete manner.

  Experimentally, it is desirable that the interval between the fall of the entire write pulse for performing the entire write discharge and the rise of the narrow pulse applied to the address electrode serving as the third electrode is within 10 μs. Has been confirmed.

  According to the twelfth embodiment described above, the opposite-side charge can be erased in a more complete manner by the entire surface write / self-erasing pulse during the reset period, and the drive voltage margin is improved. In addition, the present invention is not limited to the high contrast driving method shown in FIG.

  FIG. 21 is a driving waveform diagram showing the thirteenth embodiment, and shows only a part of the reset period.

  In this embodiment, in the reset period, after the entire write pulse falls, an address narrow pulse is applied to the address electrode serving as the third electrode, and the applied voltage value is continuously changed to the second electrode. An erase pulse SEP is applied. As a result, even if the residual wall charges remain after the entire-area write discharge, the erasure of the residual wall charges on the address electrodes can be completed more completely by the combination of the address narrow pulse and the erase pulse SEP for continuously changing the applied voltage value. Can be done in the form.

  According to the thirteenth embodiment, the opposite-side charge can be more completely erased by the entire-surface write / self-erase pulse during the reset period, and the drive voltage margin is improved. In addition, the present invention is not limited to the high contrast driving method shown in FIG.

  FIG. 22 is a drive waveform arrangement diagram in the fourteenth embodiment, and shows a case where the number of all subfields is four as an example. FIG. 22A shows a case where the arrangement order of each period in one subfield is reset, address, and sustain discharge. FIG. 22B shows an arrangement order of each period in one subfield which is address, sustain discharge, and sustain discharge. FIG. 22C shows a case where the arrangement order of each period in one subfield is reset (including a full-scale write pulse), address, sustain discharge, and reset (not including a full-scale write pulse). .

  In the present embodiment, in the high-contrast driving method, a reset period for applying a full-area write / self-erase pulse is disposed after the shortest sustain discharge period or after the longest sustain discharge period.

  For example, when a reset period for applying a full-scale write / self-erase pulse is arranged after the shortest sustain discharge period, the reset period 24 of the subfield (SF) 2 in FIG. 22A and the SF1 in FIG. 22B. 22 and the reset period 27 at the end of SF1 in FIG. 22C.

  If the number of subfields for performing full-area write discharge is reduced, residual wall charges that cannot be completely reset accumulate on the counter electrode, and the burden on the few full-area write discharges increases. Also accumulate. Therefore, in order to reduce the burden on the entire-area write discharge, it is better that the sustain discharge period of the immediately preceding subfield is shorter.

  On the other hand, when the reset period for applying the full-scale write / self-erase pulse is arranged after the longest sustain discharge period, the reset period 23 of SF1 in FIG. 22A, the reset period 26 of SF4 in FIG. In FIG. 22C, they are respectively arranged in the reset period 28 at the end of SF4.

  If the number of subfields for performing full-area write discharge is reduced, residual wall charges that cannot be completely reset accumulate on the counter electrode, and the burden on the few full-area write discharges increases. Also accumulate. Therefore, in order to increase the effect of the full-area write discharge, it is better that the sustain discharge period of the subfield immediately before it is long.

  As described above, according to the fourteenth embodiment, the influence of the residual wall charges accumulated on the counter electrode during the sustain discharge period can be minimized, and the next erasing operation can be performed in a more complete manner. Is improved.

  FIG. 23 is a drive waveform diagram showing the fifteenth embodiment, in which the present embodiment is applied to a high contrast driving method. In the subfield A, as shown in the eighth embodiment of FIG. 16, a pulse having an erasing function is applied immediately before the subfield in which the entire-area write discharge is performed.

  In the present embodiment, the idle period during which no drive waveform is output is defined as the self-erasing period after application of the entire write pulse, and the idle period is provided in the subfield A in which both the entire write discharge and the erase discharge are performed. This is because by providing the idle period as described above, the amount of wall charges that must be reset is most stable, and the erasing discharge is ensured.

  As described above, according to the fifteenth embodiment, the fluctuation of the wall charge amount due to the fluctuation of the idle period can be reduced, and the driving voltage margin is improved. In addition, the present invention is not limited to the high contrast driving method shown in FIG.

  Next, FIGS. 24 and 25 are drive waveform diagrams showing the sixteenth and seventeenth embodiments, respectively, showing examples applied to a high contrast driving method. 24 and 25 illustrate a part of the reset period.

  In these embodiments, by using a combination of a plurality of erasing pulses during the reset period, the erasing of the residual wall charges can be performed with a higher probability than the erasing of the residual wall charges by one erasing discharge.

  In the embodiment of FIG. 24A, in the reset period, a narrow pulse is applied first to the first electrode, and a second erase pulse SEP for continuously changing the applied voltage value in the positive direction is applied to the second electrode. This is an example in which a negative direction SEP is applied thirdly. In the embodiment shown in FIG. 24B, in the reset period, a narrow pulse is applied first to the first electrode, and a second erase pulse SEP for continuously changing the applied voltage value in the positive direction is applied. This is an example in which an erasing pulse applied to the second electrode and applied thirdly in the negative direction is applied to the second electrode.

  The embodiment of FIG. 25A is obtained by applying the fourth erase pulse to the embodiment of FIG. 24A, and the embodiment of FIG. 4) is obtained by applying a fourth erase pulse to the embodiment shown in FIG. The fourth erase pulse is a positive-direction SEP applied to the second electrode.

  Here, a longer effect can be obtained by making the erase pulse SEP for continuously changing the applied voltage value in the second positive direction longer than that in the fourth positive direction SEP applied. Has been experimentally confirmed. Therefore, it is preferable that the erase pulse SEP for continuously changing the applied voltage value in the (n + 1) th positive direction is longer than the nth applied SEP in the positive direction.

  As described above, according to the sixteenth and seventeenth embodiments, by combining a plurality of erase pulses, the probability of resetting the residual wall charges before performing the address selection discharge can be increased, and the driving voltage margin is improved.

  FIG. 26 is a driving waveform diagram showing the eighteenth embodiment, showing an example applied to a high contrast driving method. FIG. 26 illustrates a part of the reset period.

  In these embodiments, by using a combination of a plurality of erasing pulses during the reset period, the erasing of the residual wall charges can be performed with a higher probability than the erasing of the residual wall charges by one erasing discharge.

  In the present embodiment, in the reset period, the narrow pulse is applied first to the first electrode, and the erase pulse SEP for continuously changing the applied voltage value in the positive direction is applied second to the second electrode. Third, a positive direction SEP is applied to the first electrode.

  As described above, according to the eighteenth embodiment, by combining a plurality of erase pulses, the probability of resetting the residual wall charge before performing the address selection discharge can be increased, and the drive voltage margin is improved.

  FIG. 27 is a waveform chart showing the principle of the nineteenth and twentieth embodiments of the present invention. During the reset period, two SEP reset pulses are continuously applied to the Y electrode. The potential of the X electrode serving as the discharge partner electrode is raised by a predetermined level with respect to the first SEP reset pulse, and returned to the original level (for example, 0 V) with respect to the next SEP reset pulse. That is, the maximum potential difference between the X electrode and the Y electrode during the period in which the first SEP reset pulse is applied is smaller than the maximum potential difference during the period in which the second SEP reset pulse is applied. As a result, after reaching the discharge start voltage Vfc of the cell B, the discharge start voltage V5 at which the discharge actually starts after the elapse of a predetermined discharge delay time t becomes substantially equal to Vfc, and the wall charges can be erased.

  With the first SEP reset pulse, it is difficult to erase the wall charges of the cell A. This is because the maximum potential difference (= Vs− (Vfa−Vfb)) between the X electrode and the Y electrode during the application of the first SEP reset pulse is insufficient for resetting the cell A. Therefore, in order to erase the wall charge of the cell having such a relatively high discharge starting voltage, a second SEP reset pulse is applied, and the potential of the X electrode at this time is returned to the original, and the X electrode and the Y electrode are reset. The maximum potential difference between the electrodes is increased (maximum Vs). Thus, the cell A can be reset by the second SEP reset pulse.

  Based on the above principle, the invention can be implemented in various forms described below.

  FIG. 28 is a drive waveform diagram showing a nineteenth embodiment of the present invention. The hardware configuration of the plasma display panel is as described with reference to the related art. In the nineteenth embodiment, two SEP reset pulses are applied to the electrodes Y1 to YN during the reset period. The two SEP reset pulses have the same waveform. That is, the rising voltage gradient of the pulse waveform is equal. However, the two SEP reset pulses may have different waveforms. Discharge occurs using the Y1 to YN electrodes as anodes and the X electrodes as cathodes, thereby eliminating wall charges.

  The potential of the X electrode is the priming voltage Vx during the address period during the first SEP reset pulse period, and is 0 V during the next SEP reset pulse period. The use of the priming voltage Vx does not require a new power supply and is very advantageous in an actual configuration. However, the potential of the X electrode during the first SEP reset pulse may be a value other than the priming voltage. The maximum potential difference between the X electrode and the Y electrode during the first SEP reset pulse period is Vs-Vx, and the maximum potential difference Vs (> Vs-Vx) between the X electrode and the Y electrode during the next SEP reset pulse period.

  FIG. 29 is a modification of the nineteenth embodiment. In the modification shown in FIG. 29, while three SEP reset pulses are applied to the Y1 to YN electrodes, the potentials of the X electrodes during the first and second SEP reset pulse periods are set to Vx1 and Vx2, respectively (Vx1> Vx2> 0V). It is characterized in that the potential difference (maximum potential difference) between the X electrode and the Y electrode is set large in three stages. With this configuration, all cells can be reset more reliably. In this case, if Vx1 = Vx, only Vx2 needs to be newly generated.

  Next, a twentieth embodiment of the present invention will be described with reference to FIG. The twentieth embodiment has a configuration in which a discharge is caused between the Y electrode and the address electrode (A electrode) to erase wall charges. That is, discharge is performed using the Y electrode as an anode and the address electrode as a cathode to erase wall charges. As described above, although the address electrodes are used instead of the X electrodes, the present embodiment is different from the nineteenth embodiment, but the basic principle is the same.

  During the reset period, two SEP reset pulses are applied to the electrodes Y1 to YN. The two SEP reset pulses have the same waveform. That is, the rising voltage gradient of the pulse waveform is equal. However, the two SEP reset pulses may have different waveforms.

  The potential of the address electrode is the address voltage Va during the address period during the first SEP reset pulse period, and is 0 V during the next SEP reset pulse period. The use of the address voltage Va does not require a new power supply and is very advantageous in an actual configuration. However, the potential of the address electrode during the first SEP reset pulse period may be a value other than the address voltage Va. The potential difference between the address electrode and the Y electrode during the first SEP reset pulse period is Vs-Va, and the potential difference between the address electrode and the Y electrode during the next SEP reset pulse period is Vs (> Vs-Va).

  Note that the potential of the X electrode during a period in which the SEP reset pulse is continuously applied is set to Vx, as in the address period.

  FIG. 31 shows a modification of the twentieth embodiment. In the modification shown in FIG. 31, three SEP reset pulses are applied to the Y1 to YN electrodes, while the potentials of the address electrodes during the first and second SEP reset pulse periods are set to Va1 and Va2, respectively (Va1> Va2> 0V). It is characterized in that the potential difference (maximum potential difference) between the address electrode and the Y electrode is set large in three stages. With this configuration, all cells can be reset more reliably. In this case, if Va1 = Va, only the voltage Va2 needs to be newly generated.

  FIG. 32 is a block diagram showing a plasma display driving device of the present invention. This driving device drives the aforementioned three-electrode / surface-discharge / AC-type plasma display.

  The address electrode is connected to an address driver 31 for each address line, and the address driver 31 applies an address pulse at the time of address discharge. The Y electrodes are also connected to the Y scan driver 34 for each electrode. The Y-scan driver 34 is connected to the Y-side common driver 33. A pulse at the time of address discharge is generated from the Y-scan driver 34, and a sustain pulse and the like are generated by the Y-side common driver 33. And applied to the Y electrode.

The SEP driver 42 applies a voltage (the aforementioned SEP reset pulse) to the Y electrode via the resistor 43 via the Y scan driver 34. The voltage waveform at this time is determined by the resistance value R of the resistor 43 and the panel capacitance C, and becomes an exponential curve represented by the following equation.
V = e- ^{(t / CR)}
The X electrodes are commonly connected and taken out over all display lines of panel 30. The X electrode common driver 32 generates a write pulse, a sustain pulse, and the like.

  The X common driver 32, the Y common driver 33, and the Y scan driver 34 are controlled by a control circuit 35. The control circuit 35 is controlled by a synchronization signal (vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC) and a display data signal (DATA) input from outside the device.

  The control circuit 35 has a display data control unit 36 and a panel drive control unit 38. The drive waveform pattern ROM 41 is connected to the control unit 35. The display data DATA from the outside is stored in the frame memory 37 in the display data control section 36 in synchronization with the dot clock CLOCK from the outside, and then output to the address driver 31 as a control signal. The panel drive control unit 38 includes a scan driver control unit 39 and a common driver control unit 40, and operates in synchronization with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC and in accordance with the data in the drive waveform pattern ROM 41. The drive waveform pattern ROM 41 stores data describing waveform patterns of the address electrode drive waveform, the X electrode drive waveform, and the Y1 to YN electrode drive waveforms as shown in FIGS. The panel drive control unit 38 reads out waveform data from the drive waveform pattern ROM 41 in synchronization with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC, and controls the drivers 32, 33, 34, and 42.

  Although the embodiments have been described above, these embodiments can be implemented in any combination.

FIG. 3 is a schematic plan view of a three-electrode / surface-discharge / AC-type PDP. FIG. 3 is a schematic cross-sectional view in a vertical direction of a three-electrode / surface-discharge / AC-type PDP. It is a schematic sectional drawing in the horizontal direction of a three-electrode surface discharge AC type PDP. FIG. 9 is a waveform diagram showing a conventional driving method. 4 is a time chart of an address / sustain discharge separation type / write address system. FIG. 1 is a diagram illustrating residual wall charges. FIG. 2 shows residual wall charges. It is a figure showing the influence by weak electric discharge. FIG. 3 is a drive waveform diagram showing the first embodiment of the present invention. FIG. 6 is a drive waveform diagram showing a second embodiment of the present invention. FIG. 9 is a drive waveform diagram showing a third embodiment of the present invention. FIG. 11 is a drive waveform diagram showing a fourth embodiment of the present invention. FIG. 13 is a drive waveform diagram showing a fifth embodiment of the present invention. FIG. 14 is a drive waveform diagram showing a sixth embodiment of the present invention. FIG. 14 is a drive waveform diagram showing a seventh embodiment of the present invention. FIG. 14 is a drive waveform diagram showing an eighth embodiment of the present invention. FIG. 14 is a drive waveform diagram showing a ninth embodiment of the present invention. It is a drive waveform diagram which shows the 10th Example of this invention. It is a drive waveform diagram which shows the 11th Example of this invention. FIG. 21 is a drive waveform diagram showing a twelfth embodiment of the present invention. It is a drive waveform diagram which shows the 13th Example of this invention. FIG. 24 is a drive waveform layout diagram showing a fourteenth embodiment of the present invention. It is a drive waveform diagram which shows the 15th Example of this invention. It is a drive waveform diagram which shows the 16th Example of this invention. It is a drive waveform diagram which shows the 17th Example of this invention. It is a drive waveform diagram which shows the 18th Example of this invention. It is a wave form diagram which shows the principle of the 19th and 20th Example of this invention. It is a drive waveform diagram which shows the 19th Example of this invention. FIG. 29 is a diagram showing a modification of the nineteenth embodiment shown in FIG. 28. It is a drive waveform diagram which shows the 20th Example of this invention. FIG. 31 is a diagram showing a modification of the twentieth embodiment shown in FIG. 30. FIG. 1 is a diagram showing one embodiment of a driving device for a plasma display (PDP) of the present invention.

Explanation of reference numerals

DESCRIPTION OF SYMBOLS 11 Barrier 12 Cell 13 X electrode 14 Y electrode 15 Address electrode 16 Back glass substrate 17 Phosphor 18 Full glass substrate 19 Sustain electrode 19a Transparent electrode 19b Bus electrode 20 Dielectric layer 21 MgO film 23-28 Reset period 30 Panel 31 Address driver 32 X common driver 33 Y common driver 34 Y scan driver 35 control circuit 36 display data control unit 37 frame memory 38 panel drive control unit 39 scan driver control unit 40 common driver control unit 41 drive waveform pattern ROM

Claims (45)

In a method for driving a plasma display panel, an image of one frame is composed of n subfields, each subfield having a reset period for performing an erase discharge, an address period, and a sustain discharge period.
A first erase discharge by a narrow pulse having a pulse width of 2 μs or less during the reset period;
And a second erasing discharge by an erasing pulse for continuously changing an applied voltage value.   2. The method according to claim 1, wherein an interval between the narrow pulse and the erase pulse is 10 μs or more. First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. The plasma display panel arranged so as to intersect with the electrodes,
2. The plasma display panel according to claim 1, wherein the erase pulse for continuously changing an applied voltage value is applied to the second electrode, and at that time, a voltage pulse is also applied to the third electrode. Drive method. One frame image is composed of n subfields, each of which has a reset period, an address period, and a sustain discharge period in which a sustain discharge is performed by repeatedly applying a sustain discharge pulse. In a method for driving a display panel,
In the reset period, there is a subfield A for performing both an entire write discharge and an erase discharge, and in the reset period, a subfield B for performing an erase discharge without performing a full write discharge,
In a subfield arranged immediately before the subfield B, the pulse width of the last sustain discharge pulse in the sustain discharge period is increased. First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. The plasma display panel arranged so as to intersect with the electrodes,
When the sustain discharge pulse is repeatedly applied to the first and second electrodes during the sustain discharge period, the potential of the third electrode becomes the potential applied to the third electrode during the address period. 5. The driving method for a plasma display panel according to claim 4, wherein: In a method for driving a plasma display panel, an image of one frame is composed of n subfields, each subfield having a reset period for performing an erase discharge, an address period, and a sustain discharge period.
The pulse for performing the erasing discharge in the reset period, from the last sustain discharge pulse in the sustain discharge period of the subfield arranged immediately before, the interval between the sustain discharge pulse in the sustain discharge period and A method of driving a plasma display panel, comprising at least subfields applied at substantially equal intervals. In the reset period, the sub-field A includes both a sub-field A that performs both a full-area write discharge and an erase discharge, and a sub-field B that performs an erasure discharge without performing a full-area write discharge in the reset period.
The interval between the erase pulse applied to perform the erase discharge in the reset period of the subfield B and the last sustain discharge pulse in the sustain discharge period of the immediately preceding subfield is set. 7. The method according to claim 6, wherein an interval between the sustain discharge pulses in the sustain discharge period is substantially equal to the interval between the sustain discharge pulses.   8. The driving method of a plasma display panel according to claim 7, wherein an interval between the erase pulse in the subfield B and the last sustain discharge pulse of the immediately preceding subfield is set to 2 μs or less. . First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. The plasma display panel arranged so as to intersect with the electrodes,
When the sustain discharge pulse is repeatedly applied to the first and second electrodes during the sustain discharge period, the potential of the third electrode becomes the potential applied to the third electrode during the address period. The driving method of a plasma display panel according to claim 6, wherein: First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. Are arranged so as to intersect with the electrodes of
A method of driving a plasma display panel in which one frame of video has a reset period, an address period, and a sustain discharge period in which a sustain discharge is performed by repeatedly applying a sustain discharge pulse to the first and second electrodes. At
During the sustain discharge period, the potential of the third electrode is maintained, and the voltage pulse applied to the third electrode rises simultaneously with the fall of the last sustain discharge pulse in the sustain discharge period. A method for driving a plasma display panel, comprising:   The method of driving a plasma display panel according to claim 10, wherein an interval between the sustain discharge pulses in the sustain discharge period is set to 1 µs or less. First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. Are arranged so as to intersect with the electrodes of
In a method for driving a plasma display panel, an image of one frame is composed of n subfields, each subfield having a reset period, an address period, and a sustain discharge period.
In the reset period, the sub-field A includes both a sub-field A that performs both a full-area write discharge and an erase discharge, and a sub-field B that performs an erasure discharge without performing a full-area write discharge in the reset period.
A driving method for a plasma display panel, further comprising performing an erasing discharge before performing the entire-area writing discharge during the reset period in the subfield A.   The erasing discharge to be performed before the whole-area writing discharge may be an erasing discharge in which one of a narrow pulse having a pulse width of 2 μs or less, an erasing pulse for continuously changing an applied voltage value, or both is applied. 13. The method according to claim 12, wherein the erasing discharge is performed a plurality of times by applying the voltage.   14. The plasma display panel according to claim 13, wherein the erase pulse for continuously changing an applied voltage value is applied to the second electrode, and at that time, a voltage pulse is also applied to the third electrode. Drive method. In the reset period,
13. The driving method for a plasma display panel according to claim 12, wherein a voltage applied to the third electrode at the time of performing an erasing discharge before performing the entire-area writing discharge is set to 0V. . First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. Are arranged so as to intersect with the electrodes of
In a method of driving a plasma display panel, an image of one frame has a reset period in which a full write discharge and an erase discharge are performed, an address period, and a sustain discharge period.
A method for driving a plasma display panel, comprising: applying a narrow pulse having a pulse width of 2 μs or less to the third electrode after a fall of an entire write pulse for performing the entire write discharge during the reset period. . In the reset period,
17. The method of driving a plasma display panel according to claim 16, wherein a narrow pulse having a pulse width of 2 [mu] s or less is applied to the third electrode within 10 [mu] s after the fall of the entire write pulse. In the reset period,
17. The method of driving a plasma display panel according to claim 16, wherein an erasing pulse for continuously changing an applied voltage value is applied to the second electrode after the fall of the entire surface write pulse. One frame of video is composed of n subfields each having a predetermined weight and a rest period during which no drive waveform is output, and each of the subfields includes a reset period, an address period, a sustain discharge period, A method for driving a plasma display panel having
In the reset period, there is a subfield A for performing both an entire write discharge and an erase discharge, and in the reset period, a subfield B for performing an erase discharge without realizing a full write discharge,
The driving method of a plasma display panel according to claim 1, wherein the pause period is a self-erasing period after application of a full-area write pulse for performing a full-area write discharge. First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. Are arranged so as to intersect with the electrodes of
In a method for driving a plasma display panel, an image of one frame is composed of n subfields, each subfield having a reset period, an address period, and a sustain discharge period.
During the reset period, a first step of applying a narrow pulse having a pulse width of 2 μs or less, a second step of applying an erase pulse for continuously changing the applied voltage value in the positive direction, A third step of applying an erasing pulse for continuously changing an applied voltage value or an erasing pulse in a negative direction.   21. The method according to claim 20, further comprising applying a fourth step of applying an erasing pulse for continuously changing a voltage value applied in a positive direction during the reset period.   22. The driving method of a plasma display panel according to claim 21, wherein the (n + 1) th positive erase pulse is made longer than the nth positive erase pulse. First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. Are arranged so as to intersect with the electrodes of
In a method for driving a plasma display panel, an image of one frame is composed of n subfields, each subfield having a reset period, an address period, and a sustain discharge period.
A first step of applying a narrow pulse having a pulse width of 2 μs or less during the reset period, and a second step of applying a first erase pulse for continuously changing an applied voltage value in a positive direction; A third step of applying a second erase pulse for continuously changing the applied voltage value in the positive direction. First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. In a method for driving a plasma display panel arranged so as to intersect with the electrodes,
An image of one frame is composed of n subfields, each of which has a reset period, an address period, and a sustain discharge period,
In the reset period, a plurality of reset pulses for continuously changing a voltage applied to the electrode and causing a discharge at a potential close to a discharge starting voltage to erase wall charges are applied. Display panel driving method.   25. The method of driving a plasma display panel according to claim 24, wherein the plurality of reset pulses are applied to a second electrode, and the potential of the first electrode has a different value for each reset pulse.   25. The method according to claim 24, wherein the plurality of reset pulses are applied to a second electrode, and the potential of the third electrode has a different value for each reset pulse.   The method according to any one of claims 24 to 26, wherein the plurality of reset pulses have the same voltage gradient.   26. The maximum potential difference between the first electrode and the second electrode of the (n + 1) th reset pulse for the plurality of reset pulses is larger than the maximum potential difference in the nth reset pulse. Driving method of a plasma display panel.   27. The maximum potential difference between the second electrode and the third electrode of the (n + 1) -th reset pulse for the plurality of reset pulses is larger than the maximum potential difference in the n-th reset pulse. Driving method of a plasma display panel.   26. The plasma display according to claim 25, wherein at least one of the potentials of the first electrode which is different for each reset pulse is equal to a potential applied to the first electrode during the address period. Panel driving method.   27. The plasma display according to claim 26, wherein at least one of the potentials of the third electrode, which is different for each reset pulse, is equal to a potential applied to the third electrode during the address period. Panel driving method. First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. A plasma display panel arranged to intersect the electrodes of
A first control unit for driving a plasma display panel including a reset period, an address period, and a sustain discharge period, wherein each of the sub-fields comprises an image of one frame including n subfields;
A second control unit that continuously changes the voltage applied to the electrodes during the reset period and applies a plurality of reset pulses for erasing wall charges by causing discharge to occur at a potential close to the discharge start voltage. A driving device for a plasma display panel, comprising: First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. Are arranged so as to intersect with the electrodes of
An image of one frame is composed of n subfields, and each of the subfields includes a reset period, an address period, and a sustain discharge pulse applied repeatedly to the first and second electrodes. A method for driving a plasma display panel having a sustain discharge period for performing a sustain discharge,
In the reset period, there is a subfield A for performing both an entire write discharge and an erase discharge, and in the reset period, a subfield B for performing an erase discharge without performing a full write discharge,
In the subfield arranged immediately before the subfield B, the pulse width of the last sustain discharge pulse to the second electrode during the sustain discharge period is increased. Method.   The method according to claim 33, wherein a potential of the third electrode during the sustain discharge period is equal to a potential applied to the third electrode during the address period. One frame image is composed of n subfields, each of which has a reset period, an address period, and a sustain discharge period in which a sustain discharge is performed by repeatedly applying a sustain discharge pulse. In a method for driving a display panel,
The pulse width of the last sustain discharge pulse in the sustain discharge period of the predetermined subfield is increased, and the pulse width is 2 μs or less in the reset period of the next subfield of the predetermined subfield. A method for driving a plasma display panel, comprising performing an erasing discharge by a pulse. In a method for driving a plasma display panel, an image of one frame has a reset period, an address period, and a sustain discharge period in which a sustain discharge is performed by repeatedly applying a sustain discharge pulse.
A method of driving a plasma display panel, wherein the pulse widths of the first and last sustain discharge pulses in the sustain discharge period are increased. First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. Are arranged so as to intersect with the electrodes of
A method of driving a plasma display panel in which one frame of video has a reset period, an address period, and a sustain discharge period in which a sustain discharge is performed by repeatedly applying a sustain discharge pulse to the first and second electrodes. At
During the sustain discharge period, the potential of the third electrode is maintained and applied to the third electrode simultaneously with the trailing edge of the last sustain discharge pulse to the second electrode during the sustain discharge period. A driving method of a plasma display panel, characterized in that a voltage pulse falling is dropped. First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. Are arranged so as to intersect with the electrodes of
In a method for driving a plasma display panel, an image of one frame has a reset period in which both a full write discharge and an erase discharge are performed, an address period, and a sustain discharge period.
During the reset period, before performing the full-area write discharge, a narrow pulse having a pulse width of 2 μs or less is applied to the first electrode, and an erase pulse for continuously changing an applied voltage value is applied to the second electrode. A driving method for a plasma display panel, wherein an erasing discharge is further performed by applying a voltage to the electrodes.   39. The plasma display panel according to claim 38, wherein a voltage pulse is also applied to the third electrode when the erase pulse for continuously changing an applied voltage value is applied to the second electrode. Drive method. In the reset period,
39. The driving method of a plasma display panel according to claim 38, wherein a voltage applied to the third electrode at the time of performing an erase discharge before performing the entire-area write discharge is set to 0V. . In a method for driving a plasma display panel, an image of one frame is composed of n subfields, each subfield having a reset period, an address period, and a sustain discharge period.
In the reset period, there is a subfield A for performing both an entire write discharge and an erase discharge, and in the reset period, a subfield B for performing an erase discharge without performing a full write discharge,
During the reset period of the sub-field B, a first step of applying an erasing pulse for continuously changing the applied voltage value in the positive direction, and an erasing pulse for continuously changing the applied voltage value in the negative direction, or a negative step. A method for driving a plasma display panel, comprising: a second step of applying an erasing pulse in a positive direction; and a third step of applying an erasing pulse for continuously changing an applied voltage value in a positive direction. In a method for driving a plasma display panel, an image of one frame is composed of n subfields, each subfield having a reset period, an address period, and a sustain discharge period.
During the reset period, a first erase discharge by a narrow pulse having a pulse width of 2 μs or less, a second erase discharge by a rising of an erase pulse for continuously changing an applied voltage value in a positive direction, and A method for driving a plasma display panel, comprising: a third erasing discharge by a falling edge of an erasing pulse for continuously changing an applied voltage value. In a method for driving a plasma display panel, an image of one frame is composed of n subfields, each subfield having a reset period, an address period, and a sustain discharge period.
In the reset period, there is a subfield A for performing both an entire write discharge and an erase discharge, and in the reset period, a subfield B for performing an erase discharge without performing a full write discharge,
A method of driving a plasma display panel, wherein a reset pulse for continuously changing a voltage applied to an electrode is applied during a reset period of the subfield B. First and second electrodes are arranged in parallel on a first substrate, and a third electrode is formed on the first substrate or on a second substrate facing the first substrate. The plasma display panel arranged so as to intersect with the electrodes,
44. The driving of the plasma display panel according to claim 43, wherein when applying the reset pulse for continuously changing an applied voltage value to the second electrode, a voltage pulse is also applied to the third electrode. Method. In a method for driving a plasma display panel, an image of one frame is composed of n subfields, each subfield having a reset period, an address period, and a sustain discharge period.
In the reset period, there is a subfield A for performing both an entire write discharge and an erase discharge, and in the reset period, a subfield B for performing an erase discharge without performing a full write discharge,
A method of driving a plasma display panel, wherein a plurality of reset pulses for continuously changing a voltage applied to an electrode are applied during a reset period of the subfield B.

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