JP4216891B2 - Driving method of plasma display panel - Google Patents

Description

  In recent years, in various display devices, the information to be displayed and the installation conditions have been diversified, the screen has been enlarged and the definition has been increased. Therefore, in display devices such as plasma display panels (PDP), CRTs, LCDs, ELs, fluorescent display tubes, and light emitting diodes used for these, improvement in display quality is required to cope with these trends. ing.

  Among the above display devices, the PDP has been actively developed recently because it has excellent features such as no flickering, easy screen enlargement, high brightness and long life. The PDP includes a two-electrode type that performs selective discharge (address discharge) and sustain discharge with two electrodes, and a three-electrode type that performs address discharge using a third electrode.

  In a color PDP that performs gradation display, a phosphor formed in a discharge cell is excited by ultraviolet rays generated by discharge, but this phosphor is vulnerable to the impact of ions, which are positive charges generated simultaneously by discharge. There are drawbacks. The two-electrode type described above has a configuration in which the phosphor directly hits ions, which may cause a reduction in the lifetime of the phosphor.

  As a color PDP capable of avoiding this problem, a three-electrode structure using surface discharge is generally known. Further, even in this three-electrode type, there are cases where the third electrode is formed on the substrate on which the first and second electrodes for sustaining discharge are disposed, and on the other substrate facing each other. Even when the above three types of electrodes are formed on the same substrate, there are cases where the third electrode is disposed on the two electrodes that perform the sustain discharge and the third electrode is disposed below the third electrode. .

  Furthermore, there are a case where visible light emitted from a phosphor is viewed through the phosphor (transmission type) and a case where the reflection from the phosphor is viewed (reflection type). In addition, a cell to be discharged is disconnected from the adjacent cell by a barrier (also referred to as a rib or a barrier). This barrier is provided in four directions so as to surround the discharge cell and completely sealed, or provided in only one direction, and the other direction is used to break the coupling by optimizing the gap (distance) between the electrodes. There is.

  The present invention relates to a method for driving the above-described various types of PDPs.

  In this specification, a panel in which the third electrode is formed on an opposite substrate different from the substrate of the electrode that performs the sustain discharge, the barrier is in the vertical direction (that is, perpendicular to the first electrode and the second electrode, A description will be given based on a reflection type example in which a part of the sustain electrode is formed of a transparent electrode.

  FIG. 1 is a schematic plan view of the above-described three-electrode / surface discharge / AC type PDP. FIG. 2 is a schematic sectional view in the vertical direction of the three-electrode / surface discharge / AC type PDP. Similarly, FIG. 3 is a schematic sectional view in the horizontal direction of the three-electrode / surface discharge / AC type PDP. . 2 and 3 show one discharge cell.

  A PDP is basically composed of two glass substrates. The front glass substrate 18 includes X electrodes 13 and Y electrodes 14 which are parallel sustain electrodes 19, and these electrodes are constituted by a transparent electrode 19a and a bus electrode 19b. Since the transparent electrode 19a has a role of transmitting the reflected light from the phosphor 17, the transparent electrode 19a is formed of ITO (transparent conductive film mainly composed of oxide oxide) or the like. Further, the bus electrode 19b needs to be formed with low resistance to prevent voltage drop due to electrode resistance, and is formed of Cr or Cu.

  Further, they are covered with a dielectric layer (glass) 20, and an MgO (magnesium oxide) film 21 is formed as a protective film on the discharge surface. Further, the address electrode 15 is formed on the rear glass substrate 16 facing the front glass substrate 18 so as to be orthogonal to the sustain electrodes 19. Further, a barrier 11 is formed between the address electrodes 15, and a phosphor 17 having red, green, and blue emission characteristics is formed between the barrier electrodes 11 so as to cover the address electrode 15. Two glass substrates are assembled so that the ridge of the barrier 11 and the MgO 21 surface are in close contact with each other.

  FIG. 4 is a drive waveform diagram showing the prior art, and shows a method for driving the PDP shown in FIGS. Here, one subfield period in the so-called “address / sustain discharge period separated type (ADS) / write address system” is shown. In this example, one subfield is separated into a reset period, an address period, and a sustain discharge period. In the reset period, for example, all the Y electrodes are first set to 0 V level, and at the same time, a full-surface writing pulse composed of voltage Vs + Vw (about 330 V) is applied to the X electrodes. As a result, discharge is performed in all cells of all display lines regardless of the previous display state. The address electrode potential at this time is about 100 V (Vaw).

  Next, the potential of the X electrode and the address electrode becomes 0 V, and the voltage of the wall charge itself exceeds the discharge start voltage in all the cells, and the discharge is started. Since this discharge has no potential difference between the electrodes, no wall charge is formed, and the space charge self-neutralizes and the discharge ends. This is so-called self-erasing discharge. By this self-erasing discharge, the state of all the cells in the panel becomes a uniform state without wall charges. This reset period has the effect of making all cells the same regardless of the lighting state of the previous subfield, and the next address (writing) discharge can be stably performed.

  Next, in the address period, address discharge is performed line-sequentially in order to turn on / off the cells according to the display data. First, a scan pulse of −Vy level (about −150 V) is applied to the Y electrode, and an address of voltage Va (about 50 V) is applied to an address electrode corresponding to a cell that causes a sustain discharge in the address electrode, that is, a cell to be lit. A pulse is selectively applied.

  As a result, a discharge occurs between the address electrode and the Y electrode of the cell to be lit, and this is used as a priming (fire) to immediately shift to a discharge between the X electrode (voltage Vx = 50 V) and the Y electrode. The former discharge is called “priming address discharge”, and the latter is called “main address discharge”. As a result, the amount of wall charges capable of sustaining discharge is accumulated on the MgO surface on the X electrode and Y electrode of the selected cell of the selected line.

  Thereafter, the same operation is sequentially performed for other display lines, and new display data is written in all the display lines.

  Thereafter, in the sustain discharge period, a sustain pulse composed of a voltage Vs (about 180 V) is alternately applied to the Y electrode and the X electrode to perform a sustain discharge, and a video display of one subfield is performed. In the “address / sustain discharge separation type / write address system”, the luminance is determined by the length of the sustain discharge period, that is, the number of sustain pulses.

  FIG. 5 is a time chart of the address / sustain discharge separation type / address address system, and shows a driving method in the case of performing 16 gradation display as an example of multi gradation display. In this example, one frame is divided into four subfields (SF1, SF2, SF3, SF4). In these subfields SF1 to SF4, the reset period and the address period have the same length. The length of the sustain discharge period is, for example, a ratio of 1: 2: 4: 8. Therefore, by selecting the subfield to be lit, it is possible to display 16 levels of gradation from 0 to 15.

  In the above driving method, each subfield has a reset period, and full-surface write discharge is performed by applying a full-surface write pulse in each subfield. For this reason, light emission in the reset period that does not originally contribute to video display occurs in each subfield, which contributes to lowering the contrast of the display image.

In order to solve this problem, the applicant of the present application has invented a novel driving method that has achieved a high contrast by reducing the number of full-surface writing discharges per frame, and has already filed an application (Patent Document 1). In this method, the full-surface write discharge in the reset period is performed only in some subfields, and only the erase discharge is performed in the reset period in the other subfields. By reducing the number of full-surface write discharges, high-contrast driving with reduced light emission that does not contribute to video display is possible.
JP-A-5-313598

  There is an allowable range for the voltage values of various pulses for realizing the driving in which the ON cell is properly lit and the OFF cell is not lit. Here, the voltage range from the minimum value to the maximum value is referred to as a drive voltage margin.

  First, the first problem relating to the drive voltage margin will be described. In narrow pulse erasing at the counter electrode of a simple matrix panel (double electrode), the external applied voltage is cut off during discharge formation, so that most of the charged particles generated during discharge remain in the discharge cell space, and the panel dielectric It is attracted to the wall charges on the layer by electrostatic attraction and recombined on the wall surface to be erased. On the other hand, in a three-electrode panel having surface discharge electrodes, this narrow pulse erasing operation is performed on the surface discharge electrodes on the same substrate, so that charged particles in the discharge cell space are affected by the potential on the counter electrode.

  FIG. 6 is a diagram 1 showing the residual wall charge, and shows the residual wall charge when the counter electrode is Va during the neutralization discharge of the narrow erase in the reset period. In this case, a large amount of negative polarity charge is accumulated on the counter electrode, resulting in erasure failure.

  On the other hand, FIG. 7 is a diagram 2 showing the residual wall charges, and shows the residual wall charges when the counter electrode is GND during the neutralization discharge of the narrow erase in the reset period. In this case, a large amount of positive polarity charge is accumulated on the counter electrode, resulting in erasure failure.

  In these cases, it has been found that this erasure failure inhibits selective wall charge formation in the next address period, resulting in deterioration of the drive voltage margin.

  Next, the second problem related to the drive voltage margin will be described. When performing a narrow erase discharge during the reset period, if the discharge starts more quickly than expected due to pixel non-uniformity and changes in temperature conditions, not only the necessary wall charge can be erased, but also the wall charge before erasing. There is a risk that a wall charge having an inverted polarity with respect to the state may be formed, leading to a decrease in drive voltage margin.

  Next, a third problem relating to the drive voltage margin will be described. FIG. 8 is a diagram showing the influence of weak discharge, in which the discharge light emission pulse (light) is shown together with the A (address), X, and Y electrode pulses. When this discharge light emission pulse is observed, weak light emission exists in the gap between the sustain discharge pulse and the next sustain discharge pulse. Since this weak discharge has little influence on the next sustain discharge itself, the sustain discharge can be normally repeated.

  However, it has been found that this weak discharge has a great influence on the erasing discharge (the narrow discharge is used in FIG. 8) in the reset period. Specifically, the wall charge formed by the sustain discharge is reduced by this weak discharge, and normal erasure discharge is hindered, resulting in defective erasure of the wall charge. This leads to a reduction in drive voltage margin.

  Next, a fourth problem relating to the drive voltage margin will be described. This problem is particularly problematic in the above-described high contrast driving. The high-contrast drive performs only erasing discharge during the reset period except for some subfields. As this erasing discharge, when an erasing pulse for erasing only the cells lit in the immediately preceding subfield is applied, the residual wall on the counter electrode (address electrode) compared with the case of using the full-surface writing / self-erasing pulse. It was found that the charge erasing ability was weakened.

  Furthermore, since the residual wall charges on the counter electrode that cannot be reset each time the subfields are overlapped, the burden on the full-frame write discharge in the next frame has become very heavy. For this reason, there is a problem that the potential distribution of each cell does not become uniform even after the entire write discharge, or the subsequent address discharge is adversely affected. As a result, the drive voltage margin is reduced.

  Next, a fifth problem relating to the drive voltage margin will be described. FIG. 5 is a diagram showing a time chart of the address / sustain discharge separated type / write address system, and shows a reset period, an address period, a sustain discharge period, and a rest period. Due to fluctuations in the total time of the driving period due to fluctuations in the number of sustaining voltage pulses, the rest period fluctuates, and as a result, the discharge state due to voltage pulses applied after the rest period fluctuates and must be reset as a result. The wall charge amount fluctuated, resulting in a decrease in drive voltage margin.

  Next, a sixth problem relating to the drive voltage margin will be described. This problem is particularly problematic in high contrast driving. In high contrast driving, except for some subfields, only erasing discharge is performed during the reset period. In this high contrast driving, there is a probability that a single voltage pulse for erasing discharge will reset the charge. Since it is low, it causes erasure failure. This has led to a reduction in drive voltage margin.

  Further, the wall charge erasing by the erasing pulse that continuously changes the voltage value uses a non-linear waveform determined by the resistor and the panel capacitance from the simplicity of the circuit. In the case of such a non-linear waveform, there is a problem in that an erasure failure occurs when discharging is performed at a place where the slope of the erase waveform is steep.

The present invention has been made in view of the above, and an object thereof is to provide a driving how the possible plasma display improvement of driving voltage margin in driving a plasma display.

Accordingly, the present invention provides a plasma display panel having a first sustain electrode group , a second sustain electrode group, and an address electrode group intersecting with the first sustain electrode group and a second sustain electrode group, and displaying one frame image using a plurality of subfields. In the driving method, at least one subfield includes an address period for selecting cells to be lit in a plurality of display lines, and a plurality of display line cells selected in the address period after the address period. A sustain discharge period for generating discharge by repeatedly applying a sustain discharge pulse to each of the sustain electrode group and the second sustain electrode group, and in the sustain discharge period, a pulse is applied to the address electrode group, pulses applied to the end to each of the first sustain electrode group and the second sustain electrode group, a portion Generates an erase pulse by overlapping the time you are, and fall of the last pulse of the first sustain electrode group and pulse applied to the second sustain electrode group, is applied to the address electrodes In this method, the falling edges of the pulses are synchronized pulses.

According to the present invention, a reliable reset is possible by using a narrow pulse, and the drive voltage margin is improved.

  Next, the best mode for carrying out the present invention will be described based on the following embodiments with reference to the drawings.

  FIG. 9 and FIG. 10 are drive waveform diagrams showing the first and second embodiments, respectively, in which the present embodiment is applied to the high contrast driving method. That is, in the subfield SFn + 1, the wall charges are erased by applying an erase pulse composed of a narrow pulse (for example, a pulse width of 2 μs or less) to the X electrode without performing full-surface write discharge. The narrow pulse terminates the application of the pulse voltage immediately after the discharge is formed, and most of the charged particles generated during the discharge remain in the discharge cell space, and are statically charged to the wall charges on the panel dielectric layer. It is adsorbed by the electric attractive force and recombined on the wall surface to be erased. This is the same in the following embodiments.

  Now, it is known that the panel operates stably by setting the counter electrode potential during the sustain discharge period of the three-electrode structure panel to an intermediate value of the potential difference between the sustain discharge electrodes. For this reason, the counter electrode is maintained at a positive potential during the sustain discharge period. This also applies to erasing discharge with a narrow pulse (for example, a pulse width of 2 μs or less).

  For this reason, in this embodiment, the counter electrode potential when the wall charges are formed by performing the erase discharge by applying the narrow pulse is set to the potential difference Va between the sustain discharge electrodes. Then, the above-mentioned narrow erase discharge is performed by making the falling of the counter electrode potential Va coincide with the rising of the narrow pulse and setting the potential at the neutralization discharge caused by the falling of the narrow pulse to GND. The influence of the counter electrode potential at the time is avoided.

  The second embodiment shown in FIG. 10 is a modification of the first embodiment shown in FIG. Although the waveforms themselves applied to the X and Y electrodes are different from those of the first embodiment shown in FIG. 9, the potential difference applied between the XY electrodes is the same as that of the first embodiment shown in FIG. It can be said that the driving is substantially the same.

  According to the first and second embodiments described above, accumulation of a large amount of negative (or positive) polarity charges due to the influence of the counter electrode potential can be avoided and more complete erasure can be achieved, and the drive voltage margin can be improved.

  Although the present embodiment has been described based on the high contrast driving method, the principle of the present embodiment is not necessarily limited to the high contrast driving method. For example, the effect similar to that of the present embodiment can be expected in the case where full-surface write / narrow erase discharge is performed in the reset period of all subfields. On the contrary, it will be effective even in the case where the narrow erase discharge is performed without performing the full-surface write discharge in the reset period of all the subfields.

  FIG. 11 is a drive waveform diagram showing the third embodiment, and shows high contrast drive. In the cell that has undergone the final sustain discharge in the n-th subfield SFn, positive charge is accumulated in the X electrode and negative charge is accumulated in the Y electrode. In the figure, the approximate amount of wall charges on the X and Y electrodes is conceptually shown. In SFn + 1, which is the next subfield, wall charges are erased by applying a narrow pulse, which is the first erase pulse, to the X electrode without performing full-surface write discharge.

  At this time, if the discharge start is earlier than expected due to the non-uniformity of the pixel or the change in the temperature condition, wall charges having opposite polarities to the wall charges before erasing are accumulated in both X and Y. . In the example of the figure, although it is decreased from before the erase pulse is applied, wall charges are accumulated on the X and Y electrodes, resulting in an erase failure state.

  However, in the present embodiment, the erase failure state is made closer to the complete erase state by SEP (Slope Erase Pulse) which is the second erase pulse arranged next. Note that the SEP is desirably provided at an interval of 10 μs or more from the narrow pulse which is the first erase pulse. This is because if the interval between the SEP and the narrow pulse that is the first erase pulse is 10 μs or less, the erase operation is performed while the charge state remains unstable.

  In the example of FIG. 11, after the erase operation by the second erase pulse, the wall charges remaining on the X and Y electrodes are very small, and this residual charge has an adverse effect on the subsequent address period. Never give.

  As the second erasing pulse, the wall charge erasing amount is not sufficiently smaller than the narrow width erasing, but it is desirable to use SEP because there is no fear of charge reversal unlike the narrow width. SEP is a pulse that rises with a gentle slope, and discharge is performed sequentially from the cell where the rising pulse voltage reaches the discharge voltage. Therefore, each cell substantially has an optimum voltage (a voltage substantially equal to the discharge start voltage). ) Is applied. For this reason, the charge whose polarity is reversed does not remain in the cell.

  According to the third embodiment described above, in the erasing operation in the reset period, almost complete erasing operation can be realized without causing erasure failure, and the drive voltage margin is improved. It should be noted that this embodiment will be effective even in the case where narrow erase discharge is performed without performing full-surface write discharge even in the reset period of all subfields. As the plurality of erasing discharges, combinations other than the narrow width / SEP combination, for example, narrow width / small width, SEP / SEP, SEP / thin width, and the like are also possible.

  FIG. 12 is a drive waveform diagram showing the fourth embodiment, and this embodiment is applied to the high contrast driving method. That is, in the subfield SFn + 1, the wall charges are erased by applying the erase pulse composed of the narrow pulse to the X electrode without performing the entire surface write discharge. As described with reference to FIG. 8, a weak discharge occurs after the falling of each sustain pulse in the sustain discharge period, and in particular, the weak discharge generated after the trailing end of the last sustain discharge pulse is performed thereafter. The erase discharge was adversely affected.

  However, in this embodiment, the pulse width of the last sustain discharge pulse is made longer than the pulse widths of the other sustain discharge pulses. As a result, in this embodiment, the weak discharge does not occur after the trailing edge of the last sustain discharge pulse with the long pulse width, and the subsequent narrow discharge can be normally performed. It has been experimentally confirmed that the pulse width of the last sustain discharge pulse is required to be at least 3 μs or more in order to prevent weak discharge.

  According to the fourth embodiment described above, it is possible to prevent the erase operation failure in the reset period caused by the weak discharge after the last sustain discharge pulse falls, and the drive voltage margin is improved.

  Although the present embodiment has been described based on the high contrast driving method, the principle of the present embodiment is not necessarily limited to the high contrast driving method. Even if the driving method is such that the full address discharge is performed in the reset period of all the subfields, the same effect as in this embodiment can be expected. Conversely, it will be effective even in the case where narrow erase discharge is performed without performing full-surface write discharge in the reset period of all subfields.

  FIG. 13 is a drive waveform diagram showing the fifth embodiment, and this embodiment is applied to the high contrast driving method. That is, in the subfield SFn + 1, the wall charges are erased by applying the erase pulse composed of the narrow pulse to the X electrode without performing the entire surface write discharge. In the present embodiment, the interval between the last sustain discharge pulse and the narrow pulse applied in the reset period in the subfield where no full-surface write discharge is performed is set as the sustain discharge pulse in the sustain discharge period in the same subfield. It is assumed to be as narrow as the interval between them.

  As described with reference to FIG. 8, a weak discharge occurs after the trailing edge of the last sustain discharge pulse, which adversely affects normal erase discharge. However, it has been found that this weak discharge has almost no influence on the sustain discharge pulse applied continuously as described above. The reason why the weak discharge does not affect each sustain discharge is considered to be that the next pulse is applied immediately after the occurrence of the weak discharge.

  In the present embodiment, in consideration of this point, the interval between the last sustain discharge pulse and the narrow pulse during the reset period in the subsequent subfield (the one that does not perform full address discharge) is the interval between the sustain discharge pulses. As narrow as that. This interval is suitably 2 μs or less.

  As described above, according to the fifth embodiment, as can be seen from the light pulse in FIG. 11, although the weak discharge occurs after the last sustain discharge pulse falls, the subsequent narrow discharge can be normally performed, and the drive voltage Margin is improved.

  Although the present embodiment has been described based on the high contrast driving method, the principle of the present embodiment is not necessarily limited to the high contrast driving method. Even if the driving method is such that the full address discharge is performed in the reset period of all the subfields, the same effect as in this embodiment can be expected. In this case, the interval between the last sustain discharge pulse and the entire writing pulse during the reset period in the subsequent subfield is set to be as narrow as the interval between the sustain discharge pulses. Conversely, it may be effective even in the case where erase discharge (for example, narrow width erase) is performed without performing full-surface write discharge in the reset period of all subfields.

  FIG. 14 is a drive waveform diagram showing the sixth embodiment, which is a combination of the fourth and fifth embodiments. That is, in the present embodiment, the last sustain discharge pulse has a longer pulse width than the other sustain discharge pulses. In addition, the interval between the last sustain discharge pulse and the narrow pulse during the reset period in the next subfield (without full address discharge) is the same as the interval between the sustain discharge pulses during the sustain discharge period. Narrow to the extent.

  Since the present embodiment includes the contents of the fourth embodiment, weak discharge should not occur when the last sustain discharge pulse falls. However, this embodiment further adds the contents of the fifth embodiment so that normal narrow erase can be realized even if a weak discharge occurs due to variations in panel conditions. Thereby, the present embodiment makes the erasure discharge more reliable.

  According to the sixth embodiment described above, it is possible to prevent the erasing operation failure in the reset period caused by the weak discharge after the last sustain discharge pulse falls, and the drive voltage margin is improved. Further, the present invention is not limited to the high contrast driving method shown in FIG.

  FIG. 15 is a drive waveform diagram showing the seventh embodiment. In the subfield SFn + 1, wall charges are erased by applying a full-surface write / self-erase pulse to the X electrode.

  In the present embodiment, the wall charges on the address electrode, which is the counter electrode, are made uniform by simultaneously performing the falling edge of the last sustain discharge pulse and the falling edge of the counter electrode potential Va. It has been confirmed that the interval between the sustain discharge pulses in the sustain discharge period is desirably 1 μs or less in order to reduce wall charges on the third electrode due to weak discharge.

  According to the seventh embodiment described above, the wall charges on the address electrode which is the counter electrode can be made uniform, the erasure operation failure in the reset period can be prevented, and the drive voltage margin can be improved. Further, the present embodiment is not limited to the driving method shown in the figure, and may be effective in, for example, a high contrast driving method.

  Next, FIGS. 16, 17 and 18 are drive waveform diagrams showing the eighth, ninth and tenth embodiments, respectively, showing an example applied to the high contrast driving method. In these embodiments, a pulse having an erasing function, for example, a narrow pulse, SEP, or both, is applied immediately before a subfield for performing full-surface write discharge. By applying this erase pulse, it is possible to reduce the burden on the few full surface write discharges. That is, since the residual wall charge state before the full-surface write discharge can always be made the same regardless of the lighting state of the immediately preceding subfield, the residual wall charge on the counter electrode can be erased more completely. it can.

  The eighth embodiment is an example in which the erase pulse in the reset period of the subfield SFn + 1 is the full-surface write / self-erasure pulse, and the narrow pulse is arranged next to the sustain discharge period of the immediately preceding subfield SFn.

  The ninth embodiment is an example in which the erase pulse in the reset period of the subfield SFn + 1 is the full-surface write / self-erasure pulse, and the narrow width and SEP are arranged next to the sustain discharge period of the immediately preceding subfield SFn.

  The tenth embodiment is an example in which the erase pulse in the reset period of the subfield SFn + 1 is the full-surface write / self-erasure pulse, and the narrow pulse and the SEP are arranged after the sustain discharge period of the immediately preceding subfield SFn.

  With these pulses, the residual wall charge state before the full-surface write discharge can be made substantially the same regardless of the lighting state of the immediately preceding subfield.

  According to the eighth, ninth, and tenth embodiments described above, the opposite side charge can be erased more completely by the full write / self-erase pulse in the reset period, and the drive voltage margin is improved.

  Although the present embodiment is described based on the high contrast driving method, the principle of the present embodiment is not necessarily limited to the high contrast driving method. Even in the driving method in which the full-surface write discharge is performed in the reset period of all the subfields, the same effect as in this embodiment can be expected.

  FIG. 19 is a drive waveform diagram showing the eleventh embodiment, showing an example applied to a high contrast drive system. In this embodiment, the erase discharge is further performed before the full-surface write discharge, and the voltage applied to the address electrode as the third electrode at that time is set to 0V. In this way, by setting the voltage applied to the address electrode at the time of erasing discharge to 0 V, the residual wall charge state before the full-surface write discharge can always be made the same, so the residual wall charge on the counter electrode can be erased. It can be done in a more complete form.

  According to the eleventh embodiment described above, the counter charge on the opposite side can be erased in a more complete manner by the whole surface writing / self-erasing pulse in the reset period, and the drive voltage margin is improved.

  Although the present embodiment is described based on the high contrast driving method, the principle of the present embodiment is not necessarily limited to the high contrast driving method. Even in the driving method in which the full-surface write discharge is performed in the reset period of all the subfields, the same effect as in this embodiment can be expected.

  FIG. 20 is a drive waveform diagram showing the twelfth embodiment, and this embodiment is applied to the high contrast driving method. In this embodiment, before the full write discharge is performed in the reset period, an erase discharge is further performed. After the fall of the full write pulse for performing the full write discharge, a narrow pulse is applied to the address electrode which is the third electrode. Applied. As a result, even if the residual wall charges remain after the entire write discharge, the residual wall charges on the address electrodes can be erased more completely.

  Note that it is experimentally desirable that the interval between the fall of the full write pulse for carrying out full write discharge and the rise of the narrow pulse applied to the address electrode as the third electrode is preferably within 10 μs. It has been confirmed.

  According to the above twelfth embodiment, the counter charge on the opposite side can be erased in a more complete manner by the full-surface writing / self-erasing pulse in the reset period, and the drive voltage margin is improved. Further, the present invention is not limited to the high contrast driving method shown in FIG.

  FIG. 21 is a drive waveform diagram showing the thirteenth embodiment, and shows only a part of the reset period.

  In this embodiment, an address narrow pulse is applied to the address electrode, which is the third electrode, and the applied voltage value is continuously changed to the second electrode after the entire write pulse falls in the reset period. An erase pulse SEP is applied. As a result, even if the residual wall charges remain after the full-surface write discharge, the residual wall charges on the address electrodes are more completely erased by the combination of the address narrow pulse and the erase pulse SEP that continuously changes the applied voltage value. Can be done in the form.

  According to the thirteenth embodiment, it is possible to more completely erase the opposite side charge by the full-surface writing / self-erasing pulse in the reset period, and the drive voltage margin is improved. Further, the present invention is not limited to the high contrast driving method shown in FIG.

  FIG. 22 is a drive waveform arrangement diagram in the fourteenth embodiment, and shows an example in which the total number of subfields is four. FIG. 22A shows the case where the arrangement order of each period in one subfield is reset, address, and sustain discharge, and FIG. 22B shows the arrangement order of each period in one subfield, which is address, sustain discharge, FIG. 22C shows a case where the arrangement order of each period in one subfield is reset (including a full write pulse), address, sustain discharge, and reset (not including a full write pulse). .

  In this embodiment, in the high-contrast driving method, a reset period in which the full-surface writing / self-erasing pulse is applied after the shortest sustain discharge period or after the longest sustain discharge period is arranged.

  For example, in the case where a reset period for applying a full write / self-erase pulse is arranged after the shortest sustain discharge period, the reset period 24 of the subfield (SF) 2 in FIG. 22A and SF1 in FIG. 22B. The reset period 25 of FIG. 22 and the reset period 27 at the end of SF1 in FIG.

  If the number of subfields for full-surface write discharge is reduced, residual wall charges that cannot be completely reset are accumulated on the counter electrode, and the burden on the few full-surface write discharges increases. It accumulates in. Therefore, in order to reduce the burden on full-surface write discharge, it is better that the sustain discharge period of the subfield immediately before is shorter.

  On the other hand, when the reset period for applying the full write / self-erase pulse is arranged after the longest sustain discharge period, the reset period 23 of SF1 in FIG. 22A, the reset period 26 of SF4 in FIG. 22B, In FIG. 22C, the reset period 28 is located at the end of SF4.

  If the number of subfields for full-surface write discharge is reduced, residual wall charges that cannot be completely reset are accumulated on the counter electrode, and the burden on the few full-surface write discharges increases. It accumulates in. Therefore, in order to increase the effect of the full-surface write discharge, it is better that the sustain discharge period of the immediately preceding subfield is longer.

  As described above, according to the fourteenth embodiment, the influence of the residual wall charge accumulated on the counter electrode during the sustain discharge period can be minimized, and the next erasing operation can be performed in a more complete form. Is improved.

  FIG. 23 is a drive waveform diagram showing the fifteenth embodiment, in which the present embodiment is applied to a high contrast driving method. In the subfield A, as shown in the eighth embodiment of FIG. 16, a pulse having an erasing function is applied immediately before the subfield in which the full write discharge is performed.

  In this embodiment, a pause period in which no drive waveform is output is defined as a self-erase period after application of a full write pulse, and a pause period is provided in the subfield A in which both full write discharge and erase discharge are performed. This is because the wall charge amount that must be reset is most stable and the erasure discharge is ensured by providing the pause period as described above.

  As described above, according to the fifteenth embodiment, the fluctuation of the wall charge amount due to the fluctuation of the pause period can be reduced, and the drive voltage margin is improved. In addition, the present invention is not limited to the high contrast driving method shown in FIG.

  Next, FIGS. 24 and 25 are drive waveform diagrams showing the sixteenth and seventeenth embodiments, respectively, showing an example applied to the high contrast driving method. 24 and 25 illustrate a part of the reset period.

  In these embodiments, by using a combination of a plurality of erase pulses in the reset period, the residual wall charges can be erased with a higher probability than when the residual wall charges are erased by one erase discharge.

  In the embodiment of FIG. 24A, in the reset period, the narrow pulse is first applied to the first electrode, and the second erase pulse SEP is applied to continuously change the applied voltage value in the positive direction. This is an example in which a negative SEP is applied third. In the embodiment of FIG. 24B, in the reset period, the narrow pulse is first applied to the first electrode, and the erase pulse SEP that continuously changes the applied voltage value in the positive direction is applied second. This is an example in which an erase pulse applied to the second electrode and applied third in the negative direction is applied to the second electrode.

  In the embodiment of FIG. 25A, a fourth erase pulse is applied to the embodiment shown in FIG. 24A, and the embodiment of FIG. The fourth erase pulse is applied to the embodiment shown in FIG. The fourth erase pulse is a positive SEP applied to the second electrode.

  Here, the erase pulse SEP for continuously changing the applied voltage value in the second positive direction is made longer than the fourth SEP in the positive direction, so that a better effect can be obtained. Has been confirmed experimentally. Therefore, it is desirable that the erase pulse SEP for continuously changing the applied voltage value in the (n + 1) th positive direction is longer than the positive-direction SEP applied in the nth.

  As described above, according to the sixteenth and seventeenth embodiments, by combining a plurality of erase pulses, it is possible to increase the probability of resetting the residual wall charge before performing the address selective discharge, and the drive voltage margin is improved.

  FIG. 26 is a drive waveform diagram showing the eighteenth embodiment and shows an example applied to the high contrast drive method. FIG. 26 illustrates a part of the reset period.

  In these embodiments, by using a combination of a plurality of erase pulses in the reset period, the residual wall charges can be erased with a higher probability than when the residual wall charges are erased by one erase discharge.

  In the present embodiment, in the reset period, the narrow pulse is first applied to the first electrode, and the erase pulse SEP that continuously changes the applied voltage value in the positive direction is applied to the second electrode. In this example, SEP in the third positive direction is applied to the first electrode.

  As described above, according to the eighteenth embodiment, by combining a plurality of erase pulses, it is possible to increase the probability of resetting the residual wall charge before performing the address selective discharge, and the drive voltage margin is improved.

  FIG. 27 is a waveform diagram showing the principles of the nineteenth and twentieth embodiments of the present invention. During the reset period, two SEP reset pulses are successively applied to the Y electrode. The potential of the X electrode which is the discharge counterpart electrode is raised by a predetermined level for the first SEP reset pulse and returned to the original level (for example, 0 V) for the next SEP reset pulse. That is, the maximum potential difference between the X electrode and the Y electrode during the period when the first SEP reset pulse is applied is smaller than the maximum potential difference during the period when the second SEP reset pulse is applied. As a result, after reaching the discharge start voltage Vfc of the cell B, the discharge start voltage V5 at which the discharge actually starts after a predetermined discharge delay time t has elapsed becomes substantially equal to Vfc, and the wall charges can be erased.

  With the first SEP reset pulse, it is difficult to erase the wall charge of cell A. This is because the maximum potential difference (= Vs− (Vfa−Vfb)) between the X electrode and the Y electrode during the period when the first SEP reset pulse is applied is insufficient to reset the cell A. Therefore, in order to erase the wall charge of the cell having such a relatively high discharge start voltage, a second SEP reset pulse is applied, and the potential of the X electrode at this time is returned to the original, Increase the maximum potential difference of the electrodes (maximum Vs). Thereby, the cell A can be reset by the second SEP reset pulse.

  Based on the above principle, the present invention can be implemented in various forms described below.

  FIG. 28 is a drive waveform diagram showing a nineteenth embodiment of the present invention. The hardware configuration of the plasma display panel is as described in the prior art with reference to the drawings. In the nineteenth embodiment, two SEP reset pulses are applied to the electrodes Y1 to YN during the reset period. The two SEP reset pulses have the same waveform. That is, the voltage gradient at the rising edge of the pulse waveform is equal. However, the two SEP reset pulses may have different waveforms. Discharge occurs using the Y1 to YN electrodes as the anode and the X electrode as the cathode, and the wall charges are erased.

  The potential of the X electrode is the priming voltage Vx during the aforementioned address period during the first SEP reset pulse period, and is 0 V during the next SEP reset pulse period. If the priming voltage Vx is used, a new power supply is not required and it is very advantageous in an actual configuration. However, the potential of the X electrode during the first SEP reset pulse period may be a value other than the priming voltage. The maximum potential difference between the X electrode and the Y electrode during the first SEP reset pulse period is Vs−Vx, and the maximum potential difference between the X electrode and the Y electrode during the next SEP reset pulse period is Vs (> Vs−Vx).

  FIG. 29 is a modification of the nineteenth embodiment. In the modification shown in FIG. 29, three SEP reset pulses are applied to the Y1 to YN electrodes, while the potentials of the X electrodes during the first and second SEP reset pulse periods are Vx1 and Vx2, respectively (Vx1> Vx2> 0V). ) It is characterized in that the potential difference (maximum potential difference) between the X electrode and the Y electrode is set large in three stages. With this configuration, all cells can be reset more reliably. In this case, if Vx1 = Vx, only Vx2 needs to be newly generated.

  Next, a twentieth embodiment of the present invention will be described with reference to FIG. In the twentieth embodiment, the wall charges are erased by causing a discharge between the Y electrode and the address electrode (A electrode). That is, discharge is performed using the Y electrode as the anode and the address electrode as the cathode, and the wall charges are erased. As described above, the basic principle is the same as the nineteenth embodiment in that the address electrode is used instead of the X electrode.

  Two SEP reset pulses are applied to the electrodes Y1 to YN during the reset period. The two SEP reset pulses have the same waveform. That is, the voltage gradient at the rising edge of the pulse waveform is equal. However, the two SEP reset pulses may have different waveforms.

  The potential of the address electrode is the address voltage Va during the first SEP reset pulse, and is 0 V during the next SEP reset pulse. If the address voltage Va is used, a new power supply is not required and it is very advantageous in an actual configuration. However, the potential of the address electrode during the first SEP reset pulse period may be a value other than the address voltage Va. The potential difference between the address electrode and the Y electrode during the first SEP reset pulse period is Vs−Va, and the potential difference between the address electrode and the Y electrode during the next SEP reset pulse period is Vs (> Vs−Va).

  Note that the potential of the X electrode during the period in which the SEP reset pulse is continuously applied is set to Vx as in the address period.

  FIG. 31 shows a modification of the twentieth embodiment. In the modification shown in FIG. 31, three SEP reset pulses are applied to the Y1 to YN electrodes, while the potentials of the address electrodes during the first and second SEP reset pulse periods are Va1 and Va2, respectively (Va1> Va2> 0V). ) The potential difference (maximum potential difference) between the address electrode and the Y electrode is set large in three stages. With this configuration, all cells can be reset more reliably. In this case, if Va1 = Va, the voltage to be newly generated may be only Va2.

  FIG. 32 is a block diagram showing a plasma display driving apparatus of the present invention. This driving device drives the above-described three-electrode / surface discharge / AC type plasma display.

  The address electrode is connected to the address driver 31 for each address line, and the address driver 31 applies an address pulse during address discharge. The Y electrode is also connected to the Y scan driver 34 for each electrode. The Y scan driver 34 is connected to the Y side common driver 33, and pulses at the time of address discharge are generated from the Y scan driver 34, and sustain pulses and the like are generated by the Y side common driver 33, and then the Y scan driver 34 is turned on. Via, it is applied to the Y electrode.

The SEP driver 42 applies a voltage (the aforementioned SEP reset pulse) to the Y electrode through the resistor 43 via the Y scan driver 34. The voltage waveform at this time is determined by the resistance value R of the resistor 43 and the panel capacitance C, and becomes an exponential curve represented by the following equation.
V = e- ^{(t / CR)}
The X electrodes are connected and taken out in common across all display lines of the panel 30. The X electrode common driver 32 generates an address pulse, a sustain pulse, and the like.

  The X common driver 32, Y common driver 33, and Y scan driver 34 are controlled by a control circuit 35. The control circuit 35 is controlled by a synchronization signal (vertical synchronization signal VSYNC, horizontal synchronization signal HSYNC) or a display data signal (DATA) input from the outside of the apparatus.

  The control circuit 35 includes a display data control unit 36 and a panel drive control unit 38. A drive waveform pattern ROM 41 is connected to the control unit 35. The external display data DATA is stored in the frame memory 37 in the display data control unit 36 in synchronization with the external dot clock CLOCK, and then output to the address driver 31 as a control signal. The panel drive control unit 38 includes a scan driver control unit 39 and a common driver control unit 40, and operates according to data in the drive waveform pattern ROM 41 in synchronization with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC. The drive waveform pattern ROM 41 stores data describing the waveform patterns of the address electrode drive waveform, the X electrode drive waveform, and the Y1 to YN electrode drive waveforms as shown in FIGS. The panel drive control unit 38 reads waveform data from the drive waveform pattern ROM 41 in synchronization with the vertical synchronization signal VSYNC and the horizontal synchronization signal HSYNC, and controls the drivers 32, 33, 34 and 42.

  Although each embodiment has been described above, these embodiments can be implemented in any combination.

It is a schematic plan view of 3 electrode, surface discharge, AC type PDP. It is a schematic sectional drawing in the perpendicular direction of 3 electrode, surface discharge, and AC type PDP. It is a schematic sectional drawing in the horizontal direction of 3 electrode, surface discharge, and AC type PDP. It is a wave form diagram which shows the conventional drive method. It is a time chart of a separate address / sustain discharge type / write address system. FIG. 1 is a diagram 1 showing residual wall charges. It is FIG. 2 which shows a residual wall charge. It is a figure which shows the influence by weak discharge. FIG. 3 is a drive waveform diagram illustrating a first embodiment of the present invention. It is a drive waveform diagram which shows the 2nd Example of this invention. It is a drive waveform diagram which shows the 3rd Example of this invention. It is a drive waveform figure which shows the 4th Example of this invention. It is a drive waveform diagram which shows the 5th Example of this invention. It is a drive waveform diagram which shows the 6th Example of this invention. It is a drive waveform diagram which shows the 7th Example of this invention. It is a drive waveform diagram which shows the 8th Example of this invention. It is a drive waveform diagram which shows the 9th Example of this invention. It is a drive waveform diagram which shows the 10th Example of this invention. It is a drive waveform diagram which shows the 11th Example of this invention. It is a drive waveform diagram which shows the 12th Example of this invention. It is a drive waveform diagram which shows the 13th Example of this invention. It is a drive waveform arrangement | positioning figure which shows the 14th Example of this invention. It is a drive waveform diagram which shows the 15th Example of this invention. It is a drive waveform diagram which shows the 16th Example of this invention. It is a drive waveform diagram which shows the 17th Example of this invention. It is a drive waveform diagram which shows the 18th Example of this invention. It is a wave form diagram which shows the principle of the 19th, 20th Example of this invention. It is a drive waveform diagram which shows the 19th Example of this invention. It is a figure which shows the modification of the 19th Example shown in FIG. It is a drive waveform diagram which shows the 20th Example of this invention. It is a figure which shows the modification of the 20th Example shown in FIG. It is a figure which shows one Example of the drive device of the plasma display (PDP) of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 Barrier 12 Cell 13 X electrode 14 Y electrode 15 Address electrode 16 Back glass substrate 17 Phosphor 18 Full glass substrate 19 Sustain electrode 19a Transparent electrode 19b Bus electrode 20 Dielectric layer 21 MgO film 23-28 Reset period 30 Panel 31 Address driver 32 X common driver 33 Y common driver 34 Y scan driver 35 Control circuit 36 Display data control unit 37 Frame memory 38 Panel drive control unit 39 Scan driver control unit 40 Common driver control unit 41 Drive waveform pattern ROM

Claims (7)

A method for driving a plasma display panel, comprising: a first sustain electrode group , a second sustain electrode group, and an address electrode group intersecting with the first sustain electrode group; and displaying a frame image using a plurality of subfields.
At least one subfield includes an address period for selecting cells to be lit in a plurality of display lines, a plurality of display line cells selected in the address period after the address period, and the first sustain electrode group and the A sustain discharge period for generating discharge by repeatedly applying a sustain discharge pulse to each of the second sustain electrode groups,
In the sustain discharge period, the address electrode group pulse is applied to the pulse applied to the last respective first sustain electrode group and the second sustain electrode group overlaps a portion of time to each other As a result, an erasing pulse is generated, and the trailing edge of the last pulse among the pulses applied to the first sustaining electrode group and the second sustaining electrode group and the falling edge of the pulse applied to the address electrode are A driving method of a plasma display panel, characterized by being synchronized .   The pulse applied last to each of the first sustain electrode group and the second sustain electrode group in the sustain discharge period has a pulse width larger than the sustain discharge pulse repeatedly applied. A method for driving a plasma display panel according to claim 1.   In the sustain discharge period, the last pulse applied to each of the first sustain electrode group and the second sustain electrode group overlaps with each other in time so that the pulse width of the repeatedly applied sustain discharge pulse is increased. 3. The plasma display panel drive according to claim 1, wherein a potential difference is generated between the first sustain electrode group and the second sustain electrode group as a narrow pulse having a smaller pulse width. Method.   4. The method of claim 3, wherein the narrow pulse has a pulse width of 2 [mu] sec or less.   5. The driving of a plasma display panel according to claim 1, wherein the last pulse applied in the sustain discharge period is a pulse having the same voltage value as the sustain discharge pulse repeatedly applied. Method. A driving method of a plasma display panel for displaying a frame of video using a plurality of subfields,
At least one subfield has an address period for selecting cells arranged in a plurality of lines using the address electrode and the first sustain electrode, and sustain discharge pulses alternately on the first sustain electrode and the second sustain electrode, respectively. A sustain discharge period for generating a discharge in a selected cell by applying to
After applying the sustain discharge pulse, a first pulse having the same voltage value as the sustain discharge pulse and a large pulse width is applied to the first sustain electrode, and the sustain discharge pulse is applied to the second sustain electrode. A second pulse having the same voltage value and a large pulse width is applied, and the second pulse rises and falls after the first pulse rises and falls. An erasing pulse for erasing charges generated by the sustain discharge is generated by the fall of the first pulse, and the fall of the second pulse is the rise of the pulse applied to the address electrode during the sustain discharge period. A method for driving a plasma display panel, wherein the method is synchronized with a downlink . The method according to claim 6 , wherein the first pulse and the second pulse generate a narrow pulse between the first sustain electrode and the second sustain electrode. .

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