KR100285623B1 - Driving Method of Plasma Display Panel - Google Patents

Abstract

The present invention relates to a method and an apparatus for driving a plasma display panel which can improve contrast by minimizing the amount of light emitted in a subfield reset section.

The PDP driving method of the present invention is characterized in that reset pulses for reset discharge are supplied differently in every subfield.

According to the present invention, the number of reset pulses is reduced in the reset period of the subfield, and the size and width of the reset pulse are controlled and supplied differently for each subfield, thereby suppressing light emission in the non-emission display period, thereby improving contrast. Can be.

Description

Method and Driving Plasma Display Panel and Apparatus

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display apparatus, and more particularly, to a method and apparatus for driving a plasma display panel capable of improving contrast by minimizing light emission in a subfield reset section.

Plasma Display Panel (hereinafter referred to as PDP), which is one of the flat panel displays, is a display device that displays an image by using a gas discharge phenomenon, and is another flat panel display device such as a liquid crystal display (LCD). ) And large area that EL (Electro Luminescence) display module does not have. In general, the PDP obtains a discharge through voltage control applied between the vertical and horizontal electrodes of a cell constituting the pixel, and the amount of light discharged is controlled by changing the length of the discharge time in the cell. In other words, the PDP includes a write pulse for inputting a digital image signal to the vertical and horizontal electrodes of each cell, a scan pulse for scanning, a sustain pulse for maintaining a discharge, and a discharge. By applying an erase pulse for stopping the discharge of the cells, the cells are driven in a matrix form. Here, the step brightness required for image display, that is, gray scale, is expressed by implementing different lengths of time for discharging individual cells within a time (16.67 ms) when a screen of one frame is displayed. Contrast, which represents the difference in contrast, is determined by the brightness and brightness of the background, such as lighting. In order to increase this contrast, not only the background needs to be darkened, but also the brightness needs to be increased.

Such PDPs are generally classified into AC and DC types according to driving methods. Among the AC PDP driving methods, ADS (Addressing Display Separated) driving method divides one frame into a plurality of subfields according to the gradation to be implemented, and each subfield is divided into a reset period, a scan period, and a sustain period. It is driven separately.

Referring to FIG. 1, a method of implementing grayscales of one frame using the ADS method is illustrated. Specifically, FIG. 1 illustrates a case where one frame having a time of 16.67 ms is configured with eight subfields to implement 256 gray scale images. For this purpose, the sustain period in which the relative value of the luminance is determined in each subfield to which the reset and the address period are all allocated equally is 2 ⁸ , 2 ⁷ ,.. , 2 ¹ , 2 ⁰ It is allocated at the ratio of. The gradation of one frame is realized by the combination of the luminance determined in each sustain period of each subfield.

In the PDP driving method, voltage pulses for reset discharge, sustain discharge, erase discharge, and the like are supplied to each subfield in the reset section for stable operation of the cell. However, each cell of the PDP emits light in the black display section due to the discharge in the reset section, resulting in an increase in the brightness of the black level, resulting in a decrease in contrast. Hereinafter, with reference to the accompanying drawings will be described in detail the factors causing the above-described problem in the conventional PDP driving method.

2 shows the magnitude of the light emission waveform generated in the reset and address sections of each subfield. One frame shown in FIG. 2 includes eight subfields for 256 gradation display. Here, it can be seen that light emission waveforms having the same size are generated for each reset period of each subfield constituting one frame. This means that the light of the same size is emitted in the reset section as in the other cells even when the corresponding cell is in the black display period. This causes a problem that the brightness of the black level is increased.

Referring to FIG. 3, a driving waveform for one subfield of a PDP driven by an ADS method is shown. One subfield of FIG. 3 includes a reset period, an address period, and a sustain period.

In FIG. 3, (A) shows a voltage waveform supplied to an address electrode arranged in the vertical direction on the lower substrate of the PDP, and (B) shows sustain and scan electrodes arranged in the horizontal direction on the upper substrate of the PDP (hereinafter, The voltage waveform supplied to the Y sustain electrode), and (C) the voltage waveform supplied to the sustain electrode (hereinafter referred to as Z sustain electrode) arranged side by side with the Y sustain electrode. First, in each subfield, the reset period is a period for slightly remaining wall charges in the entire cell for stable operation of the cell. To this end, a relatively high front writing voltage (Vs + Vw) pulse is applied between the Y and Z sustain electrodes to form wall charges in the dielectric layer inside the cell. Once erased, most wall charges are neutralized. Subsequently, a plurality of discharges are generated by applying a sustain voltage (Vs), an erase voltage (Vs) pulse, or the like between the Y and Z sustain electrodes, so that uniform wall charge remains in the cell. The address section in each subfield is a section for accumulating wall charges such that the next sustain discharge is possible for the pixels to be lit in accordance with the address discharge. For this purpose, wall charges are formed inside the cell to be lit by causing address discharge by the image data pulse applied to the address electrode of the PDP and the scan pulse applied to the Y sustain electrode. At this time, the address driving voltage Va is relatively low due to the wall charge remaining inside the cell in the reset period. In each subfield, a sustain period is a section for generating sustain discharge only for a cell in which an address discharge occurs by raising a sustain pulse under the wall charge. To this end, a sustain voltage (Vs) pulse applied between the Y and Z sustain electrodes of the PDP is added to the wall charges formed inside the lit cell in the address period to generate a sustain discharge to determine the relative value of luminance.

Here, the multiple discharges generated in the reset section play a very important role because they are to maintain uniform wall charges inside all cells for the next stable operation. To this end, in each subfield, in the reset section, discharges such as front writing discharge, sustain discharge, and erase discharge are generated three to four times. By the way, the discharge which occurs in this reset period is larger in magnitude than the normal sustain discharge in the sustain period. In other words, the brightness due to three discharges in the reset period corresponds to about five times of the sustain discharge. This also occurs in the black display section, causing the brightness of the black level (that is, the minimum luminance value) to increase. As a result, there is a problem in that contrast, that is, the contrast, which means the ratio between the maximum luminance value and the minimum luminance value, is lowered.

For example, assuming that the number of discharges included in one frame is 1020, the luminance value due to three to four discharges in the reset period in one subfield is about 0.6 to 0.7 cd / m ² , and in one frame Eight times this, that is, about 5 to 6 cd / m ² , which is the brightness in the non-light-emitting region (ie, the minimum luminance). In this case, the maximum luminance value in the light emitting region is usually about 300 cd / m ^2, so that the contrast ratio of the PDP is very low to 50 to 60: 1. For reference, the contrast ratio in the dark is 26: 1. In addition, in bright places, surface reflection is added, so the contrast of the PDP is further lowered.

As a result, according to the conventional PDP driving method, the brightness of the black level is increased due to the multiple discharges generated in the reset section of each subfield, resulting in a problem of lowering the contrast. In this case, it becomes meaningless to implement high gradation display.

Accordingly, an object of the present invention is to provide a PDP driving method and apparatus capable of suppressing light emission in a non-light emitting period by changing the reset discharge pulse in every subfield.

Another object of the present invention is to provide a method and apparatus for driving a PDP capable of increasing contrast by suppressing light emission in a non-light emitting period.

It is still another object of the present invention to provide a PDP driving method and apparatus capable of relatively reducing the address driving voltage by remaining wall charges in a reset section.

1 is a diagram showing the configuration of one frame of the ADS method.

Fig. 2 is a diagram showing light emission waveforms in a non-light emitting area for one frame by the conventional PDP driving method.

3 is a diagram showing waveforms supplied to respective electrodes of a PDP by a conventional driving method.

4 is a waveform diagram illustrating a PDP driving method according to the first embodiment of the present invention.

5 is a waveform diagram illustrating a reset pulse supplied to a reset section of FIG. 4.

Fig. 6 is a diagram showing light emitting waveforms in a non-light emitting area during one frame by the PDP driving method of the present invention.

7 is a waveform diagram showing a reset pulse applied to the PDP driving method according to the second embodiment of the present invention.

8 is a view showing the voltage magnitude and waveform form of the reset pulse applied to the PDP driving method according to the present invention.

9 is a block diagram showing a PDP driving apparatus according to the present invention.

<Brief description of symbols for the main parts of the drawings>

10: timing controller 12: Y sustain drive unit

14: Z sustain drive unit 16: Y back pressure pulse drive unit

18: Z back pressure pulse drive unit 20: PDP

In order to achieve the above object, the PDP driving method according to the present invention is characterized in that the reset pulse for the reset discharge is supplied differently to every subfield.

In addition, the PDP driving apparatus according to the present invention includes timing control means for generating first and second sustain control signals in response to vertical and horizontal synchronization signals from an input line, and according to the first sustain control signal from the timing control means. First sustain driving means for supplying a drive signal to the first sustain electrode lines, second sustain driving means for supplying a drive signal according to the second sustain control signal from the timing control means to the second sustain electrode lines; A first back pressure pulse driving means for supplying a back pressure pulse synchronized with a reset pulse of each subfield included in the drive signal to the first sustain driving means in response to a drive signal from the first sustain driving means, and a second sustain driving means; In response to the drive signal from the second source, a back pressure pulse synchronized with the reset pulse of each subfield included in the drive signal; First supplying to retain the drive means is characterized in that it comprises a second back-pressure pulse driving means.

Other objects and advantages of the present invention in addition to the above object will become apparent from the description of the preferred embodiment of the present invention with reference to the accompanying drawings.

First, the PDP driving method according to the present invention suppresses light emission in the reset and address periods, that is, non-light emission periods, by varying the wall charge distribution formed inside the cell by supplying different sizes of the reset discharge pulses for each subfield. . In this case, the driving voltage in the address section depending on the wall charges formed in each reset section can be reduced.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to FIGS. 4 to 9.

4 shows a waveform diagram showing a PDP driving method according to the first embodiment of the present invention, which shows a waveform diagram supplied during one subfield.

In FIG. 4, (A) shows the voltage waveform supplied to the address electrode of the PDP, (B) shows the voltage waveform supplied to the Y sustain electrode, and (C) shows the voltage waveform supplied to the Z sustain electrode. . First, the normal negative voltage pulse (-Vy) is supplied to the Y sustain electrode in the reset section, and the normal positive voltage pulse (Vs) is supplied to the Z sustain electrode, so that the front lighting discharge is discharged between the Y sustain electrode and the Z sustain electrode. Let (a) happen. At this time, no voltage is supplied to the address electrode. Accordingly, positive ions accumulate on the Y sustain electrode side and electrons accumulate on the Z sustain electrode side, so that wall charges are formed inside each PDP cell. At this time, since the amount of electrons and positive ions becomes the same on the address electrode side and almost neutralizes, wall charges do not accumulate. This is because the voltage between the address electrode and the Y sustain electrode and the voltage between the address electrode and the Z sustain electrode have absolute values and are opposite in polarity, so that the attraction of the electrostatic charge and the negative charge of the address electrode are equal so that the wall charge is neutralized in the address electrode. . Subsequently, the first self-erasing discharge b occurs by the wall charges accumulated on the Y sustain electrode and the Z sustain electrode side, so that most of the wall charges are erased and the inside of the cell is in a neutral state. This self-erasing discharge is possible because the voltage Vwall between the wall charges formed inside the cell is larger than the threshold voltage Vfire which can be discharged. Subsequently, the second self-erasing discharge (c) occurs due to the wall charge remaining inside the cell during the period where no voltage is supplied to the Y sustain electrode, the Z sustain electrode, and the address electrode. Will be neutralized. Here, for a cell of an error in which the wall charges are not erased by two self-erasing discharges, a normal positive voltage Vs is applied to the Y sustain electrode and the address electrode to cause the erase discharge. In other words, by applying a positive voltage (Vs) pulse to the Y sustain electrode and the address electrode, the applied voltage (Vs) is added to and discharged from the first and second wall charges that are not erased, thereby erasing the wall charge of the error cell. This prevents excessive lighting. Then, in the address period and the sustain period, the operation shifts to the address discharge and the sustain discharge.

The above-described operation is repeated for each subfield, where the width and magnitude of the voltage pulse for the reset discharge are applied differently to each subfield to improve the contrast and lower the driving voltage.

In detail, in the first subfield SF1 of one frame section illustrated in FIG. 6, a three-fold front lighting pulse is applied to the Y sustain electrode and the Z sustain electrode as shown in FIG. After generating a 3x voltage erase pulse is applied to the Y sustain electrode to cause an erase discharge. A reset discharge is generated by applying a double back pressure front writing pulse and an erase pulse as shown in FIG. 5B to the next second subfield SF2, and in FIG. 5C, in the third subfield SF3. The reset discharge is caused by applying a 1 back pressure pulse as shown in Fig. 1). Double back pressure pulse in the fourth subfield SF4, triple back pressure pulse in the fifth subfield SF5, double back pressure pulse in the sixth subfield SF6, and single back pressure pulse in the seventh subfield SF7. And a double discharge pulse is applied to the eighth subfield SF8 to cause a reset discharge. In other words, 3-2-1-2-3-2-1-2 back pressure pulses are supplied to subfields for one frame, respectively, to cause reset discharge. In this case, the amount of light emitted in the reset section of each subfield is shown in proportion to the back pressure pulse supplied in a significantly reduced state as shown in FIG.

Alternatively, the back pressure sequence of the reset pulses supplied to each subfield may be 1-2-3-1-2-3-1-2 or 1-2-3-2-1-2-3-2, 3 Various combinations are possible, such as -2-1-3-2-1-3-2 and 3-3-3-2-2-2-1-1. In this case, the distribution of the amount of light emitted in the reset section of each subfield also changes in proportion to the back pressure order of the reset pulses.

Here, an error cell may exist in which the number of discharges in the reset period is small so that the excessive wall charges are not erased. In general, however, there are only a few cells in error, and wall charges such that sustain discharge can not be maintained may be left when they are not written by the erase. In addition, the polarity of the wall charge remaining in the faulty cell becomes a polarity that lowers the voltage between the address electrode and the Y sustain electrode in the address section, so that discharge in a cell that is not lit is not only prevented, but also excessive lighting is prevented in the lit cell. Will be.

FIG. 7 illustrates reset pulses supplied to Y and Z sustain electrodes as applied to the PDP driving method according to the second embodiment of the present invention.

In the PDP driving method shown in Fig. 7, only the front recording pulses of different sizes are applied to the reset section of each subfield to generate a reset discharge. In this case, when a reset discharge is generated for each subfield, a reset pulse is supplied differently according to the state of the previous subfield. This is because if the wall charges are formed in the previous subfield, the previous wall charge state can be used so that there is no problem in the operation characteristics even if a small reset discharge occurs in the next subfield. In detail, when less wall charges are formed in the previous subfield, more wall charges are formed in the next subfield by supplying a larger reset pulse than the previous one, and when more wall charges are accumulated in the previous subfield, less reset pulses than before. By supplying the wall charge to form the wall charge to prevent excessive wall charges are formed, it is possible to lower the driving voltage. In this case, it is preferable that the back pressure sequence of the reset pulses supplied to the reset section of each subfield is 3-2-1-2-3-2-1-2. In addition, if the shape of the pulse or the width of the pulse is adjusted in the above manner, the effect becomes even better.

Referring to FIG. 8, three types of voltage magnitudes and waveforms of the reset pulses supplied to the Y and Z sustain electrodes are illustrated. FIG. 8A shows a case where pulses of 1, 2, and 3 times are independently applied in the reset section of every subfield as in the reset pulses shown in FIGS. 5 and 7. (B) shows a case where the voltage of the back pressure pulse is applied in a stepwise manner while the voltage of the previous stage is maintained. In this case, the rising time of relatively high energy consumption is reduced by rising to the voltage of the next back pressure pulse while the voltage pulse of the previous stage is maintained. Accordingly, there is an effect that can reduce the power consumption. (C) shows a case where the voltage of the back pressure pulse is raised and lowered step by step. In addition, the rising and falling time of the voltage pulse is reduced, thereby reducing the power consumption.

FIG. 9 is a block diagram showing a PDP driving apparatus according to the present invention. The PDP driving apparatus shown in FIG. 9 is a Y sustain according to a horizontal synchronizing signal and a vertical synchronizing signal input together with an image signal through an input line 11. The timing controller 10 for supplying control signals to the driver 12 and the Z sustain driver 14, and the Y and Z sustain electrode lines of the PDP 20 according to the control signals of the timing controller 10 (not shown). The Y sustain driver 12 and the Z sustain driver 14 for applying voltage pulses to each of them, and the Y back pressure pulse driver 16 and Z back pressure pulses for applying the back pressure pulses to the Y and Z sustain drivers 12 and 14, respectively. The drive part 18 is provided.

In the PDP driving apparatus shown in FIG. 9, the timing controller 10 controls the Y and Z sustain drivers 12 and 14 according to the horizontal synchronizing signal and the vertical synchronizing signal inputted together with the image signal through the input line 11. Input the signal. The Y sustain driver 12 applies a drive signal to the Y sustain electrode lines arranged in the PDP 20 and the Y back pressure pulse driver 16 according to a control signal input from the timing controller 10. The Y back pressure pulse driver 16 applies the back pressure pulse synchronized with the reset pulse to the Y sustain driver 12 differently in every subfield in response to the drive signal from the Y sustain driver 12. Accordingly, the Y sustain driver 12 synchronizes with the reset pulses of every subfield, and adds back pressure pulses applied from the Y back pressure pulse driver 16 to supply the Y sustain electrode lines of the PDP 20. At this time, the reset pulses supplied to the Y sustain electrode lines are as shown in FIGS. 5 and 7. Similarly, the Z sustain driver 14 applies a drive signal to the Z sustain electrode lines arranged in the PDP 20 and the Z back pressure pulse driver 18 according to a control signal input from the timing controller 10. The Z back pressure pulse driver 18 applies the back pressure pulse synchronized with the reset pulse to the Z sustain driver 14 differently in every subfield in response to the drive signal from the Z sustain driver 14. Accordingly, the Z sustain driver 12 adds back pressure pulses applied from the Y back pressure pulse driver 16 in synchronization with the reset pulses of every subfield to supply the Y sustain electrode lines of the PDP 20. At this time, the reset pulses supplied to the Z sustain electrode lines are as shown in FIGS. 5 and 7.

As a result, in the PDP driving method of the present invention, unlike the conventional supply of a reset pulse, the width of the reset pulse and the magnitude of the voltage are supplied in every subfield, thereby minimizing the amount of light emission caused by the reset discharge. Will be improved.

As described above, according to the PDP driving method and apparatus according to the present invention, the number of reset pulses is reduced in the reset period of the subfield and the size and width of the reset pulses are controlled and supplied differently for each subfield so as not to display the light emission period. It is possible to improve the contrast by suppressing light emission from the light. In addition, by supplying a reset pulse in consideration of the wall charge generated in the previous field, the cell can be stably operated and can be driven at a low voltage in the address period.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (7)

A reset period for initializing all the cells and remaining the wall charges by a predetermined amount in the plasma display panel in which the first and second sustain electrode lines and the cells generating gas discharge using the address electrode lines are arranged in a matrix; A method for driving in units of frames comprising a plurality of subfields comprising an address period for selecting a cell to be lit and a discharge sustain period for determining the brightness of a lit cell, And resetting discharge is generated by supplying different types of reset pulses to all the cells in consideration of the wall charge magnitude of the previous subfield for each reset period of the subfield. The method of claim 1, And a voltage level of the reset pulses is different from each other. The method of claim 1, And a width and a voltage size of the reset pulse are different from each other. The method of claim 1, And any one of a basic voltage pulse, a double pressure pulse and a triple pressure pulse with respect to the basic voltage pulse is selectively supplied as the reset pulse. The method of claim 1, When the wall charge formed in the reset period of the previous subfield is large, a relatively small reset pulse is supplied, And a relatively large reset pulse is supplied when the wall charges formed during the reset period of the previous subfield are small. The method of claim 1, The reset pulse is a front lighting pulse for causing front lighting discharge to form wall charge in all the cells, And the wall charge is formed such that self-discharge discharge is generated at least once by the wall charge. The method of claim 6, And the reset pulse further comprises an erase pulse for causing an erase discharge to erase the wall charge.