JP4240160B2 - AC type PDP driving method and plasma display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving method for an AC type PDP (Plasma Display Panel).
[0002]
A PDP is a thin display device capable of high-speed display, and has come to be widely used for applications such as television images and computer monitors when a color screen is put into practical use. It is also attracting attention as a means of realizing a large screen for high vision. One of the problems of such PDP is improvement of luminance.
[0003]
[Prior art]
The AC type PDP is a PDP having a structure in which a main electrode is covered with a dielectric in order to maintain a lighting state using wall charges. At the time of display, line sequential addressing (setting of lighting / non-lighting) that forms a state in which only the cells to be lit (emitted) are charged is performed, and thereafter, the lighting sustaining voltage of alternating polarity is simultaneously applied to all the cells. Vs is applied. The lighting sustaining voltage Vs satisfies the formula (1).
[0004]
Vf−Vwall <Vs <Vf (1)
Vf: discharge start voltage
Vwall: Wall voltage
In a cell in which wall charges exist, the wall voltage Vwall is superimposed on the lighting sustaining voltage Vs, so that the effective voltage (also referred to as cell voltage) Veff applied to the cell exceeds the discharge start voltage Vf and discharge (sustain discharge) occurs. If the application period of the lighting sustaining voltage Vs is shortened, an apparently continuous lighting state can be obtained. The brightness of the display depends on the number of discharges per unit time. Therefore, the halftone is reproduced by appropriately setting the number of discharges of one field (one frame in the case of non-interlace) for each cell according to the gradation level.
[0005]
As a PDP gradation display method, one field is composed of a plurality of subfields weighted with luminance (that is, the number of discharges), and the total number of discharges for one field is set according to the combination of the presence or absence of lighting in units of subfields. Is widely known (Japanese Patent Laid-Open No. 4-195188). In general, a weight of 2 for each subfield ⁿ A so-called “binary weighting” represented by (n = 0, 1, 2, 3...) Is performed. For example, if the number of subfields is 8, it is possible to display 256 gradations with gradation levels of “0” to “255”.
[0006]
Color display is a kind of gradation display. That is, the display color is determined by the combination of the luminances of the three colors R (red), G (green), and B (blue). In the PDP, phosphor layers of each color of R, G, and B are provided for each cell, and a set of cells of each color of R, G, and B corresponds to one pixel. If the luminance of each cell is 256 gradations, the number of display colors is 256. ^Three It is.
[0007]
In the conventional driving method, the sustain discharge is generated the same number of times in each color cell of R, G, B corresponding to one pixel in each subfield. In other words, a predetermined number of lighting sustain voltages are applied uniformly to the cells of each of the R, G, and B emission colors.
[0008]
[Problems to be solved by the invention]
Conventionally, in order to ensure the color balance (white reproducibility) of pixels, it is necessary to optimize the R, G, B emission luminance ratio in one sustain discharge. Therefore, the selection of the phosphor material is limited, and it is difficult to improve the luminance. This is because the brightness must be increased uniformly for the three colors. It is also necessary to align emission characteristics such as afterglow so that the luminance changes in proportion to the number of discharges.
[0009]
An object of the present invention is to increase the degree of freedom in selecting a phosphor material and facilitate the improvement of luminance and color purity.
[0010]
[Means for Solving the Problems]
In the present invention, the number of discharges is individually set for each of the three colors for color display, and the color balance is ensured by adjusting the integrated emission intensity ratio of the three colors. That is, the number of discharges of the low-luminance color is made larger than that of the high-luminance color. Even if there is a luminance difference depending on the phosphor material among the three colors in one discharge, the difference in luminance can be compensated by optimizing the number of discharges of each color in subfield units or field units. it can.
[0011]
When one field is composed of a plurality of subfields having different luminance weights and color display is performed by assigning a sustain period to each subfield, the ratio of the number of discharges of three colors is basically constant for all subfields. It is a form. However, if there is no significant problem in color reproduction, the ratio of the number of discharges of the three colors may be different for each subfield. For example, the number of discharges of three colors may be made equal for subfields with a small weight (small number of discharges), and the number of discharges of three colors may be varied so as to maintain color balance for a subfield with a large weight.
[0012]
The method of the invention of claim 1 includes first and second electrodes that define rows of a matrix display, a third electrode that defines columns, and three kinds of phosphor layers having different emission colors, A driving method of an AC type PDP having a surface discharge structure for color display in which light emission colors of cells adjacent in a column direction are the same, wherein the first and second electrodes By alternately applying a sustain pulse to All three cells at once Sustain pulse During the sustain period when the same number of times is applied, Sustain pulse And the second electrode is interrupted And applying a charge erasing pulse having a polarity opposite to that of the sustain pulse and a small amplitude, The third electrode in a row selected by emission color The second electrode and the third electrode are applied by applying a voltage having the same polarity and a small voltage value as the sustain pulse. Reapply after interruption between Sustain pulse so Light up A discharge is generated to erase the charge so that no sustain discharge occurs. Let Then Sustain pulse Is applied, and the number of times of sustaining discharge in at least the first light emitting color cell in the sustain period is made smaller than that in the other light emitting color cells.
[0013]
In the driving method according to the second aspect of the present invention, the polarity that contributes to the discharge for the charge erasure in the vicinity of the third electrode of the selected column in the sustaining discharge before the discharge for the charge erasure is generated. To be charged.
[0014]
According to the driving method of the invention of claim 3, one field is composed of a plurality of subfields having different luminance weights, and when color display is performed by assigning a sustain period for each subfield, the luminance weights are selected in descending order. In the sustain period of the above subfield, discharge for the charge erasure is generated.
[0015]
The field in the present invention is a unit image for time-series image display. That is, in the case of television, it means each field of an interlace format frame, and in the case of a non-interlace format typified by computer output (which can be regarded as a one-to-one interlace format), it means the frame itself.
[0016]
According to a fourth aspect of the present invention, there is provided a plasma display device comprising first and second electrodes for defining a matrix display row, a third electrode for defining a column, and three kinds of phosphor layers having different emission colors. 4. An AC type PDP having a surface discharge structure for color display in which the light emission colors of cells adjacent in the column direction are the same, and the driving method of the AC type PDP according to any one of claims 1 to 3. And a drive circuit that applies the applied sequence of voltage to the PDP.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a configuration diagram of a plasma display device 100 according to the present invention.
The plasma display device 100 includes an AC-type PDP 1 that is a matrix-type color display device, and a drive unit 80 for selectively lighting a large number of cells C constituting a screen (screen) SC. Used as a wall-mounted television receiver and computer system monitor.
[0018]
In the PDP 1, sustain electrodes X and Y as a pair of first and second main electrodes are arranged in parallel, and in each cell C, the sustain electrodes X and Y intersect with an address electrode A as a third electrode 3. This is a PDP having an electrode surface discharge structure. The sustain electrodes X and Y extend in the row direction (horizontal direction) of the screen, and one of the sustain electrodes Y is used as a scan electrode for selecting cells in units of rows at the time of addressing. The address electrode A extends in the column direction (vertical direction) and is used as a data electrode for selecting cells in units of columns. A region where the sustain electrode group and the address electrode group intersect is a display region, that is, a screen SC.
[0019]
The drive unit 80 includes a controller 81, a frame memory 82, a data processing circuit 83, a subfield memory 84, a power supply circuit 85, an X driver 87, a Y driver 88, and an address driver 89. The drive unit 80 receives field data Df in units of pixels indicating luminance levels (gradation levels) of R, G, and B colors from various external devices such as a TV tuner and a computer together with various synchronization signals.
[0020]
The field data Df is temporarily stored in the frame memory 82 and then sent to the data processing circuit 83. The data processing circuit 83 is data conversion means for setting a combination of subfields to be lit, and outputs subfield data Dsf corresponding to the field data Df. The subfield data Dsf is stored in the subfield memory 84. The value of each bit of the subfield data Dsf is information indicating whether or not the cells need to be lit in the subfield.
[0021]
The X driver circuit 87 applies a drive voltage to the sustain electrode X, and the Y driver circuit 88 applies a drive voltage to the sustain electrode Y. The address driver circuit 89 applies a drive voltage to the address electrode A in accordance with an address control signal S89 from the controller 81. Predetermined power is supplied from the power supply circuit 85 to these driver circuits.
[0022]
FIG. 2 is a perspective view showing the internal structure of the PDP 1.
In the PDP 1, a pair of sustain electrodes X and Y are arranged for each row L on the inner surface of the front glass substrate 11. Row L is a cell column in the horizontal direction on the screen. Each of the sustain electrodes X and Y includes a transparent conductive film 41 and a metal film (bus conductor) 42, and is covered with a dielectric layer 17 made of low-melting glass and having a thickness of about 30 μm. A protective film 18 made of magnesia (MgO) and having a thickness of several thousand angstroms is provided on the surface of the dielectric layer 17. The address electrodes A are arranged on a base layer 22 covering the inner surface of the glass substrate 21 on the back side, and are covered with a dielectric layer 24 having a thickness of about 10 μm. On the dielectric layer 24, one partition wall 29 having a height of 150 μm in a straight line in plan view is provided between the address electrodes A. These partition walls 29 divide the discharge space 30 into sub-pixels (unit light-emitting regions) in the row direction, and the gap size of the discharge space 30 is defined. Then, phosphor layers 28R, 28G, and 28B of three colors R, G, and B for color display are provided so as to cover the inner surface on the back side including the upper side of the address electrode A and the side surface of the partition wall 29. ing. The three-color arrangement pattern is a stripe pattern in which the light emission colors of cells in one column are the same and the light emission colors of adjacent columns are different. According to this stripe pattern, the phosphor layers 28R, 28G, and 28B can be efficiently formed using screen printing in which the phosphor paste is dropped into the arrangement gaps of the partition walls 29.
[0023]
The discharge space 30 is filled with a discharge gas in which xenon is mixed with neon as a main component (filling pressure is 500 Torr), and the phosphor layers 28R, 28G, and 28B are locally excited by ultraviolet rays emitted by xenon during discharge. Emits light. One pixel (pixel) for display is composed of three sub-pixels arranged in the row direction. A structure in each sub-pixel is a cell (display element). Since the arrangement pattern of the barrier ribs 29 is a stripe pattern, the portion corresponding to each column in the discharge space 30 extends across all rows L in the column direction. Therefore, the dimension of the electrode gap between adjacent rows L (referred to as reverse slits) is sufficiently larger than the surface discharge gap of each row L (for example, a value in the range of 80 to 140 μm), and the discharge coupling in the column direction is reduced. A value that can be prevented (for example, a value in the range of 400 to 500 μm) is selected.
[0024]
FIG. 3 is a configuration diagram of the address driver 89.
The address driver 89 includes a shift register 891 and a tristate circuit 892. The shift register 891 stores, in addressing, subfield data Dsf- (R), Dsf- (G), Dsf- (for each color of R, G, B for one row from the subfield memory 84 for each scanning of one row. B) is entered. At this time, the sub-field data Dsf for each color in a predetermined order (B, G, R... In the figure) by one cell so that the data is arranged in the row direction in the order corresponding to the arrangement of the phosphor layers 28R, 28G, 28B. -(R), Dsf- (G), Dsf- (B) are read from the subfield memory 84. In a sustain period described later, G and R erase data DDG and DDR according to the present invention are transferred from the subfield memory 84 to the shift register 891. The erasure data DDG is data for generating an erasure discharge in a cell having an emission color G, and the erasure data DDR is data for generating an erasure discharge in a cell having an emission color R. Since the erase data DDG and DDR are fixed data that does not depend on the display contents, instead of transferring erase data for one line for each color of G and R, the input terminal voltage of the shift register 891 is synchronized with the shift clock. Alternatively, binary control may be performed.
[0025]
The tri-state circuit 892 receives a 2-bit address control signal S89 from the controller 81. The tristate circuit 892 forcibly sets all the address electrodes A to the ground state when the value of the address control signal S89 is “0”, and forcibly sets all the address electrodes A when the value of the address control signal S89 is “1”. Thus, it is biased to the address potential Va. When the value of the address control signal S89 is “2”, the tristate circuit 892 sets each address electrode A to the ground state or sets the address potential Va according to the data for one row latched by the shift register 891. Bias.
[0026]
Hereinafter, a method for driving the PDP 1 in the plasma display device 1 will be described.
FIG. 4 is a diagram showing a field configuration and an outline of a drive sequence.
For example, in the display of a television image, in order to perform gradation reproduction by binary lighting control, each time-series field f that is an input image as in the past (the subscript of the code indicates the display order). ) Is divided into, for example, eight subframes sf1, sf2, sf3, sf4, sf5, sf6, sf7, and sf8. In other words, each field f constituting the frame F is replaced with a set of eight subframes sf1 to sf8. However, when a non-interlaced image such as a computer output is reproduced, each frame is divided into eight. Then, weighting is performed so that the relative ratio of luminance in these subfields sf1 to sf8 is 1: 2: 4: 8: 16: 32: 64: 128, and the maximum number of times of sustain light emission in each subfield sf1 to sf8 is determined. Set. Since 256 levels of luminance can be set for each color of RGB by the combination of lighting / non-lighting in units of subfields, the number of colors that can be displayed is 256. ^Three It becomes. It is not necessary to display the subfields sf1 to sf8 in the order of the luminance weight. For example, optimization can be performed such that the subfield sf8 having a large weight is arranged in the middle of the display period.
[0027]
The subfield period Tsf assigned to each of the subfields sf1 to sf8 includes a reset period TR for uniformizing the charged state of the entire screen, an address period TA for performing addressing in an erase format (shown format) or a write format, and a gradation level. It consists of a sustain period TS in which the lighting state is maintained in order to ensure the corresponding luminance. In each subfield period Tsf, the length of the reset period TR and the address period TA is constant regardless of the luminance weight, but the length of the sustain period TS is longer as the luminance weight is larger. That is, the lengths of the eight subfield periods Tsf corresponding to one field f are different from each other.
[0028]
In the reset period TR, a first process of applying a positive voltage pulse Pr to the sustain electrode X, a positive voltage pulse Prx to the sustain electrode X, and a negative voltage pulse Pry to the sustain electrode Y are applied. As a result of the second process, wall charges having a predetermined polarity are formed in the “previously lit cell” that was lit in the previous subfield and the “previously unlit cell” that was not lit. In the first process, the address electrode A is biased to a positive potential of about 50 to 120 V to prevent unnecessary discharge between the address electrode A and the sustain electrode X. Subsequent to the second process, a positive voltage pulse Prs is applied to the sustain electrode Y to cause surface discharge in all cells in order to improve the charging uniformity. This surface discharge reverses the charging polarity. Thereafter, the potential of the sustain electrode Y is gradually reduced to a predetermined value in order to avoid the disappearance of charges.
[0029]
In the address period TA, each row is selected in order from the first row, and a negative scan pulse Py is applied to the corresponding sustain electrode Y. Simultaneously with the selection of the row, a positive address pulse Pa is applied to the address electrode A corresponding to the cell that should not be lit (currently non-lighting cell). In the cell to which the address pulse Pa is applied in the selected row, a counter discharge occurs between the sustain electrode Y and the address electrode A, and the wall charge of the dielectric layer 17 disappears. When the address pulse Pa is applied, positive wall charges exist in the vicinity of the sustain electrode X, so that the address pulse Pa is canceled by the wall voltage, and no discharge occurs between the sustain electrode X and the address electrode A. . Such an erasing type addressing is suitable for speeding up because charge re-formation is not required unlike the writing type. The address time per line is about 1.3 μs.
[0030]
In the sustain period TS, all address electrodes A are basically biased to a positive potential in order to prevent unnecessary discharge, and a positive sustain pulse Ps is first applied to all sustain electrodes X. Thereafter, a sustain pulse Ps is alternately applied to the sustain electrode Y and the sustain electrode X. In the present embodiment, the final sustain pulse Ps is applied to the sustain electrode Y. By applying the sustain pulse Ps, a surface discharge is generated in a cell in which wall charges remain (currently lit cell) in the address period TA.
[0031]
FIG. 5 is a waveform diagram showing the driving method of the present invention.
In the present embodiment, the sustain period TS of each of the subfields sf1 to Sf8 includes a three-color light emission period TS3 that causes the R, G, and B cells to emit light, a two-color light emission period TS2 that causes the R and B cells to emit light, and This is divided into a one-color light emission period TS1 in which only the B cell emits light. That is, the number of times of the sustaining discharge of the currently lit cell varies depending on the emission color, B is the largest, R is the second largest, and G is the smallest. The ratio of the number of sustaining discharges of the three colors is based on the light emission characteristics of the phosphor layers 28R, 28G, and 28B so that a good white color can be reproduced when lighting is performed in the eight subfields sf1 to Sf8. Appropriately selected.
[0032]
Thus, in order to make the number of G and R lighting sustain discharges less than B, wall charges are erased for the G and R cells during the sustain period TS. That is, immediately after the end of the three-color light emission period TS3, after the sustain pulse Ps is applied to the sustain electrode Y, the application of the sustain pulse Ps is temporarily stopped, and the negative polarity pulse Pdy (for charge erasing is applied to the sustain electrode Y. The peak value is -20 to -120V). At this time, the address electrode A corresponding to the G cell is kept in a positive bias state (potential is 50 to 120 V), and the other address electrodes A are grounded. As a result, in the G lighted cell this time, a counter discharge occurs between the address electrode A and the sustain electrode Y, and this causes a surface discharge. If the peak value of the pulse Pdy is set to a minimum, the wall charge is not lost by the surface discharge, and the charge is not re-formed, so that the G lighted cell is not charged. On the other hand, in each of the currently lit cells of R and B, the pulse Pdy is canceled by setting the address electrode A to the ground state, and the charged state is maintained as it is. Therefore, when the application of the sustain pulse Ps to all the cells is restarted in the two-color light emission period TS, the G lighted cell is not lit, and the R and B lighted cells are lit.
[0033]
Further, immediately after the end of the two-color light emission period TS2, after the sustain pulse Ps is applied to the sustain electrode Y, the application of the sustain pulse Ps is interrupted again, and the pulse Pdy is applied to the sustain electrode Y. At this time, the address electrode A corresponding to the cell B is brought into the ground state. As a result, a surface discharge occurs in the current lighting cell of R, and the wall charges disappear. In the current lighting cell of B, the charged state is maintained as it is, and only the current lighting cell of B lights up in the subsequent one-color light emission period TS.
[0034]
FIG. 6 is a time chart of a first example of address driver control.
At the start of the sustain period TS, the controller 81 (see FIG. 3) forcibly sets all the address electrodes A to a positive potential by setting the value of the address control signal S89 to “1” in order to prevent unnecessary counter discharge. Bias. Thereafter, when the wall charges are erased (the target here is a G cell), the value of the address control signal S89 is set to “0” after the final sustain pulse Ps falls before the application of the pulse Pdy, and all the address electrodes are set. Force A to ground. Then, when the pulse Pdy is applied to the sustain electrode Y, the value of the address control signal S89 is set to “2”. The erase data DDG is input to the shift register 891 within the period from the end of addressing to this signal switching. The erase data DDG in this case is data for biasing the G address electrode A and setting the R and B address electrodes A to the ground state. After the application of the pulse Pdy, all the address electrodes A are forcibly biased to a positive potential by setting the value of the address control signal S89 to “1” again in accordance with the resumption of the application of the sustain pulse Ps. The G address electrode A may be grounded after the end of the application of the pulse Pdy as indicated by the chain line in the figure, but the control is simpler if all the address electrodes A are forcibly biased. .
[0035]
FIG. 7 is a time chart of a second example of address driver control.
In the example of FIG. 7, when the sustain pulse Ps is applied immediately before the application of the pulse Pdy, the address electrode A corresponding to the color to be erased (here, G) is set to the ground state. That is, appropriate erase data DDG is input to the shift register 891, and the value of the address control signal S89 is switched from “1” to “2” in synchronization with the application of the sustain pulse Ps. Thus, as described later, in the lighting sustain discharge, a positive charge is charged in the vicinity of the G address electrode A, and trigger discharge is likely to occur. After that, as in the example of FIG. 6, all the address electrodes A are once grounded, and only the G address electrode A is biased to generate a discharge for charge erasing. Bias to potential. While all the address electrodes A are in the ground state, the data content of the shift register 891 is replaced with erase data DDG whose value is inverted from the previous erase data DDG.
[0036]
FIG. 8 is a diagram showing a charging model of the driving method of FIG.
In the three-color light emission period 3, by alternately applying the sustain pulse Ps to the sustain electrodes X and Y, a surface discharge H2 is generated in the current lighting cell of each color, and the dielectric layer 17 in the vicinity of the sustain electrodes X and Y previously The wall charge of the opposite polarity is charged.
[0037]
As described above, when the sustain pulse Ps other than the final sustain pulse Ps applied to the sustain electrode Y is applied, all the address electrodes A are biased to the positive potential Va in order to prevent unnecessary discharge. On the other hand, when the final sustain pulse Ps is applied, only the G address electrode A is grounded. As a result, the positive wall charges are charged in the dielectric layer 24 above the address electrodes A in the G lighted cell this time. This wall charge increases the applied voltage when the pulse Pdy is applied, and easily causes the counter discharge H1. Therefore, the peak value of the pulse Pdy can be made lower in order to prevent unnecessary charge re-formation after the wall charge disappears by the surface discharge H2.
[0038]
According to the above embodiment, even when the emission luminances of the G, R, and B phosphor layers are different, a good white color can be reproduced. Therefore, the composition of the phosphor material and the phosphor paste Great freedom of choice. However, the number of discharges of the three colors R, G, and B does not need to be different from each other, and only the number of discharges of one color may be smaller than the other two colors.
[0039]
In the above-described embodiment, if the peak value of the pulse Pdy applied for charge erasing in the sustain period TS is the same as the scan pulse Py applied in the address period TA, the drive circuit configuration is simplified. If the pulse width of the pulse Pdy is longer than that of the scan pulse Py (for example, 3 to 13 μs), the occurrence probability of trigger discharge is increased, and unnecessary charges can be erased more reliably.
[0040]
In the above-described embodiment, in order to reduce the deterioration of the phosphor due to the address discharge, the address pulse Pa is determined to be positive, the polarity of the other pulse is set, and the positive sustain pulse is applied only to one of the sustain electrodes. Although an example in which the drive circuit is simplified by applying the voltage is given, the present invention is not limited to this. That is, the polarity of the applied voltage can be changed. In addition, a writing format may be adopted instead of the erasing format exemplified in the addressing. In the reset period TR, the entire surface is erased, and in the case of performing addressing of the address type in which the wall charge is charged to the lighting cell this time, all the sustain electrodes Y are biased to the negative polarity in the addressing, and only the address electrode A of the scanning target row If the negative scan pulse Py is superimposed on the Y pulse, the peak value of the scan pulse Py can be lowered to reduce the burden on the Y driver 88. In this case, if the peak value of the pulse Pdy applied for charge erasing in the sustain period TS is used as a bias potential at the time of addressing, the circuit configuration is simplified.
[0041]
【The invention's effect】
According to the first to fourth aspects of the invention, the degree of freedom in selecting the phosphor material can be expanded and the luminance and color purity can be easily improved.
[0042]
According to the second aspect of the present invention, the voltage applied for charge erasing during the sustain period can be lowered, and the burden on the drive circuit can be reduced.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a plasma display device according to the present invention.
FIG. 2 is a perspective view showing an internal structure of a PDP.
FIG. 3 is a configuration diagram of an address driver.
FIG. 4 is a diagram showing a field configuration and an outline of a drive sequence.
FIG. 5 is a waveform diagram showing a driving method of the present invention.
FIG. 6 is a time chart of a first example of address driver control.
FIG. 7 is a time chart of a second example of address driver control.
FIG. 8 is a diagram showing a charging model of the driving method of FIG.
[Explanation of symbols]
1 PDP
X Sustain electrode (first electrode)
Y Sustain electrode (second electrode)
A Address electrode (third electrode)
28R phosphor layer
28G phosphor layer
28B phosphor layer
R, G, B emission color
C cell
Vs lighting maintenance voltage
TS Sustain period
H2 surface discharge (lighting sustain discharge)
H1 Counter discharge (discharge for charge erasing)
f field
sf1-8 subfield
80 Drive unit (drive circuit)
100 Plasma display device.

Claims (4)

Light emission between cells adjacent to each other in the column direction, having first and second electrodes that define rows of a matrix display, a third electrode that defines columns, and three types of phosphor layers having different emission colors A method for driving an AC type PDP having a surface discharge structure for color display having the same color,
In the middle of the first and simultaneously sustain period for the same number of applied sustain pulses with respect to 3 colors all cells by applying alternating sustain pulses to the second electrode, to interrupt the application of the sustain pulse A charge erasing pulse having a polarity opposite to that of the sustain pulse and having a small amplitude is applied to the second electrode , and the polarity of the sustain pulse is the same as that of the sustain pulse to the third electrode in a column selected for each emission color. when a voltage value applied to small voltage causes a discharge to erase the second electrode and the electric charge so that a sustaining discharge is re-applied sustain pulse after the interruption is not generated between the third electrode is allowed, then resumes the application of the sustain pulse, at least the number of sustaining discharge in the first emission color of the cell other light emission in the sustain period The driving method of the AC type PDP, which comprises less than a cell. 2. The AC type according to claim 1, wherein, in a lighting sustain discharge before the discharge for the charge erasure is generated, the vicinity of the third electrode of the selected column is charged to a polarity that contributes to the discharge for the charge erasure. Driving method of PDP. In the sustain period of one or more subfields selected in descending order of the luminance weight when one field is composed of a plurality of subfields having different luminance weights, and the sustain period is assigned to each subfield to perform color display, The method for driving an AC type PDP according to claim 1, wherein discharge for charge erasing is generated. Light emission between cells adjacent to each other in the column direction, having first and second electrodes that define rows of a matrix display, a third electrode that defines columns, and three types of phosphor layers having different emission colors AC type PDP having a surface discharge structure for color display having the same color;
4. A plasma display device, comprising: a drive circuit that applies a voltage application to the PDP in a sequence to which the driving method of the AC type PDP according to claim 1 is applied.

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