JPH11175025A - Driving method of ac type pdp - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the display of a high-quality moving picture in which a moving pseudo contour is not conspicuous by mitigating the discontinuity of luminous patterns among gradated levels. SOLUTION: In the gradated display drive comprising dividing the pair of subfields sf1 to 8 equivalent to one field (f) into subfield groups sfg1 to 4 smaller than the number 8 of the subfields and performing write addressing and lighting sustenance on every subfield after initializing every subfield group by one time, subfields sf7, sf8 of two or more are made belong to the subfield group sfg4 having the largest luminance and the weight '19' of the luminance at least the final subfield sf8 in subfield groups of one or more including the subfield group having the highest luminance is set smaller than other weight '27' in the subfield group and set to a value larger than the maximum value '9' of weights of subfield groups sfg1 to 3 other than the subfield group.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an AC type PDP (Pl
The present invention relates to a method for driving an asma display panel.

A PDP is a thin self-luminous display device using a substrate pair as a support, and has come to be widely used for applications such as television images and computer monitors with the practical use of color screens. It is also attracting attention as a means for realizing large screens for high-definition television. In order to increase the definition and the screen size of the PDP, it is necessary to reduce the power consumption while ensuring the reliability of the operation.

[0003]

2. Description of the Related Art An AC PDP is a PDP having a structure in which a main electrode is covered with a dielectric material in order to maintain a lighting state using wall charges. At the time of display, line-sequential addressing is performed to form a state in which only cells to be lit (emit light) are charged, and then a lighting sustaining voltage Vs having an alternating polarity is applied to all the cells simultaneously. Lighting maintenance voltage Vs
Satisfies the expression (1).

Vf-Vwall <Vs <Vf (1) Vf: discharge starting voltage Vwall: wall voltage In a cell having wall charges, the wall voltage Vwall is superimposed on the lighting sustaining voltage Vs, so that the effective voltage applied to the cell ( Discharge occurs when Veff exceeds the discharge start voltage Vf. By shortening the application period of the lighting sustaining voltage Vs, an apparently continuous lighting state can be obtained. The brightness of the display depends on the number of discharges per unit time. Therefore, the halftone is reproduced by appropriately setting the number of discharges of one field (one frame in the case of non-interlace) for each cell in accordance with the gradation level. Color display is a type of gradation display, and the display color is determined by the combination of the luminance of the three primary colors.

As a gradation display method of the PDP, one field is composed of a plurality of subfields weighted with luminance (ie, the number of times of discharge), and the total number of times of discharge in one field is determined by a combination of lighting on / off in subfield units. A setting method is widely known (Japanese Patent Laid-Open No. 4-19518).
No. 8). In general, a weight of 2 for each subfield
A so-called “binary weighting” represented by ⁿ (n = 0, 1, 2, 3...) is performed. For example, if the number of subfields is 8, the gradation level is 256 from “0” to “255”.
Display of gradation is possible.

[0006] Binary weighting has no redundancy in the weights and is suitable for multiple gradations. However, in order to make the gradation width (luminance difference for one gradation) uniform over the entire gradation range, addressing must be performed for each subfield. Prior to addressing, a reset process (initialization process) for equalizing the charged state of the entire screen must be performed for each subfield. If the reset process is omitted, the discharge condition is different between the cell in which the wall charges remain (previous lighting cell) and the other cell (previous non-lighting cell), and it is difficult to reliably perform addressing. Since the reset process and the addressing involve discharge, it is desirable that the number of these processes be smaller from the viewpoint of contrast and power consumption. Especially high definition PD
In the case of P, the burden on the circuit components for addressing is large, so that reduction of the number of times of addressing is desired from the viewpoint of measures against heat generation.

Therefore, conventionally, a predetermined number of subfields are divided into a plurality of subfield groups, and the weights of the subfields belonging to each subfield group are made equal.
A driving method for performing a reset process once for each subfield group has been proposed (Japanese Patent No. 2639311).

FIG. 6 is a diagram showing a conventional field configuration. FIG. 6A shows the weights of the subfields in a table format,
FIG. 6B shows the breakdown of the field period. FIG.
In the example of (A), the field f is composed of a total of eight subfields sf1 to sf8, and these subfields sf1 to sf8 are divided into two subfield groups sfg1 to sfg4. Each subfield sf1, sf2 of the first subfield group sfg1
Is 1, the weight of each of the subfields sf3 and sf4 of the second subfield group sfg2 is 3, and each of the subfields sf3 of the third subfield group sfg3 is
The weight of 5, sf6 is 9. The weight of each of the subfields sf7 and sf8 of the fourth subfield group sfg4 is 27. With this field configuration, it is possible to display 81 gradations of gradation levels “0” to “80”.

The display order of the subfield groups sfg1 to sfg4 is not limited to the order of the weights, but can be set arbitrarily. In the example of FIG. 6B, the first subfield group s
fg1 → third subfield group sfg3 → fourth subfield group sfg4 → second subfield group sfg2
Are displayed in this order. The address period TA for performing the write addressing and the sustain period TA for maintaining the lighting state are assigned to each of the subfields sf1 to sf8. The reset period TR for erasing the residual charge as a pre-process of the write addressing includes a subfield group s.
Only one period is assigned to each of fg1 to sfg4. That is, each subfield group sfg1 to sfg
In 4, reset processing is performed first, and thereafter, write addressing and lighting maintenance are performed for each subfield.

Since the addressing is in a write format,
When only one subfield is turned on in each of the subfield groups sfg1 to sfg4, the subfield is limited to the rear side. For example, when the gray level to be reproduced of the cell of interest is “9”, the subfield group sf
The subfield sf6 of g3 is turned on. That is,
In the address period TA of the front subfield sf5, no writing (formation of wall charges) is performed on the cell of interest,
Writing is performed on the cell of interest in the address period TA of the rear subfield sf6. Subfield sf
The lighting sustain voltage is applied in both the sustain periods TS5 and sf6, but the target cell is not lit in the sustain period TS of the subfield sf5 where no writing has been performed. When the gradation level is “18” and both the subfields sf5 and sf6 are turned on, writing is performed in the address period TA of the preceding subfield sf5. Thus, each subfield group sfg1 to sf
By changing the timing of writing according to the gradation level to be reproduced for each g4, the number of reset processing can be reduced to the number of subfield groups, and the number of addressing can be reduced to the number of subfield groups or less. When the gradation level to be reproduced is "0", addressing is unnecessary.

[0011]

FIG. 7 is a diagram for explaining a problem in the conventional driving method. FIG. 7 (A)
Indicates the gray level to be reproduced of each cell C, and the symbol “★” in FIG. 7B indicates that the cell is lit in the subfield.

Conventionally, as shown in FIG. 7A, lighting is performed only in one subfield sfg8 of a high-brightness subfield group having a relatively large sum of luminance weights (for example, a subfield group sfg4 having a maximum sum). A cell (in the illustrated example, a cell having a gray level of “27”) and a cell to be lit in all subfields of a subfield group having a smaller sum of weights than the high luminance subfield group (in the illustrated example, a gray level “27”) 26 "), when displaying a moving image having a portion adjacent thereto, the boundary of the gradation level looks unnaturally bright or dark. That is, as shown in FIG. 7B, the light emitting pattern (lighting time distribution) of the field is between the cell of the gradation level "26" and the cell of the gradation level "27".
Are extremely different from each other, so that there is a problem that so-called dynamic false contours are conspicuous and display quality is deteriorated.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the discontinuity of a light emission pattern between gradation levels and realize a high-quality moving image display in which a moving false contour is inconspicuous.

[0014]

According to the method of the present invention, one field is composed of three or more sub-fields weighted with luminance, and the set of sub-fields for one field is determined by the number of sub-fields. An initialization process for erasing the residual charge is performed once for each of the subfield groups divided into a small number of two or more subfield groups,
What is claimed is: 1. A method of driving an AC-type PDP, comprising: performing a write addressing and applying a voltage for maintaining lighting for each of said sub-fields; The subfields are divided so that two or more subfields belong to the group, and the weight of the luminance of at least the last subfield in at least one subfield group including the highest luminance subfield group is determined. Is selected to be larger than the maximum weight of subfields belonging to a subfield group that is smaller than the weight of the other subfields and has a smaller luminance weight than the subfield group other than the subfield group.

In the driving method according to the second aspect of the present invention, the display timing of the highest luminance subfield group is selected in the middle of a field period. The field in the present invention is:
It is a unit image of a time-series image display. That is, in the case of television, it means each field of an interlaced frame, and is a non-interlaced format represented by a computer output (can be regarded as a one-to-one interlaced format).
Means the frame itself.

[0016]

FIG. 1 is a configuration diagram of a plasma display device 100 according to the present invention. Plasma display device 100
Is a drive unit 80 for selectively lighting an AC type PDP 1 which is a matrix type color display device and a large number of cells C constituting a screen (screen) SC.
And a wall-mounted television receiver,
It is used as a monitor for computer systems.

In the PDP 1, a pair of sustain electrodes X and Y as first and second main electrodes are arranged in parallel, and in each cell C, the sustain electrodes X and Y and an address electrode A as a third electrode are connected. This is a PDP having a three-electrode surface discharge structure arranged in an intersecting manner. The sustain electrodes X and Y extend in the row direction (horizontal direction) of the screen, and one of the sustain electrodes Y is used as a scan electrode for selecting cells on a row basis in addressing. The address electrodes A extend in the column direction (vertical direction), and are used as data electrodes for selecting cells in column units. A region where the sustain electrode group and the address electrode group intersect is a display region, that is, a screen SC.

The drive unit 80 includes a controller 81,
It has a frame memory 82, a data processing circuit 83, a subfield memory 84, a power supply circuit 85, an X driver 87, a Y driver 88, and an address driver 89.
Field data Df in pixel units indicating luminance levels (gradation levels) of R, G, and B colors is input to the drive unit 80 from an external device such as a TV tuner or a computer, together with various synchronization signals.

The field data Df is once stored in the frame memory 82 and then sent to the data processing circuit 83. The data processing circuit 83 is data conversion means for setting a combination of subfields to be turned on, and outputs subfield data Dsf corresponding to the field data Df. The subfield data Dsf is stored in the subfield memory 84. The value of each bit of the subfield data Dsf is information indicating whether or not the cells in the subfield need to be lit, more precisely, whether or not the address discharge is necessary.

The X driver 87 applies a drive voltage to the sustain electrode X, and the Y driver 88 applies a drive voltage to the sustain electrode Y. The address driver 89 applies a drive voltage to the address electrode A according to the subfield data Dsf. These drivers are supplied with predetermined power from a power supply circuit 85.

FIG. 2 is a perspective view showing the internal structure of the PDP 1. In the PDP 1, a pair of sustain electrodes X and Y are arranged on the inner surface of the glass substrate 11 on the front side for each row L which is a horizontal cell column in the matrix screen. The sustain electrodes X and Y are each composed of a transparent conductive film 4.
1 and a metal film (bus conductor) 42 and are covered with a dielectric layer 17 of low melting point glass having a thickness of about 30 μm. On the surface of the dielectric layer 17, a protective film 18 made of magnesia (MgO) and having a thickness of several thousand angstroms is provided. The address electrode A is connected to the glass substrate 21 on the rear side.
Are arranged on the underlayer 22 covering the inner surface of
It is covered with a dielectric layer 24 of about 0 μm. On the dielectric layer 24, a partition 29 having a height of 150 μm and having a linear band shape in a plan view is provided between each address electrode A. These partition walls 29 divide the discharge space 30 in the row direction for each sub-pixel (unit light-emitting region), and define the gap size of the discharge space 30. And
R and R for color display are covered so as to cover the wall surface on the back side including the upper side of the address electrode A and the side surface of the partition wall 29.
Phosphor layers 28R, 28G, and 28B of three colors G and B are provided. One pixel (pixel) of the display is composed of three sub-pixels arranged in the row direction, and the sub-pixels in each column have the same emission color. The structure in each sub-pixel is a cell (display element) C. Since the arrangement pattern of the partition walls 29 is a stripe pattern, a portion corresponding to each column in the discharge space 30 is continuous in the column direction across all the rows L.

Hereinafter, the PDP in the plasma display device 1 will be described.
The first driving method will be described. FIG. 3 is a diagram showing a field configuration of the present invention. FIG. 3A shows the weights of the subfields in a table format, and FIG. 3B shows the breakdown of the field periods.

In order to reproduce the gradation by the binary lighting control, each of the time-series fields f as the input image is divided into, for example, eight sub-fields sf as in the conventional example (see FIG. 6).
1, sf2, sf3, sf4, sf5, sf6, sf
7, sf8. In other words, field f is 8
It is replaced with a set of subfields sf1 to sf8 and displayed. An address period TA and a sustain period TS are assigned to each of the subfields sf1 to sf8. Then, in order to reduce the number of times of addressing, a plurality of (four in the example) subfield groups sfg1, sfg2, and sfg are arranged in order of two subfields sf1 to sf8.
3, sfg4. Each subfield group sfg1
Ｓsfg4 is assigned a reset period TR for preparing for addressing. The above field division is the same as the conventional example (see FIG. 6) except for the weighting described below.

In this embodiment, the subfields sf1, sf2 belonging to the first subfield group sfg1
, The weight of the luminance of the subfields sf3 and sf4 belonging to the second subfield group sfg2 is set to “3”, and the third subfield group sf
The weight of the luminance of the subfields sf5 and sf6 belonging to g3 is “9”. Here, in the second and third subfield groups sfg2 and sfg3, the weight of each subfield is an integer multiple of the minimum weight (“1”) and is a value obtained by adding 1 to the sum of weights smaller than the minimum. is there. That is, 3 = 1 × 2 + 1 and 9 = 1 × 2 + 3 × 2 + 1. The fourth subfield group sfg4 also has a basic weight “27 (= 1 × 2 + 3 × 2 + 9 ×) in the same manner as the second and third subfield groups sfg2 and sfg3.
2 + 1) ”is set. However, the subfield sf displayed last in the fourth subfield group sfg4
Regarding 8, a value smaller than the basic weight "27" and larger than the maximum value "9" of the weights of the other subfield groups sfg1 to sfg3, for example, "19" is set as the weight according to the present invention. The above 1,1,3,3,9,9,2
According to the field configuration of weighting of 7, 19, 73 gradations of gradation levels "0" to "72" can be displayed by combining the presence or absence of lighting of the subfield. Note that the reset period TR and the address period TA have a fixed length, but the sustain period TS is longer as the luminance weight is larger.

The display order of the subfield groups sfg1 to sfg4 is sfg1 → sfg3 → sfg4 → sfg2. According to this order, the subfield group sfg4 having the largest sum of the weights is displayed in the middle of the field period, and when the fields before and after are combined, the emission is dispersed and the display quality is improved.

FIG. 4 is a diagram showing a light emitting pattern according to the present invention. The numbers in FIG. 7A indicate the gradation levels to be reproduced in each cell C, and the symbol “★” in FIG. 7B indicates that the cells are lit in the subfield. Illustrative gradation levels are the same as in the conventional example of FIG.

In the cell C of the gradation level "26", the subfields sf1, sf2, sf5, sf6, sf3, sf
4 is turned on, and in the cell C of the gradation level "27", the subfields sf1, sf2, sf8, sf3, and sf4 are turned on. As is clear from the comparison between the example of FIG. 4 and the conventional example of FIG. 7, in this embodiment, the light emission pattern of the gradation level “26” and the light emission pattern of the gradation level “27” are similar. Therefore, even when a moving image having a portion where the cell C of the gradation level “26” and the cell C of the gradation level “27” have adjacent portions is displayed, a moving false contour hardly occurs.

In the above embodiment, the subfield sfg4 of the subfield group sfg4 having the largest luminance weight
An example in which the weight of f8 is set to a value different from that of the subfield sf7 is given. However, the weight of the subfield sf6 of the subfield group sfg3 having the second largest luminance weight is set to a value different from that of the subfield sf6, for example, “5”. If it is set, it is more effective in suppressing the false contour.

FIG. 5 is a waveform diagram of the driving voltage. As described above, the reset period TR is set in each of the subfield groups sfg1 to sfg1.
This is provided at the forefront of the sfg4 allocation period. In this reset period TR, for example, a positive write pulse having a sufficiently high peak value is simultaneously applied to all the sustain electrodes X to erase charges on the entire screen. . A strong discharge is generated by application of the write pulse, and excessive wall charges are charged. When the write pulse falls, an excessive wall voltage is applied to the cell, so-called self-erasing discharge occurs, and the wall charge disappears. When applying the address pulse, the address electrode A is biased to a positive potential in order to prevent discharge between the sustain electrode X and the address electrode A.

After the reset process, in the address period TA, a scan pulse Py is applied to each sustain electrode Y sequentially from the top line, and an address pulse Pa is applied to an address electrode A corresponding to a cell to be turned on in parallel with the scan pulse Py.
In the cells to which the scan pulse Py and the address pulse Pa have been applied, an address discharge occurs to form a predetermined amount of wall charges. In the sustain period TS, first, a sustain pulse Ps of positive polarity is applied to the sustain electrode Y, and thereafter, the sustain pulse Ps is alternately applied to the sustain electrode X and the sustain electrode Y. A discharge occurs in the cell written in the address period TA for each application, and an apparently continuous lighting state is maintained.

Even if the sustain pulse Ps is applied in the state where the reset processing has been performed, the cell is not turned on. Lights up only in the sustain period TS after the write addressing is performed. Therefore, each subfield group sfg1-sfg1-s
In fg4, for a cell having a gradation level for lighting m (1 ≦ m ≦ n) subfields out of n (2 in the example) subfields belonging to it, (n−m
Wall charges are formed in the (+1) th address period TA.
Writing is not performed on cells of a gradation level for lighting 0 subfields. By changing the writing time according to the gradation level to be reproduced for each of the subfield groups sfg1 to sfg4, the number of times of resetting the entire screen can be reduced to the number of subfield groups, and the number of addressing times can be reduced. Can be reduced to less than the number of subfield groups.

[0032]

According to the first or second aspect of the present invention,
It is possible to alleviate the discontinuity of the light emission pattern between the gradation levels, and realize a high-quality moving image display in which a moving false contour is inconspicuous.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a plasma display device according to the present invention.

FIG. 2 is a perspective view showing an internal structure of the PDP.

FIG. 3 is a diagram showing an example of a field configuration to which a driving method according to the present invention is applied.

FIG. 4 is a diagram showing a light emitting pattern according to the present invention.

FIG. 5 is a waveform diagram of a driving voltage.

FIG. 6 is a conventional field configuration diagram.

FIG. 7 is a diagram for explaining a problem in a conventional driving method.

[Explanation of symbols]

1 PDP (AC type PDP) f field sf1-8 subfield sfg1-4 subfield group sfg4 subfield group (highest brightness subfield group) Tf field period TR reset period (period for performing initialization processing) TA address period (writing) Addressing period) TS sustain period (period for applying voltage to maintain lighting)

Claims (2)

[Claims] 1. One field is composed of three or more subfields weighted with luminance, and the set of subfields for one field is divided into two or more subfield groups having a smaller number of subfields. A method for driving an AC-type PDP, wherein an initialization process for erasing residual charges is performed once for each subfield group, and write addressing and voltage application for maintaining lighting are performed for each subfield. The subfields are divided so that two or more subfields belong to the highest luminance subfield group having the highest luminance of the subfields belonging to the subfield group, and at least one or more subfields including the highest luminance subfield group are included. The luminance weight of at least the last subfield in the subfield group is The weight is selected to be smaller than the weight of the other subfields in the field group and larger than the maximum weight of the subfields belonging to the subfield group other than the subfield group and having a smaller luminance weight than the subfield group. AC type P
Driving method of DP. 2. The AC according to claim 1, wherein a display time of said group of highest luminance subfields is selected in a middle period of a field period.
Driving method of type PDP.