JPH11184427A - Pdp driving method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To uniformize a discharge condition related to addressing and to eliminate a disturbance in a display. SOLUTION: In a matrix display by an AC type PDP(plasma display panel) of a structure generating a surface discharge by electrodes each other extending in the row direction and covered with a dielectric layer, respective rows of a picture are classified to plural groups K1, K2, K3, and addressing preparation uniformizing a charged distribution and the addressing forming the charged distribution according to display contents are performed at every groups K1, K2, K3 in time division.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface discharge AC
The present invention relates to a method for driving a PDP (Plasma Display Panel).

2. Description of the Related Art In PDPs, high definition and large screens have been promoted for application to high vision.
The number of cells (that is, the number of pixels) tends to increase. As the number of lines on the screen (the number of lines) increases, the time required for addressing increases.

[0003]

2. Description of the Related Art As a color display device, an AC type PDP having a three-electrode surface discharge structure has been commercialized. In this configuration, a pair of main electrodes for maintaining lighting are arranged for each row of the matrix display, and address electrodes are arranged for each column.
Since the display is of the AC type, the memory function of the dielectric layer covering the main electrode is used for display. That is, addressing for forming a charged state according to display contents is performed, and thereafter, a lighting sustaining voltage Vs having an alternating polarity is applied to all the main electrode pairs simultaneously. As a result, only in the cell where the wall charge exists, the effective voltage (also referred to as the cell voltage) Veff exceeds the firing voltage Vf, and a surface discharge occurs along the substrate surface.

When displaying a time-series image, it is desirable to temporarily initialize the charged state of the cell as a preparation for addressing during a period from the end of lighting of one image to the addressing of the next image. The discharge condition of each cell is made constant. Addressing preparation for performing so-called erase addressing is a process of charging each cell with an appropriate amount of wall charge regardless of whether or not wall charge has been erased in the previous addressing. The preparation for addressing in the case of performing write addressing is a process of setting a cell to a non-charged state. Note that erase addressing is a process of causing an address discharge only in cells that do not need to be lighted to erase wall charges, and write addressing is a process of causing an address discharge only in cells to be lighted and charging the wall charges.

[0005] Unlike addressing, addressing preparation does not need to be performed line by line. Conventionally, addressing preparations have been made to apply a predetermined voltage to all rows at the same time to cause discharge, thereby making the entire charged state of the screen uniform at once.

[0006]

Conventionally, as described above, addressing preparations have been made simultaneously for all the rows, so that the first row selected in the subsequent addressing and the last row selected in the subsequent addressing are prepared. The elapsed time from addressing preparation to addressing was greatly different. That is, the addressing of the last row starts from the addressing of the first row and starts at the scanning cycle (for example, 1.5 μs).
Will be delayed by about the number of lines. For this reason, especially in the case of erasing addressing, as the addressing time is delayed, the wall charge is attenuated and the discharge probability is reduced (specifically, the start voltage of the address discharge is increased by about 5 to 10 V). There is a problem that it is difficult to secure a drive voltage margin.

In order to display a high-definition full-color moving image,
It is necessary to use erase addressing that is faster than write addressing. However, in the conventional driving method, display disorder is likely to occur due to an address discharge error in the rear end portion of the addressing in the screen.

SUMMARY OF THE INVENTION It is an object of the present invention to equalize discharge conditions relating to addressing and eliminate display disturbance.

[0009]

According to a first aspect of the present invention, there is provided a method of driving an AC type PDP having a structure in which a surface discharge is generated between electrodes extending in a row direction and covered with a dielectric layer, Each line of the screen is classified so as to belong to one of a plurality of groups smaller than the number of lines, and addressing preparation for uniforming the charge distribution and addressing for forming a charge distribution according to display contents are time-divided for each group. Is what you do.

In the driving method according to the second aspect of the present invention, the addressing preparation is a process of charging a wall charge to a cell, and the addressing is a process of erasing a wall charge of a cell that does not need to be turned on for each row.

In a driving method according to a third aspect of the present invention, the preparation of addressing between the groups and the order in which the addressing is performed are periodically changed. Claim 4
In the driving method according to the invention, after the addressing of all the groups is completed, a voltage for maintaining lighting is applied to the pair of electrodes defining each row at the same time.

In a driving method according to a fifth aspect of the present invention, a driving circuit that can be independently controlled is provided for each of the groups, and for the group whose addressing has been completed, the lighting is maintained in parallel with the addressing of the other groups. Is applied.

[0013]

FIG. 1 is a configuration diagram of a plasma display device 100 according to a first embodiment. The plasma display device 100 is a flat type color display device AC
Type PDP 1 and a drive unit 80 for selectively lighting vertically and horizontally arranged cells C constituting a screen SC, and as a wall-mounted television receiver, a monitor of a computer system, etc. Used.

In the PDP 1, sustain electrodes X and Y as a pair of first and second main electrodes are arranged in parallel, and in each cell C, the sustain electrodes X and Y and an address electrode A as a third electrode are connected. This is a PDP having an intersecting surface discharge structure. The sustain electrodes X and Y are in the row direction (horizontal direction) of the screen.
And one sustain electrode Y is used as a scan electrode for selecting a cell C in a row unit at the time of addressing. The address electrode A extends in the column direction (vertical direction), and is used as a data electrode for selecting a cell C in a column unit. A region where the sustain electrode group and the address electrode group intersect is a display region, that is, a screen SC.

The drive unit 80 includes a controller 81,
A frame memory 82, a data processing circuit 83, a subfield memory 84, a power supply circuit 85, an X driver circuit 87,
Y driver circuit 88 and address driver circuit 89
A, 89B. The drive unit 80 includes a TV
R, G, B from external devices such as tuner and computer
The pixel-based field data DF indicating the luminance level (gradation level) of each color is input together with various synchronization signals.

The field data DF is once stored in the frame memory 82 and then sent to the data processing circuit 83. The data processing circuit 83 is data conversion means for dividing a field into a predetermined number of subfields and performing gradation display, as described later, and outputs subfield data Dsf corresponding to the field data DF. The subfield data Dsf is stored in the subfield memory 84. The value of each bit of the subfield data Dsf is
Information indicating the necessity of lighting the cell in the subfield,
Strictly, it is information indicating whether address discharge is necessary.

The X driver circuit 87 applies a drive voltage to the sustain electrode X, and the Y driver circuit 88 applies a drive voltage to the sustain electrode Y. Address driver circuit 89
A and 89B apply a drive voltage to the address electrode A. A predetermined power is supplied from the power supply circuit 85 to these driver circuits.

The drive unit 80 is arranged on the back side of the PDP 1, and each driver circuit and the electrodes are electrically connected by a flexible cable (not shown). In order to make the connection strength uniform, three to five flexible cables are used for each driver circuit.

FIG. 2 is a perspective view showing the internal structure of the PDP 1. In the PDP 1, a pair of sustain electrodes X and Y are arranged for each row L on the inner surface of the glass substrate 11 on the front side. Row L is a horizontal cell column on the screen.
Each of the sustain electrodes X and Y is composed of a transparent conductive film 41 and a metal film (bus conductor) 42, and is covered with a dielectric layer 17 made of low melting point glass and having a thickness of about 30 μm. On the surface of the dielectric layer 17, a protective film 18 made of magnesia (MgO) and having a thickness of several thousand angstroms is provided. The address electrodes A are arranged on a base layer 22 that covers the inner surface of the glass substrate 21 on the rear side, and have a thickness of 10 mm.
It is covered with a dielectric layer 24 of about μm. On the dielectric layer 24, a partition 29 having a height of 150 μm and having a linear band shape in a plan view is provided between each address electrode A. These partition walls 29 divide the discharge space 30 in the row direction for each sub-pixel (unit light-emitting region), and define the gap size of the discharge space 30. Then, R, G, and R for color display are covered so as to cover the inner surface on the back side including the upper side of the address electrode A and the side surface of the partition wall 29.
The three color phosphor layers 28R, 28G, and 28B are provided. The discharge space 30 is filled with a discharge gas in which xenon is mixed with neon as a main component.
28G and 28B are locally excited by ultraviolet light emitted by xenon during discharge to emit light. One pixel (pixel) of the display is composed of three sub-pixels arranged in the row direction.
The structure in each sub-pixel is a cell (display element) C. Since the arrangement pattern of the partition walls 29 is a stripe pattern, a portion corresponding to each column in the discharge space 30 is continuous in the column direction across all the rows L.

Hereinafter, P in the plasma display device 100 will be described.
The driving method of DP1 will be described. FIG. 3 is a diagram showing a field configuration and a basic drive sequence. For example, in the display of a television image, in order to reproduce gradation by binary lighting control, each field f of a time series as an input image (a subscript of a code represents a display order) is, for example, 8 sub-frames. sf1, sf2, sf3, sf4, sf
5, sf6, sf7, and sf8. In other words, each field f forming the frame F is replaced with a set of eight sub-frames sf1 to sf8. However,
When a non-interlaced image such as a computer output is reproduced, each frame is divided into eight. And
Weighting is performed so that the relative ratio of luminance in these subfields sf1 to sf8 is 1: 2: 4: 8: 16: 32: 64: 128.
The number of sustain discharges of f8 is set. It is 256 for each color of RGB by lighting / non-lighting combination in subfield units.
Since the luminance can be set stepwise, the number of colors that can be displayed is 256 ³ . Note that the subfields sf1 to sf1
It is not necessary to display sf8 in the order of the luminance weight. For example, optimization such as placing the subfield sf8 having a large weight in the middle of the display period can be performed.

The subfield period Tsf assigned to each of the subfields sf1 to sf8 includes an addressing preparation period TR, an address period TA, and a sustain period TS
Consists of The sustain period TS is a period during which the lighting state is maintained in order to secure luminance according to the gradation level. In each subfield period Tsf, the reset period TR
The length of the address period TA is constant regardless of the luminance weight, but the length of the sustain period TS is longer as the luminance weight is larger. That is, the lengths of the eight subfield periods Tsf corresponding to one field f are different from each other.

In the addressing preparation period TR,
A first step of applying a positive voltage pulse Pr to the sustain electrode X; and a positive voltage pulse P to the sustain electrode X.
By applying the rx and applying the negative voltage pulse Pry to the sustain electrode Y, the “last time lit cell” illuminated in the immediately preceding subfield and the “last time non-illuminated cell” not illuminated are obtained. A wall charge of a predetermined polarity is formed. In the first step, the address electrode A is set to 50
Bias to a positive potential of about 120 V
Unnecessary discharge between the electrode and the sustain electrode X is prevented. Subsequent to the second step, a positive voltage pulse Prs is applied to the sustain electrode Y to increase surface uniformity in all cells in order to improve the uniformity of charging. The charging polarity is reversed by this surface discharge. After that, the potential of the sustain electrode Y is gradually reduced to a predetermined value in order to avoid the loss of charge.

In the address period TA, each row is selected one by one in order, and a negative scan pulse Py is applied to the corresponding sustain electrode Y. Simultaneously with the selection of the row, a positive address pulse Pa is applied to the address electrode A corresponding to the cell to be turned off (the non-lighted cell this time). In the cell to which the address pulse Pa is applied in the selected row, a counter discharge occurs between the sustain electrode Y and the address electrode A, and the wall charges of the dielectric layer 17 disappear. At the time of application of the address pulse Pa, positive wall charges exist near the sustain electrode X, so that the address pulse Pa is canceled by the wall voltage, and no discharge occurs between the sustain electrode X and the address electrode A. . Such erasing addressing is suitable for high-speed operation, because it does not require the regeneration of charges unlike the writing method.

In the sustain period TS, all the address electrodes A are biased to a positive potential in order to prevent unnecessary discharge, and a positive sustain pulse Ps is first applied to all the sustain electrodes X. Thereafter, a sustain pulse Ps is alternately applied to the sustain electrodes Y and the sustain electrodes X. In the present embodiment, the last sustain pulse Ps is applied to the sustain electrode Y.
By applying the sustain pulse Ps, the address period T
At A, a surface discharge occurs in a cell where the wall charges are left (the currently lit cell).

Table 1 shows an example of the peak value and pulse width of each pulse.

[0026]

[Table 1]

FIG. 4 is a diagram showing a driving sequence. In the plasma display device 100, the addressing preparation and the addressing are not performed simultaneously for all the rows L, and the screen is divided into blocks K1 and K, for example, divided into three in the column direction.
2 and K3 in time division. In the example of FIG. 4, the total number of rows is 480, and the number of rows in each of the blocks K1 to K3 is 16
0. As the number of screen divisions increases, the time lag of address discharge between the first row and the last row of row selection (scanning) decreases, but the number of addressing preparations per subfield increases. This must be taken into account when selecting the number of divisions. Also, from the viewpoint of circuit configuration and assembly, the number of divisions is adjusted to the number of flexible cables used to connect each sustain electrode Y and the drive unit 80, and the screen is divided according to the distribution of the rows L to each flexible cable. It is desirable to do.

In the example of FIG. 4, the first block K1 → the second block K1
, The addressing is performed in the order of the block K2 → the third block K3, and thereafter, sustaining (lighting maintenance) is performed simultaneously in all the blocks K1 to K3. That is, the addressing preparation period, the addressing period, and the sustain period are completely separated in time. The order of preparing the addressing and performing the addressing is not limited to the ascending order of the line numbers (the order shown), but may be the descending order of the line numbers (K3 → K2 → K1). In addition, the order may be switched between ascending order and descending order for each subfield or for each field, or may be an unspecified order using random numbers.

FIG. 5 is a schematic diagram of voltage application to the main electrode. X driver circuit 87 has voltage pulses Pr, Prx
A switching device for controlling application of (voltage Vwx) is provided for each of the blocks K1 to K3. Switching devices for controlling the application of the voltage pulses Pr and Prx (voltage Vwy) to the Y driver circuit 88 are also provided in blocks K1 to K1.
It is provided for each K3. As a result, addressing preparation and addressing can be performed in a time-division manner as described above. Note that the sustain pulse Ps (voltage Vs)
Is applied in common to all the rows L without distinguishing the blocks K1 to K3.

FIG. 6 is a configuration diagram of a main part of a plasma display device 200 according to the second embodiment. Plasma display device 2
Reference numeral 00 denotes a PDP 1 having the above-described structure and a drive unit for selectively lighting the cell. In the plasma display device 200, in order to apply a drive voltage to the sustain electrode X, an X driver circuit 9 that can be controlled independently of each other for each block obtained by dividing the screen into three in the column direction.
7A, 97B and 97C are provided. Similarly, for the sustain electrode Y, Y driver circuits 98A, 98B, 98C are provided for each block. Although it has two address driver circuits 99A and 99B,
This is because the external connection terminals of the address electrode A are provided separately at both ends of the substrate 21. The address electrode A in each column extends over three blocks, and is common to all rows.

FIG. 7 is a diagram showing a drive sequence according to the second embodiment. In the plasma display device 200 as well, preparation for addressing and addressing are performed in a time-division manner for each block as in the above-described embodiment. However, sustaining is performed sequentially from the block for which addressing has been completed, without waiting for the end of addressing for all rows. That is, addressing of certain blocks K2 and K3 and sustaining of blocks K1 and K2 whose addressing has been completed before that are performed in parallel. The addressing preparation for the next subfield may be started in order from the block where the sustain has been completed, or the addressing preparation for the next subfield may be started after the sustain of all the blocks K1 to K3 is completed. Is also good.

According to the above embodiment, the current capacity required for the drive circuit components in preparation for addressing is reduced to 1/3 of the conventional one, so that the drive unit can be reduced in cost.

According to the above embodiment, the addressing preparation is performed for each of the blocks K1 to K3 arranged in the column direction.
The wiring of the drive circuit is simple. However, a certain number of addresses to be prepared for each addressing (16
The rows in 0) do not need to be adjacent to each other, and the rows can be arbitrarily selected and grouped. The number of rows in each group may be different from each other.

In the above embodiment, the address pulse P is used to reduce the deterioration of the phosphor due to the address discharge.
a is defined as positive polarity, and the polarity of other pulses is set.
An example was given in which the driving circuit was simplified by applying a positive sustain pulse to only one of the sustain electrodes, but the present invention is not limited to this. That is, the polarity of the applied voltage can be changed. Regarding the voltage pulses Prx and Pry in the second step in the addressing preparation, the peak value can be arbitrarily assigned, but it is advantageous to use a combination of Vs and −Vs which are equally assigned as illustrated in the circuit configuration.

[0035]

According to the first to fifth aspects of the present invention,
Discharge conditions relating to addressing can be equalized and display disturbance can be eliminated.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a plasma display device according to a first embodiment.

FIG. 2 is a perspective view showing an internal structure of the PDP.

FIG. 3 is a diagram showing a field configuration and a basic drive sequence.

FIG. 4 is a diagram showing a driving sequence.

FIG. 5 is a schematic diagram of voltage application to a main electrode.

FIG. 6 is a configuration diagram of a main part of a plasma display device according to a second embodiment.

FIG. 7 is a diagram illustrating a drive sequence according to the second embodiment.

[Explanation of symbols]

 1 PDP X, Y sustain electrode (electrode) 17 L row K1, K2, K3 group C cell Ps sustain pulse (voltage for maintaining lighting) 97A-B X driver circuit (drive circuit) 98A-BY driver circuit (drive) circuit)

Claims (5)

[Claims] 1. A method of driving an AC-type PDP having a structure in which surface discharge is generated by electrodes extending in a row direction and covered with a dielectric layer, wherein each row of a screen is divided into a plurality of groups smaller than the number of rows. A method for driving a PDP, characterized in that addressing preparation for uniforming the charge distribution and addressing for forming a charge distribution in accordance with display contents are performed in a time-division manner for each of the groups. 2. The method of driving a PDP according to claim 1, wherein said preparation for addressing is a process of charging a cell with wall charges, and said addressing is a process of erasing a wall charge of a cell which does not need to be turned on for each row. . 3. The method of driving a PDP according to claim 1, wherein an addressing preparation between the groups and an order relationship in which the addressing is performed are periodically changed. 4. After all groups have been addressed,
4. The method of driving a PDP according to claim 1, wherein a voltage for maintaining lighting is simultaneously applied to the pair of electrodes defining each of the rows. 5. 5. A driving circuit which is independently controllable for each group, and a voltage for maintaining lighting is applied to the group after the addressing in parallel with the addressing of the other groups. The method of driving a PDP according to claim 3.