KR20010068700A - method of driving a plasma display panel - Google Patents

Abstract

PURPOSE: A method for driving a plasma display panel is provided to improve the contrast and the color purity by lowering the back brightness and to prevent the data writing error and to secure the enough display time by permitting the optimum elimination pulse unconcerned with the structural deviation of a panel. CONSTITUTION: In the method for driving the plasma display panel, a field and many sub-fields are included. One field is divided into 8 sub-fields. The contrast ratio is decided as the ratio of the condition, in which each serve field didn't permit the maintaining pulse, and the condition, in which the maintaining pulse assigned to each sub-field is displayed. Thereby the contrast ratio is decided as the lowest and highest brightness ratio of one field. And if the lowest brightness is lowered, the contrast is raised. Each sub-field includes the maintaining discharge period and the reset period. If the brightness in the reset period of all the sub-fields is added, it is the lowest brightness.

Description

Method of driving a plasma display panel

The present invention relates to a method of driving a plasma display panel, and more particularly, to a method of driving a plasma display panel in which a background luminance of a plasma display device is reduced, and contrast and color purity are improved to improve characteristics of the panel. .

FIG. 1 shows a schematic partial cross-sectional view for explaining the structure of the plasma display panel. As shown in FIG. 1, the plasma display panel includes a front electrode group formed of the X electrode 3 and the Y electrode 4. The dielectric layer 6 is formed on the front substrate 1. In addition, an address electrode 5 is formed on the opposite rear substrate 2 of the front substrate 1, a dielectric layer 7 is formed thereon, and a fluorescent layer 9 is formed between the partitions 8. .

In the driving method of the plasma display panel configured as described above, as shown in FIG. 2, one field is divided into, for example, first to eighth subfields for gray scale display, and each subfield is assigned to a reset period and an address. Each subfield is provided with a specific sustain period, and the gray level of the video screen is displayed by the combination of these subfields.

In the reset period of each subfield, as shown in FIG. 2, the front write pulse Vw is applied to the X electrodes commonly connected to discharge all the cells. The wall charges are accumulated on the dielectric layers covering the X electrode and the Y electrode by this front-side discharge, that is, -charge () on the X electrode and + charge () on the Y electrode as shown in FIG. ) Is accumulated. Next, a gradually increasing priming erase pulse is applied to further initialize cells completely by further discharging the cells whose wall charges are not completely erased due to nonuniformity of the cells as shown in FIG. Such an initialization process is an essential process for distinguishing each subfield when a gray level is expressed by dividing one field into a plurality of subfields.

In general, when one field is divided into a plurality of fields, for example, eight subfields, to express gradation, the contrast ratio is a state in which a sustain pulse is not applied to each subfield at all and the sustain pulses allocated to each subfield are all. It is determined as the ratio of the displayed state. Therefore, since the contrast ratio is determined by the minimum luminance and the highest luminance ratio of one field, the contrast can be increased by lowering the minimum luminance, that is, the background luminance. However, as described above, each subfield further includes a reset period in addition to the sustain discharge period for the actual display. The sum of the luminance in the reset periods of all the subfields is the lowest luminance.

As a proposal for lowering the minimum luminance as described above, as shown in FIG. 4, one field is divided into eight subfields, and the first subfield of the eight subfields has a front write period and a full erase period. And an address period and a sustain discharge period, and the second to eighth subfields include a front erasing period, an address period, and a sustain discharge period (Japanese Patent Laid-Open No. 5-313598). This method has an advantage of improving contrast by lowering background luminance. However, there is no problem in the address period of the first subfield, but only the erase pulse is applied in the second subfield to the eighth subfield without performing the front write, so that the discharge condition of the cells becomes irregular as the number of subfields increases. There is a problem that a data write error occurs during the address period. In this case, the erase pulse used is a narrow pulse, which is very effective in erasing wall charges on the dielectric layer, but includes an insufficient initialization problem due to irregular distribution of wall charges due to structural differences of cells.

As another proposal for the above-described initialization method, an erase pulse which gradually increases at a time of 5 to 10 ms in the resetting process of all subfields is applied (Japanese Patent Laid-Open No. 8-212930). In general, the erase function of the wall charge is excellent in the narrow square erase pulse, and the erase pulse gradually increasing with time is relatively decreased. On the contrary, when the wall charge distribution of each cell is uneven, an erase pulse gradually increasing with time is more advantageous in terms of reliability, and a narrow square erase pulse is relatively inferior. In this method, since there is no front writing process in all subfields, when a large number of fields are displayed, insufficient wall charge cancellation occurs in each subfield.

Further, Japanese Patent Laid-Open No. 8-212930 discloses setting the width of the erase pulse in the range of 5 Hz to 10 Hz. In general, if the panel has 480 lines of scan electrodes and divides one field into eight subfields, and the width of the scan pulse is about 3 ms, the address period in one subfield is about 1.44 ms (3 ms x 480). The address period of one field is approximately 11.52 ms (1.44 ms x 8). Therefore, since the time for displaying one field is 16.67 ms, the time for actually displaying is only about 4 to 5 ms. As a result, the time of about 4 to 5 ms is not enough to display a signal, so it is impossible to set the erase pulse too large.

Therefore, an object of the present invention is to provide a method of driving a plasma display panel which can prevent a data writing error while lowering background luminance to improve contrast and color purity.

Another object of the present invention is to provide a method of driving a plasma display panel that can apply an optimum erase pulse irrespective of the structural variation of the panel to ensure sufficient display time.

1 is a schematic partial cross-sectional view for explaining the configuration of a general plasma display panel;

2 is a pulse waveform diagram illustrating a conventional method of driving a plasma display panel;

3 is a diagram showing wall charge distribution according to a voltage applied to a plasma display panel;

4 is a pulse waveform diagram for explaining another conventional method of driving a plasma display panel;

5 is a pulse waveform diagram illustrating a method of driving a plasma display panel according to an embodiment of the present invention;

6 is a pulse waveform diagram illustrating an address / display separation driving method of a plasma display panel according to another embodiment of the present invention;

7 is a graph showing the voltage and time width of the erase pulse waveform used in the reset period according to the present invention;

8 is a V-Q Lissajous (Lissajous) diagram used in the measurement of the wall charge of the present invention,

9 is a graph showing the wall voltage state according to the pulse width and voltage of the present invention, and

FIG. 10 is a graph showing the erasing range when the sustain voltage of the present invention is based on 180V.

<Description of the symbols for the main parts of the drawings>

1: Front board 2: Back board

3: X electrode 4: Y electrode

5 address electrode 6,7 dielectric layer

8: bulkhead 9: fluorescent layer

10: MgO layer

In order to achieve this object, according to an embodiment of the present invention, one field is divided into a plurality of subfields, each of the subfields allocates a specific number of sustain discharge pulses, and each of the subfields is turned on / off. In the driving method of a plasma display panel in which desired gray scale display is realized by a combination of boiling points, each of the plurality of subfields has a reset period for equalizing discharge conditions of all cells and cells to be displayed according to an input signal. An address period for designation, and a sustain discharge period for applying sustain discharge pulses capable of performing a sustain discharge in overlapping with the wall charges on the dielectric covering the XY electrode to the designated cells as many as the number assigned to the corresponding subfields; In the reset period of at least one of the plurality of subfields, wall charge accumulation occurs on the dielectric covering the XY electrode. And applying an erase pulse for erasing wall charges formed by the discharge electrode to all cells, and applying all of the cells except for the at least one subfield. The reset period of the field includes applying an erase pulse having a specific time width and the voltage amplitude gradually increasing or decreasing to 244V or -244V, wherein the determination of the specific time width is determined according to the structural characteristics of the panel. It is characterized by.

In addition, according to another embodiment of the present invention, a method of driving a plasma display panel includes: dividing a field into a plurality of subfields, each of the subfields assigns a specific number of sustain discharge pulses, and each of the subfields. In the method of driving a plasma display panel in which a desired gray scale display is realized by a combination of lighting and boiling points, each of the plurality of subfields must be displayed according to a reset period and an input signal for uniformizing discharge conditions of all cells. An address period for designating cells to be performed, and a sustain discharge period for applying sustain discharge pulses capable of performing a sustain discharge by overlapping the wall charges on the dielectric covering the XY electrodes to the specified cells as many as the number assigned to the corresponding subfields. And a reset period of at least one subfield of the plurality of subfields covering an XY electrode. Applying a front write pulse capable of discharging without accumulating wall charges to all cells, and applying an erase pulse to erase all of the wall charges formed by the front write discharge to all the cells. The reset period of the remaining subfields except for the subfield is selected from the range of 5 to 150 ms, and a reset period consisting of applying an erase pulse whose voltage amplitude gradually increases or decreases to 244 V or -244 V. Characterized in that it comprises a.

Further, according to another embodiment of the present invention, one field is divided into a plurality of subfields, each of the subfields is assigned a specific number of sustain discharge pulses, and a combination of lighting / boiling points of the respective subfields. A method of driving a plasma display panel in which desired gray scale display is implemented, each of the plurality of subfields has a reset period for equalizing discharge conditions of all cells and an address for designating cells to be displayed according to an input signal. And a sustain discharge period in which sustain discharge pulses capable of performing a sustain discharge in superimposition with wall charges on the dielectric covering the XY electrodes are applied to the designated cells as many as the number assigned to the corresponding subfields. The reset period of is to apply an erase pulse that has a specific time width and the voltage amplitude increases or decreases to 244V or -244V gradually. The specific time width is applied to the plasma display panel by applying an erase pulse having a different time width to the voltage amplitude gradually up to 244 V or -244 V, and then measuring data writing characteristics for each time width. And is determined based on the measured data writing characteristics.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is a pulse waveform diagram illustrating a method of driving a plasma display panel according to an embodiment of the present invention.

In the method of driving the plasma display panel of the present invention, one field is divided into eight first to eighth subfields, and each subfield is divided into a reset period (A or B), an address period, and a sustain period. Include. In the reset period A of the first subfield, as shown in FIG. 5, a front write pulse Vw of about 350 V is applied to the X electrode to discharge all cells. As a result, wall charges are accumulated on the dielectric layers covering the X electrode and the Y electrode, that is, -charge () is accumulated on the X electrode and + charge () is accumulated on the Y electrode as shown in FIG. . Next, as shown in Fig. (C), a selective gradually increasing priming erase pulse is applied to further initialize cells completely by further discharging the cells whose wall charges are not completely erased by non-uniformity of the cells. In the next address period, scan pulses are sequentially applied to the Y electrodes and at the same time a data signal is applied to the address electrodes in accordance with the input signal. Therefore, the address discharge is performed on the cells to be displayed by the data pulses applied to the address electrodes and the scan pulses applied to the Y electrodes, so that wall charges are formed in the cells initialized in the above-described reset period A. FIG. During the sustain discharge period, the sustain discharge pulses are alternately applied to the common-connected X electrodes and all the Y electrodes by the number assigned to the corresponding subfields, so that the wall charges and sustains are displayed in the designated cells, that is, cells in which wall charges are accumulated. The sustain discharge is performed by overlapping the discharge voltage.

Next, in the reset period B of each of the remaining subfields, an erase pulse that gradually increases or decreases to a voltage amplitude of 244V or -244V is applied with a specific time width suitable for the structural characteristics of the plasma display panel. . The above-described determination of the erase pulse time width is performed by applying erase pulses having various time widths to the plasma display panel to measure data writing characteristics of the plasma display panel, and then optimally erase the plasma display panel based on the measurement result. The pulse can be determined. Measurements of data write characteristics different from the time width of the erase pulse are, for example, 5 ms, 10 ms,... After applying an erase pulse of 150 kHz, a black mode in which data is not written in all cells and a white mode in which all cells are displayed are displayed, and the degree of flicker is visually or mechanically measured. Here, in the white mode, a method of measuring the luminance according to each time width may be used.

In addition, the measuring method is a method of measuring for each individual plasma display panel and applying an erase pulse of a suitable time width to the panel, and plasma display panels made of the same material under the same manufacturing conditions are treated as the same, and only a sample is treated. It is possible to apply a specific erase pulse to the plasma display panels produced by the extraction and measuring in the same manufacturing line.

Meanwhile, in the method of driving the plasma display panel according to another embodiment of the present invention, as shown in FIG. 6, an erase pulse is applied after the sustain discharge period in order to stop the sustain discharge in one subfield. It is also possible to further include an erasing period. At this time, the erasing pulse is selected and applied to the time-sensitive erasing pulse for each individual plasma display panel or a plasma display panel produced in the same manufacturing line.

Fig. 7 shows triangular waveform pulses with increasing voltage amplitude, discharge current, and constant inclination with time. As shown in FIG. 7, the voltage gradually increases with time, and when the voltage reaching the discharge condition of the corresponding cell is reached, erase discharge is performed. At this time, if the structural and material characteristics of all the cells are equally ideal, complete erasure discharge is possible with the same voltage amplitude and time width. However, since the characteristic difference is large for each plasma display panel, for each plasma display panel produced in another manufacturing line, or for each plasma display panel produced by different materials, the optimum time width of the erase pulses varies.

Fig. 8 shows the Lissajudo used for the measurement of the wall charge, and Fig. 9 shows the wall charge distribution according to the erase pulses of various time widths. As shown in Fig. 10, it is shown that as the pulse time width increases, the erase function of wall charges also improves. In addition, when the pulse time width is 5 ms or less, it is difficult to apply because the erase function is poor. Fig. 9 shows the upper and lower use ranges of the erase pulses, and it is possible to use a voltage range of 140 to 244V.

As described above, according to the present invention, data write errors can be prevented while lowering the luminance of light emitted during the reset period, thereby reducing the overall background luminance, and as a result, it is possible to increase contrast and color purity and to increase address discharge margin. In addition, by adjusting the time width of the erase pulse in accordance with the structural material characteristic difference of the panel it is possible to improve the erase function and to improve the address operation margin.

Although the present invention has been described in detail with reference to the accompanying drawings, the present invention is not limited thereto, and modifications, improvements, and applications thereof may be made without departing from the ordinary knowledge of those skilled in the art.

Claims (14)

A method of driving a plasma display panel in which one field is divided into a plurality of subfields, each subfield is assigned a specific number of sustain discharge pulses, and a desired gray scale display is realized by a combination of lighting of the respective subfields. In Each of the plurality of subfields is maintained in overlap with a reset period for equalizing discharge conditions of all cells, an address period for designating cells to be displayed according to an input signal, and a wall charge on a dielectric covering the display electrode. And a sustain discharge period for applying sustain discharge pulses capable of performing discharge to the designated cells as many as a specific number assigned to the corresponding subfield; The reset period of each subfield includes applying an erase pulse that has a specific time width and gradually increases or decreases to a voltage of a specific value, wherein the determination of the specific time width and voltage value is performed by the structural or material of the panel. A driving method of a plasma display panel, characterized in that determined according to the characteristic. The method of claim 1, wherein the subfields further include an erase period for applying an erase pulse that gradually increases or decreases to a voltage of a specific value with a specific time width for erasing cells being sustained after the sustain discharge period. And determining the specific time width and voltage value according to structural or material properties of the panel. The method of driving a plasma display panel according to claim 1 or 2, wherein a specific time width of the erase pulse is determined within a range of 5 to 150 ms. The method of driving a plasma display panel according to claim 1 or 2, wherein the voltage of the specific value of the erase pulse is determined within a range of 140 to 244V or -140 to -244V. 3. The method according to claim 1 or 2, wherein the determination of the specific time width and the voltage of the specific value of the erasing pulse comprises applying the erasing pulses to the individual plasma display panel by applying the multi-step time width and the multi-level voltage value, respectively. Measuring write characteristics and selecting an erase pulse range optimally according to the measured result. The method according to claim 1 or 2, wherein the specific time width of the erasing pulse and the voltage value of the specific value are determined by applying a multi-step time width and a multi-step voltage value to samples extracted from plasma display panels produced in the same manufacturing line. Applying erasing pulses, measuring respective data writing characteristics, and selecting an erasing pulse range optimally according to the measured results. 3. The method according to claim 1 or 2, wherein the specific time width of the erasing pulse and the voltage determination of the specific value apply erasing pulses to the plasma display panel manufactured by the same material. And measuring each data writing characteristic and selecting an erase pulse range optimally according to the measured result. A method of driving a plasma display panel in which one field is divided into a plurality of subfields, each subfield is assigned a specific number of sustain discharge pulses, and a desired gray scale display is realized by a combination of lighting of the respective subfields. In Each of the plurality of subfields is maintained in overlap with a reset period for equalizing discharge conditions of all cells, an address period for designating cells to be displayed according to an input signal, and a wall charge on a dielectric covering the display electrode. And a sustain discharge period for applying sustain discharge pulses capable of performing discharge to the designated cells as many as a specific number assigned to the corresponding subfield; The reset period of at least one of the plurality of subfields may include applying a front write pulse capable of discharging even without wall charges accumulated on the dielectric covering the display electrode to all cells and forming the front write discharge. Applying an erase pulse to all cells that erases wall charge; The reset period of the remaining subfields except for the at least one subfield includes applying an erase pulse that gradually increases or decreases to a voltage having a specific time width, and wherein Crystals are determined according to the structural or material properties of the panel. 9. The method of claim 8, wherein the subfields further include an erase period for applying an erase pulse that gradually increases or decreases to a voltage of a specific value with a specific time width to erase cells under sustain discharge after the sustain discharge period. And determining the specific time width and voltage value according to structural or material properties of the panel. 10. The method of driving a plasma display panel according to claim 8 or 9, wherein a specific time width of the erase pulse is determined within a range of 5 to 150 ms. The method of driving a plasma display panel according to claim 8 or 9, wherein the voltage of the specific value of the erase pulse is determined within a range of 140 to 244V or -140 to -244V. 10. The method according to claim 8 or 9, wherein the determination of the specific time width and the voltage of the specific value of the erasing pulse comprises applying the erasing pulses to the individual plasma display panel by applying the multi-step time width and the multi-step voltage value, respectively. Measuring write characteristics and selecting an erase pulse range optimally according to the measured result. 10. The method according to claim 8 or 9, wherein the specific time width of the erasing pulse and the voltage value of the specific value are determined by applying a multi-step time width and a multi-step voltage value to samples extracted from plasma display panels produced in the same manufacturing line. Applying erasing pulses, measuring respective data writing characteristics, and selecting an erasing pulse range optimally according to the measured results. 10. The method according to claim 8 or 9, wherein the specific time width of the erase pulse and the voltage value of the specific value apply the erase pulses to the plasma display panel manufactured by the same material. And measuring each data writing characteristic and selecting an erase pulse range optimally according to the measured result.