JP3787713B2 - Plasma display device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a plasma display device, and more particularly to a multi-gradation plasma display device.
Recently, except for special applications such as communication, only a display device (CRT: cathode ray tube) uses a vacuum tube among all electronic devices. The disadvantage of the CRT is that the electron gun's storage cylinder protrudes far behind, so that the depth is large. Moreover, since a heater is required, power consumption is large.
[0002]
The liquid crystal display device is thin and consumes less power, and is expected to replace the CRT. However, the replacement is not progressing slowly. The main reason is the high price resulting from the poor manufacturing yield.
A plasma display device (abbreviation: PDP) also has a feature that it is thin and consumes less power, but also has an advantageous advantage that it has a higher yield than a liquid crystal display device. Liquid crystal display devices, particularly those with high-definition display, require an active switching element called TFT (thin film transistor) for each pixel, which requires a complicated manufacturing process similar to that of a semiconductor integrated circuit, which deteriorates the yield. This is because the structure of the PDP (details will be described later) is very simple and only a printing-oriented process is required.
[0003]
However, since the basic principle of the plasma display is a two-gradation display of lighting and non-lighting by gas discharge, it cannot meet the recent multi-gradation display request (Note) as it is. Note: The multi-gradation display here may be monochrome or color.
[0004]
[Prior art]
As a conventional plasma display device corresponding to multi-gradation, there is known a combination of a structure called “three electrodes, surface discharge, AC type” and a driving method called “subfield method” (for example, JP-A-7-160218).
(1) PDP cell structure There are two basic types of PDP cell structures: a DC type in which electrodes are exposed to a discharge cell, and an AC type in which an electrode is covered with an insulating layer. In terms of luminance, the current mainstream is the latter AC type (AC type). Further, the AC type PDP is also a two-electrode type in which an anode and a cathode are provided on each of two substrates, and an anode and a cathode are provided on one substrate and a third electrode (a so-called address electrode; A electrode) is provided on the other substrate. In particular, in the case of a color PDP, the three-electrode type is used because it can prevent deterioration of the phosphor. The positive / negative of the anode and cathode of the AC type PDP is determined by the polarity of the applied voltage, and there is also a polarity reversal depending on the driving method. Therefore, according to the convention, the coordinate axes (X, Y) of the panel are attached and the X electrode and It will be called a Y electrode.
[0005]
FIG. 6 is a cross-sectional structure diagram of two pixels of the three-electrode type PDP (pixels in the i-th row and i + 1-th row in the j-th row). 1 and 2 are glass substrates, 3 _i-1 , 3 _i , 3 _{i + 1} , 3 _{i + 2} are A electrodes, 4 _j is an X electrode, 5 _j is a Y electrode, 6 _j and 7 _j are transparent electrodes, 8 _i-1 , _8i , _{8i + 1} , _{8i + 2} are phosphors, 9 is an insulating film, 10 and 11 are dielectric layers, and 12 is a partition. Gas is enclosed in a space partitioned by the partition walls 12, and in this figure, an i-th discharge space 13 and an i + 1-th discharge space 14 are defined. The intersections of the discharge spaces 13 and 14 with the X electrode 4 _j and the Y electrode 5 _j become the pixel in the i-th column of the j-th row and the pixel in the i + 1-th row, respectively. In addition, a pixel may be called a cell.
(2) Sub-field method In the sub-field method, one frame or one field is divided into k sub-fields (for example, k = 8 in the case of 256 gradations, and will be described below for convenience), and each sub-field is divided. The sustain discharge period is set to a ratio of 1: 2: 4: 8: 16: 32: 64: 128, and a multi-gradation display is realized by combining these subfields.
[0006]
FIG. 7 is a conceptual diagram of a subfield type frame structure. One frame is composed of eight subfields SF _{1 to} SF ₈ and a slight interruption period (corresponding to a so-called blanking period). Each subfield is composed of three periods, that is, a “reset period”, an “address period”, and a “sustain discharge period”. The lengths of the first two periods are the same, but the sustain discharge periods t _{1 to} t ₈ are , As shown in the above ratio. L ₁ , L ₂ ,..., L _{n are} row numbers (horizontal scanning line numbers). In addition, the thick diagonal lines in the address period of each subfield schematically indicate that L ₁ , L ₂ ,..., L _n are selected in line sequence.
[0007]
FIG. 8 is a drive waveform diagram of address electrodes, X electrodes, and Y electrodes in one subfield period. Note that the voltage value used in the following description is a convenience value and is not limited to this. In the reset period, first, a positive pulse 20 of about +110 V is applied to the address electrode and a positive voltage of about +330 V is applied to the X electrode in order to provide a sufficient potential difference necessary for discharge while applying 0 V to all the Y electrodes. A pulse 21 (also referred to as a full write pulse) is applied. As a result, discharge occurs in all cells. Next, when 0 V is applied to the address electrode and the X electrode to cause discharge in all the cells again, this discharge is terminated by self-neutralization without forming wall charges because the potential difference between the electrodes is zero. Then, so-called self-erasing discharge is performed. The four pulses 22 to 26 after the self-erasing discharge are those described in the above publication, and are so-called countermeasure pulses for preventing excessive lighting. That is, a normal cell can neutralize wall charges completely (or to the extent that it does not cause a mis-display even if it remains to some extent) through the process up to self-erasing discharge, but it rarely occurs due to manufacturing factors. Abnormal cells that occur (cells that are not self-erasable or cells that do not self-erase at all) become excessively lit cells that emit light unintentionally during the sustain discharge period without address discharge, and impair display quality. End up. Therefore, in the above-mentioned publication, a positive pulse 23 of about +180 V is applied to all the Y electrodes in a state where a positive pulse 22 of about +110 V is applied to the address electrodes after self-erasing discharge, and then 0 V is applied to the address electrodes. In the applied state, a negative pulse 24 of about −150 to −160 V is applied to all the Y electrodes, and then an erase pulse 25 that gradually rises to about +180 V is applied to all the Y electrodes (hereinafter, to distinguish it from the entire surface erase pulse). And a positive pulse 26 of about +110 V having the same width as that of the residual point erasing pulse 26 is applied to the address electrode.
[0008]
In cells that discharge in response to positive pulses 22 and 23, “negative” charges remain on the X electrode side relative to the Y electrode side, and the remaining amount reaches a level at which sustain discharge is possible. Cell. In the cells that discharge in response to the negative pulse 24, “positive” charges remain on the X electrode side relative to the Y electrode side, and the remaining amount reaches a level at which sustain discharge is possible. Cell. The residual wall charges of these abnormal cells are finally largely erased by the residual pulse 25. The wall charge remaining in a small amount is a positive charge and has a polarity opposite to that of the pulse in the next address period, so that unintentional discharge is unlikely to occur and excessive lighting can be prevented.
[0009]
In the next address period, while applying a positive voltage 27 of about +50 V to the X electrode, a negative pulse 28 (hereinafter “scan pulse”) of about −150 to −160 V is applied to the Y electrode in a line sequential manner, and the address electrode A positive pulse 29 (hereinafter referred to as an “address pulse”) of about +60 V is selectively applied to. A negative voltage of about −50 to −60 V may be applied to the Y electrode to which no scan pulse is applied. Since there is a sufficient potential difference (about 210 to 220 V) necessary for the discharge between the address electrode to which the address pulse 29 is applied and the Y electrode to which the scan pulse 28 is applied, a discharge (address discharge) occurs between the two electrodes. Arise. On the other hand, the potential difference of the scan pulse portion between the X electrode and the Y electrode is about 200 to 210 V, which is about 10 V lower than that between the address electrode, and this potential difference alone does not cause self-discharge, but triggers the address discharge (trigger ) And discharge occurs between the X electrode and the Y electrode, so that a wall charge is formed in the dielectric layer located at the intersection.
[0010]
In the last sustain discharge period (also referred to as a sustain period), a positive pulse 30 (sustain pulse) of about +180 V is alternately applied to the X electrode and the Y electrode while a positive pulse 30 ′ of about +110 V is continuously applied to the address electrode, A discharge (sustain discharge) is generated between the X and Y electrodes using the electric charge. The period of the sustain pulse 30 is the same in all subfields. Therefore, the number of sustain pulses 30 in each subfield is 1n: 2n: 4n:...: 64n: 128n, and the subfields are selected or combined according to the display gradation. As a result, 2 ^k gradations, that is, multi-gradation display from “0” to “256” (in the case of the above ratio) can be realized. However, “n” is an integer determined by the frequency of the sustain pulse 30 (hereinafter “sustain frequency”).
(3) Panel configuration and overall PDP configuration including the panel FIG. 9 is a plan view of the PDP panel. The illustrated panel 31 is a monochrome panel having a resolution of 640 × 480 for the sake of convenience. That is, address electrodes are provided from A ₁ to A _{640 for} each column of the screen, and Y electrodes and Y electrodes are provided from Y ₁ to Y ₄₈₀ and X ₁ to X ₄₈₀ for each row of the screen, respectively. A double line parallel to the address electrode is a barrier, and a region surrounded by two barriers (see a broken line) including an intersection of the address electrode, the Y electrode, and the X electrode becomes one cell.
[0011]
FIG. 10 is a configuration diagram of an AC type PDP and its driving device. 9 is a panel shown in FIG. 9, 32 is an address driver, 33 is a Y scan driver, 34 is a Y common driver, 35 is an X common driver, and 36 is a control circuit.
The control circuit 36 includes a display data control unit 36a, a panel drive control unit 36b, and the like. The display data control unit 36a temporarily stores display data (DATA) given from the outside in the frame memory 36c. The data in the frame memory 36 c is subjected to predetermined signal operations and timing processing and output to the address driver 32. The panel drive control unit 36b includes a scan driver control unit 36d, a common driver control unit 36e, and the like, and generates various timing signals based on a vertical synchronization signal (V _SYNC ) and a horizontal synchronization signal (H _SYNC ) given from the outside. Then, the data is supplied to the display data control unit 36a, the Y scan driver 33, the Y common driver 34, the X common driver 35, and the like.
[0012]
The address driver 32 generates an address pulse by using the display selection high-voltage power supply Va, and selectively applies the address pulse to the address electrodes (A ₁ , A ₂ ,..., A ₆₄₀ ) of the panel 31. The Y scan driver 33 generates a scan pulse by using the display maintaining high voltage power source Vs, and the scan pulse is generated as a Y electrode (Y ₁ , Y ₂ , Y ₃ ,..., Y ₄₈₀ ) of the panel 31. These address pulses and scan pulses are generated in an “address period” in one subfield.
[0013]
The Y common driver 34 generates a sustain pulse by using the display maintaining high voltage power supply Vs, and applies the sustain pulse to all the Y electrodes of the panel 31 simultaneously in the “sustain discharge period” in one subfield. Similarly, the X common driver 35 generates a sustain pulse and a full write pulse using the display maintaining high voltage power supply Vs, and this full write pulse is applied to all X electrodes of the panel 30 in the “reset period” in one subfield. The sustain pulse is simultaneously applied to the X electrode during the “sustain discharge period” in one subfield.
[0014]
[Problems to be solved by the invention]
A disadvantage of such a conventional plasma display device is that it cannot respond to a request for a large increase in display lines (for example, 480 lines → 768 lines).
Now, if it is a reasonable value, if one sustain time is 6 μs, the total number of sustains per frame is 510 cycles, one address time is 3 μs, and the time of one frame is 16.6 ms (1/60 field), one frame The allocation time of all the sustain periods is 6 μs × 510 cycles = 3.06 ms, so the allocation time of all reset periods and all address periods in one frame is 16.6 ms−3.06 ms = 13.54 ms. Within this time (13.54 ms), the reset period and the address period of 8 times (however, in the case of the subfield configuration of FIG. 7) must end safely. That is, one reset period and address period must be terminated at 13.54 ms ÷ 8≈1.7 ms.
[0015]
The address period is related to the display line. For example, in the case of 480 rows, 3 μs × 480 rows≈1.5 ms per subfield. Therefore, the allocation time for one reset period is 1.7 ms−1.5 ms≈200 μs, and this time is an appropriate value, so there is no problem in the case of about 480 display rows.
However, for example, when the number is increased to 768, the address period per time becomes 3 μs × 768 rows≈2.3 ms, which exceeds the reset time and the allocated time of the address period. Normal display cannot be performed.
[0016]
Note that 768 display lines correspond to the XGA standard of personal computers, and are a standard supported by most recent CRT display devices. Also, there are some that require a display line of XGA or higher, such as high-definition. Therefore, it is a technical issue that must be cleared by all means in order to aim for these replacements.
Accordingly, an object of the present invention is to substantially reduce the subfield length and respond to a request for an increase in the number of display lines by using the reduced amount.
[0017]
[Means for Solving the Problems]
According to the first aspect of the present invention, in the plasma display device in which one frame is constituted by a plurality of subfields including at least two subfields having different luminances, each of the plurality of subfields has a reset period for adjusting wall charges. The pulses applied during the reset period include a first reset pulse including a full-surface write pulse and a second reset pulse, and at least the highest luminance sub- pixel on the high luminance side of the plurality of sub-fields. In the reset period of the field, the first reset pulse and the second reset pulse are applied, and in the reset period of the low-luminance side subfield of the plurality of subfields, the first reset pulse is applied, and The second reset pulse is not applied.
[0018]
According to a second aspect of the present invention, in the first aspect, the second reset pulse includes an auxiliary pulse for preventing excessive lighting.
[0019]
According to a third aspect of the present invention, in the plasma display device in which one frame is constituted by a plurality of subfields including at least two subfields having different luminances, the low luminance side subfield of the plurality of subfields has a high luminance. Compared with at least the highest luminance subfield on the side , the pulse width in the address period is shortened.
[0020]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings. In the following description, for the sake of convenience, a plasma display device having the cell structure of FIG. 6 and the panel layout of FIG. 9 (640 columns × 480 rows) and used in the system configuration of FIG. 10 is taken as an example.
[0021]
FIG. 1 is a drive waveform diagram of each electrode, showing a first embodiment of the plasma display device according to the present invention. In FIG. 1, two representative sub-fields (A-th sub-field and B-th sub-field) are drawn consecutively for convenience of illustration, but this has no particular meaning. The intent of the illustration is in the difference in the number of sustain discharge pulses 30A and 30B in the two subfields A and B. In addition, the code | symbol of each pulse in a figure respond | corresponds to the code | symbol of FIG. 8, and the alphabet (A, B) of a code | symbol end corresponds to a subfield number.
[0022]
The number of sustain pulses 30B in the Bth subfield is smaller than the number of sustain pulses in the Ath subfield. This is because a short time (t _{1 to} t ₈ ) of the subfields SF _{1 to} SF ₈ in FIG. 7 is assigned to the Bth subfield and a long time is assigned to the Ath subfield. In short, this means that the luminance of the Bth subfield is lower than the luminance of the Ath subfield.
[0023]
Here, the operations in the reset period and address period of the two subfields A and B of high luminance and low luminance are exactly the same in the case of the conventional example at the beginning. However, according to the study by the inventors of the present application, it has been found that, in the low-luminance subfield, the severer operation management is not required as in the case of the high luminance. That is, in the case of the conventional example, a reset period and an address period suitable for the highest luminance subfield are set, and the reset period and the address period are applied to other luminance subfields. The “adapted” reset period and address period are optimal for preventing address misses and surplus lighting, and these mislighting and surplus lighting tend to occur more frequently as the brightness increases. This is because even if it is suitable for a high-luminance subfield, it is over-spec for the low-luminance subfield.
[0024]
Therefore, in the present embodiment, the length of the reset period and the address period or one of the both periods is changed according to the brightness, and more specifically, the length is reduced as the brightness becomes lower. Therefore, by shortening the length of each subfield in one field, the shortened portion is used to respond to a request to increase the number of display lines (for example, from 480 lines to 768 lines) with a margin. It is to provide useful technology that can.
[0025]
FIG. 2 is a drive waveform diagram of a high-luminance subfield shown for comparison, and corresponds to the Ath subfield of FIG. In the figure, T _{1 to} T ₄ are reset periods, T ₅ is an address period, and T ₆ is a sustain discharge period. Although the number of sustain discharge pulses 30A shown in the figure is not extremely large, this is for the convenience of illustration and is actually a number corresponding to the maximum luminance. This is because, as described above, the reset period and address period suitable for the subfield with the highest luminance must be used to prevent address misses and excessive lighting. The full-surface writing pulse 20A and the remaining point erasing pulses 23A to 25A shown in the figure are set to voltages and pulse widths suitable for the sub-field with the highest luminance. Similarly, the pulse interval is set to a value suitable for the subfield with the highest luminance. Therefore, the drive waveform of FIG. 2 corresponds to the conventional drive waveform (FIG. 8).
[0026]
On the other hand, the drive waveform of FIG. 3 is a low-luminance subfield, and is a drive waveform specific to this embodiment, that is, a drive waveform corresponding to the Bth subfield of FIG. Compared with FIG. 2, it is needless to say that the number of sustain discharge pulses 30B is small because of low luminance, but that T ₄ is deleted from the reset period and that T _{3 in the} reset period is shortened. There are characteristic differences. T _{4 in the} reset period is a generation period of five auxiliary pulses (see pulses 22 to 26 in FIG. 1) for preventing excessive lighting. In the case of a low-intensity subfield, the display quality is hardly affected even if these auxiliary pulses are eliminated. This is because even if an excessively lit cell is generated, it is difficult to visually recognize because of low luminance. Further, T ₃ is a neutralization period of the discharge charge by the entire writing pulse 21B. The length of the neutralization period must be increased as the number of sustain discharge pulses in the immediately preceding subfield increases, that is, as the brightness of the immediately preceding subfield increases. This is because the amount of wall charge accumulated in the immediately preceding sustain discharge period is large, and the amount of discharge charge due to the full-surface write pulse 21B in the next subfield is also increased .
[0027]
Here, FIG. 2 and FIG. 3 are compared by applying actual values. Where appropriate, T ₁ (interruption period) in FIG. 2 is 50 μs, T ₂ is 10 μs, T ₃ is 50 μs, and T ₄ is 70 μs. The other values are the same as those used in “Problems to be solved by the invention” at the beginning. On the other hand, in the case of FIG. 3, but T ₁ and T ₅ are the same as FIG. 2, T ₄ Since there is no (−70 μs) , the entire subfield has a shortening effect of at least 70 μs. Further, since the low luminance does not stand out even if some address miss occurs, the pulse width of the address pulse 29B in the address period can be shortened. For example, if the pulse width 3 μs in the case of high luminance is shortened to 2.5 μs, it can be reduced by −0.5 μs per pulse. Therefore, since the entire T ₅ is −0.5 μs × number of rows, for example, if it is 480 rows, the reduction is as much as −240 μs, and the total of the reset period is −90 μs, and the effect of shortening as much as −330 μs per subfield is obtained. be able to.
[0028]
Incidentally, the reason why the address pulse can be shortened is as follows. (1) In the subfield of low luminance, even if there are some display errors, it is not noticeable because of the low luminance. Since the priming effect due to the discharge of the full-surface write pulse in the subfield remains, and the priming effect due to the discharge of the full-surface write pulse in the self-subfield is added to the residual effect, the write address that does not hinder even a short address pulse It is possible to discharge.
[0029]
Alternatively, the length of the interruption period before full writing may be controlled according to the number of sustain discharges in the immediately preceding subfield, that is, the luminance.
FIG. 4 is a drive waveform diagram, and a pulse with “−1” as a subscript is in the immediately preceding subfield. In this figure, since there is one sustain pulse 30B- ₁ in the immediately preceding subfield, the wall charges due to the sustain discharge pulse 30B- ₁ are not sufficiently formed. For this reason, even if the full write pulse 22B is immediately generated with the interruption period (T ₁ ) set to zero, a strong discharge that causes inconvenience does not occur. Alternatively, as shown in FIG. 5, a corresponding effect can be obtained by shortening the interruption period (T ₁ ) without making it zero.
[0030]
【The invention's effect】
According to the present invention, it is possible to substantially reduce the subfield length, and it is possible to respond to a request for increasing the number of display lines by using the reduced amount.
[Brief description of the drawings]
FIG. 1 is a driving waveform diagram of two subfields of high luminance and low luminance according to an embodiment.
FIG. 2 is a drive waveform diagram of a high-luminance subfield according to an embodiment.
FIG. 3 is a drive waveform diagram (reset and address period control) of a low-luminance subfield according to an embodiment;
FIG. 4 is a drive waveform diagram (control of an interruption period) of a low-luminance subfield according to one embodiment.
FIG. 5 is a drive waveform diagram (controlling the width of a full write pulse) of a low-luminance subfield according to one embodiment.
FIG. 6 is a pixel structure diagram of a plasma display panel.
FIG. 7 is a subfield frame structure diagram.
FIG. 8 is a conventional drive waveform diagram.
FIG. 9 is a layout diagram of a plasma display panel.
FIG. 10 is a system configuration diagram of the plasma display device.
[Explanation of symbols]
30, 30A, 30B: sustain pulse SF ₁ - SF _8: subfields T ₁ through T _4: reset period T _5: address period T _6: sustain discharge period

Claims (3)

In a plasma display device in which one frame is constituted by a plurality of subfields including at least two subfields having different luminances,
Each of the plurality of subfields has a reset period for adjusting wall charge;
The pulses applied during the reset period include a first reset pulse including a full-surface write pulse and a second reset pulse,
In the reset period of at least the highest luminance subfield on the high luminance side of the plurality of subfields, the first reset pulse and the second reset pulse are applied,
The plasma display apparatus, wherein the first reset pulse is applied and the second reset pulse is not applied during a reset period of a low-luminance subfield of the plurality of subfields.   The plasma display apparatus of claim 1, wherein the second reset pulse includes an auxiliary pulse for preventing excessive lighting. In a plasma display device in which one frame is constituted by a plurality of subfields including at least two subfields having different luminances,
A plasma display apparatus, wherein a pulse width in an address period is shortened in a subfield on the low luminance side of the plurality of subfields as compared to at least the highest luminance subfield on the high luminance side .

Images