JP2756053B2 - AC Drive Type Plasma Display Panel Driving Method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an AC-driven plasma display panel driving method.

[0002]

2. Description of the Related Art FIG. 3 shows an overall configuration of an AC drive type plasma display device.

[0003] AC driven plasma display panel 1
0 denotes scanning electrodes Y1 to Y parallel to each other on one surface thereof.
n and a common electrode X are provided, and address electrodes A1 to An are provided on a facing surface in a direction perpendicular to these electrodes.
The common electrode X is provided in close proximity to each of the scanning electrodes Y1 to Yn, and has one end commonly connected to each other.

FIG. 4 shows a cross-sectional structure of a cell Cij in the i-th row and the j-th column, which is one pixel. Common electrode X and scan electrode Y
i is formed on a glass substrate 11, on which a dielectric layer 12 for insulating against a discharge space 17 is adhered, and further thereon, a MgO protective film 13 is adhered. On the other hand, the address electrodes Ai are formed on a glass substrate 14 arranged opposite to the glass substrate 11, and a phosphor 15
Is attached. Further, on the glass substrate 14 and the address electrodes Ai, separators 16 for preventing color mixing between cells and maintaining a discharge gap are formed at pixel boundaries.
Ne + Xe Penning gas is sealed in the discharge space 17 between the MgO protective film 13 and the phosphor 15.

In FIG. 3, a common electrode X is an X driver 2
0, the scanning electrodes Y1 to Yn are connected to the output terminal of the Y driver 30, and the address electrodes A1 to Am are connected to the output terminal of the address driver 40. These X driver 20, Y driver 30, and address driver 40 are controlled by control signals from a control circuit 50,
The control circuit 50 generates this control signal based on the display data D from the outside, a clock CLK indicating the read timing of the display data D, the horizontal synchronization signal HS, and the vertical synchronization signal VS.

FIG. 5 is a voltage waveform diagram showing one example of a method of driving an AC drive type plasma display panel, and shows one subfield. This one subfield is divided into a full address period, a full erase period, an address period, and a sustain discharge period.

When performing 2 ^N gray scale display, one frame is set to N
, And each subfield is composed of the four periods, and the ratio of the sustain discharge periods in the ^{first to Nth} subfields is 2 ⁰ : 2 ¹ :...: 2 ^N−2 : 2 ^N-1 (Japanese Patent Application No. 2-331589). FIG. 6 shows the configuration of each subfield of one frame when N = 8.

[0008]

However, since the entire writing and erasing are performed in each subfield in one frame, even when displaying the entire erasing state, discharge emission is performed four times in this driving waveform in each subfield. , For example N =
In the case of No. 8, discharge light emission was performed 32 times in one frame, so that even when the entire image was erased, that is, when the entire image was displayed in black, the image became gray, which hindered high-quality display.

An object of the present invention is to provide an AC-driven plasma display panel driving method capable of improving display quality in view of such problems.

[0010]

Means and operation for solving the problems] of claim 1
In the invention, one frame is composed of a plurality of subfields
And each subfield has a pixel to be turned on.
Period during which wall charges are generated, and the address period
Discharge period in which the pixels selectively written in step are discharged and emitted.
To drive a plasma display panel with
Current Driven Plasma Display Panel Driving Method
Therefore, the one frame is stored in all pixels before the address period.
To generate a wall charge and accumulate in the pixel
Sub-flag that performs both erase discharge and erase
Field and before the address period,
Without performing a write discharge to generate
For erasing discharge to erase wall charges accumulated in
And subfields. In the present invention,
Full surface only in one subfield in one frame
Since writing is in progress, when displaying the display of all erase,
For example, when N = 8, 4 + 3 × 7 = 25 discharges in one frame
Emits light, the number of times of discharge emission at the time of entire erasure is 32 times
And the display quality is improved.

According to the invention of claim 2, in claim 1,
The erasing discharge interrupts a pulse during the progress of the discharge.
It is characterized by narrow width erasure.

According to a third aspect of the present invention, in the first aspect,
The erasing discharge is a small discharge at a voltage lower than the sustain voltage.
It is characterized by a large erasure that occurs.

According to the fourth aspect of the present invention, any one of the first to third aspects is provided.
In one of the cases, a wall charge is generated in all the pixels.
The subfield in which the write discharge is performed is the one field.
The first subfield of the frame and the other subfields.
The erase discharge without performing the write discharge.
It is a subfield to be implemented.

[0014]

[0015]

[0016]

An embodiment of the present invention will be described below with reference to the drawings.

For example, when displaying 256 gradations, one frame is composed of first to eighth subfields as shown in FIG. 1 corresponding to FIG. The first subfield includes a full address period, a full erase period, an address period, and a sustain discharge period. Each of the second to eighth subfields is
The first sub-field excludes the entire address period, that is, the entire erase period, the address period, and the sustain discharge period.

The ratio of each of the sustain discharge periods t1 to t8 in the first to eighth subfields is the same as in FIG. 6, and t1: t2: t3:...: T7: t8 = 1: 2: 4: 8: 16: 32: 64: 128.

One frame time is equal to that of FIG.
/ 60 seconds. Therefore, in the present embodiment, it can be used in another period only for the period of (the entire writing period) × 7 compared with the case of FIG. 6, and the pulse width can be made wider than that of FIG.

FIG. 2 shows waveforms of voltages applied to the address electrodes A1 to A480, the common electrode X, and the scan electrodes Y1 to Y480 in the first and second subfields. The voltage waveform of the first subfield is the same as that of FIG. 5, and will be described below. Note that the subfield division signal in the figure is generated by the control circuit 50 in FIG.

[0021] (1) the entire surface writing period first the entire surface writing period, scan electrodes Y1~Yn is the ground level GND, the common electrode X in this state, is to a high write voltage V _W than the discharge starting voltage V _f (The entire writing pulse), the common electrode X and the scanning electrodes Y1 to Yn.
, Ie, in all the cells, the address discharge is performed.
As the discharge proceeds, negative wall charges are accumulated in the dielectric layer 12 on the common electrode X electrode, and positive wall charges are accumulated in the dielectric layer 12 on the scan electrodes Y1 to Yn. Since the wall charges reduce the voltage in the discharge space, the discharge ends in about 1 μs.

Next, the scanning electrodes Y1 to Yn are set to the sustain voltage V _S lower than the discharge starting voltage _Vf , and the common electrode X is set to the ground level GND (sustain pulse). Then, a sustain discharge is performed between the common electrode X and the scan electrodes Y1 to Yn. This allows
Positive wall charges are accumulated in the dielectric layer 12 on the common electrode X electrode, and negative wall charges are accumulated in the dielectric layer 12 on the scan electrodes Y1 to Yn, and the discharge ends. The sustain pulse stabilizes the wall charges.

(2) Entire erasing period Next, the common electrode X is set to the sustain voltage V _S , and the scanning electrode Y 1
ＹYn are set to the ground level GND (entire erasing pulse), an erasing discharge occurs, and wall charges are neutralized and erased. This erasing method includes a narrow erasing method in which a pulse is interrupted at the stage of the progress of discharge, and a wide erasing method in which a minute discharge is generated at a voltage lower than the sustain voltage V _S.

(3) Address Period Next, writing of display data is performed line-sequentially. That is, first, the scanning electrode Y1 is set to the ground level GND and selected, the voltage Va is applied to the address electrode corresponding to the cell to be turned on in the first display row (address pulse), and the address discharge occurs between both electrodes. And a wall charge is generated. Hereinafter, the same operation as described above is performed on the second to n-th display rows in this order.

(4) Sustain discharge period Next, the common electrode X is set to the ground level GND (sustain pulse) while all of the scan electrodes Y1 to Yn are at the sustain voltage V _S , and a write discharge is performed in the address period in the cell. The wall charges are added, and a sustain discharge is performed. Next, the scan electrodes Y1~Y while returning the common electrode X in the sustain voltage V _S
n are both set to the ground level GND (sustain pulse),
Wall charges are added in the cells that have performed the address discharge in the address period, and sustain discharge is performed. Hereinafter, such an operation is alternately repeated. That is, an AC sustaining pulse is supplied between the common electrode X and the scanning electrodes Y1 to Yn, and an image is displayed.

In the second sub-field, the entire address period in the first sub-field is omitted, and the sustain discharge period is twice as long as that in the first sub-field. Others are the same as the first subfield.

In the entire erasing period of the second subfield, the wall charges generated by the immediately preceding sustain discharge disappear by the entire erasing discharge. The entire erasing period from the third subfield onward is the same as in the second subfield.

In this embodiment, since the entire writing is performed only in the first subfield in one frame,
In the case of performing display of entire erasure, 4 + 3 × 7 =
Discharge emission is performed 25 times, and the number of times of discharge emission is smaller than the conventional 32 times, and the display quality is improved. The above embodiment
, The common electrode may be divided into a plurality of sets.
No.

[0029]

As described above, in the method of driving the AC drive type plasma display panel according to the present invention, the entire writing is performed only in one subfield in one frame. In addition, the number of times of discharge light emission is reduced as compared with the related art, and an effect of improving display quality is achieved.

[Brief description of the drawings]

FIG. 1 is a diagram showing the configuration of each subfield of one frame when displaying 256 gradations according to an embodiment of the present invention.

FIG. 2 is a diagram showing voltage waveforms applied to respective electrodes in first and second subfields.

FIG. 3 is a schematic configuration diagram of an AC drive type plasma display device.

FIG. 4 is a cross-sectional configuration diagram of the cell of FIG.

FIG. 5 is a diagram of a voltage waveform applied to each electrode in one subfield according to a conventional example.

FIG. 6 is a diagram showing the configuration of each subfield of one frame when displaying 256 gradations according to the conventional example.

[Description of Symbols] A1 to Am Address electrode X Common electrode Y1 to Yn Scanning electrode

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-5-241528 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) G09G 3/28

Claims (4)

(57) [Claims] 1. One frame is composed of a plurality of subfields.
Make up, each subfield try to light
An address period in which a pixel generates wall charges;
Sustain discharge to discharge and emit light on the pixels selectively written in the period
Drive a plasma display panel with
AC driving type plasma display panel driving method
And the one frame generates wall charges in all pixels before the address period.
Erase write discharge and wall charges accumulated in pixels
Before the address period , a sub-field in which erasing discharge is performed, and wall charges are generated in all the pixels.
Without having to perform a write discharge
Subfield for erasing discharge to erase wall charges
If, AC-driven plasma display panel driving method, which comprises a. 2. The erasing discharge according to claim 1, wherein a pulse
A narrow width erasure that interrupts the process
1. AC drive type plasma display panel driving method described in 1.
Law. 3. The erasing discharge according to claim 1, wherein the erasing discharge has a voltage lower than a sustain voltage.
It is characterized by being a large erasure that generates a minute discharge at
An AC-driven plasma display panel according to claim 1,
Flannel driving method. 4. A writing method for generating wall charges in all the pixels.
The sub-field for performing the embedded discharge is the one-frame
Is the first subfield of the other subfield
Performs an erase discharge without performing the write discharge.
2. The subfield according to claim 1, wherein
3. The AC-driven plasma display according to any one of
Play panel driving method.