JP2002132209A - Driving method for plasma display panel - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a driving method by which stable write-in can be obtained in an AC type plasma display panel. SOLUTION: In the plasma display panel in which plural opposing first and second display electrodes and data electrodes arranged so as to be made orthogonal to the first display electrodes are provided between one pair of parallel substrates and writing operation is performed by applying voltages among the first display electrodes and the data electrodes, the plasma display panel is driven by varying pulse widths or voltage values of voltages to be applied at the time of the writing operation among fields or among sub-fields or in sub-fields.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for driving an AC type plasma display panel used for displaying an image on a television receiver, a computer terminal or the like, and more particularly, to a plasma for facilitating data writing and realizing a high quality panel. The present invention relates to a display panel driving method.

[0002]

2. Description of the Related Art FIG. 1 is a partial perspective view of a conventional AC type plasma display panel (hereinafter referred to as a panel).
As shown in FIG. 1, on a front panel glass 21, a first display electrode (scanning electrode 22) and a second display electrode (sustain electrode 23) covered with a dielectric film 24 and a protective film 25 are paired. And are provided in parallel with each other. A data electrode 27 covered with a dielectric film 33 is provided on the back panel glass 26, and a partition wall 28 is provided on the dielectric film 33 between the data electrodes 27 in parallel with the data electrode 27. Phosphors 30, 31, and 32 are provided from the surface of the dielectric film 33 to the side surface of the partition wall 28, and the scanning electrodes 2 are provided.
2 and front panel glass 21 and back panel glass 2 so that sustain electrode 23 and data electrode 27 are orthogonal to each other.
6 are disposed to face each other with the discharge space 29 interposed therebetween.
The discharge space 29 is filled with at least one rare gas of helium, neon, argon, and xenon as a discharge gas, and is sandwiched between two adjacent partition walls 28.
A discharge cell is formed in the discharge space at the intersection of the scan electrode 22 and the sustain electrode 23 that form a pair facing the data electrode 27.

Next, FIG. 2 shows an electrode arrangement diagram of this panel. As shown in FIG. 2, the electrode arrangement of this panel is m × n
And m rows of data electrodes D1 to Dm are arranged in the column direction, and n rows of scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SU in the row direction.
Sn is arranged. Further, the discharge cell shown in FIG. 1 is configured as shown in FIG.

FIG. 3 shows an operation drive timing chart of a conventional drive method for driving this panel.

As shown in FIG. 3, one field period is
The first to n-th subfields having an initialization period, a writing period, a sustaining period, and an erasing period,
Thus, gradation display is performed.

First, an initialization pulse is applied to the scan electrodes SCN1 to SCNn shown in FIG. 2 to initialize wall charges in the discharge cells of the panel.

Next, in order to perform the display of the first row in the writing period, a scan pulse voltage is applied to the scan electrodes SCN1 of the first row, and the data electrode groups D1 to D1 corresponding to the discharge cells are applied.
Dm, a write pulse voltage is applied to the data electrode group D1.
A write discharge is caused between .about.Dm and the scan electrode SCN1 in the first row, wall charges are accumulated on the surface of the dielectric layer, and a write operation in the first row is performed.

The above-described operations are sequentially performed, and the writing operation of the Nth row is completed, and a latent image for one screen is written.

Next, in the sustain period, the data electrode group D1
To Dm are grounded, and all the sustain electrode groups SUS1 to SU
By applying a sustain pulse voltage to Sn, subsequently applying a sustain pulse voltage to all of the scan electrode groups SCN1 to SCNn, and continuing this operation alternately to apply the sustain pulse voltage, writing is performed in the write period. In the discharge cell where the operation has been performed, the light emission of the sustain discharge is continuously performed, and the screen is displayed.

Thereafter, in the erasing period, a discharge is generated by applying a narrow erasing pulse, and the wall charges disappear, so that an erasing operation is performed.

As described above, in the conventional driving method of the PDP,
Image display is performed by a series of driving methods including an initialization period, a writing period, a sustaining period, and an erasing period.

[0012]

In the conventional driving method,
Since the write pulse voltage and the pulse width of the voltage applied during the write period were fixed between all fields, between all subfields, and within subfields, the discharge probability was low even for the discharge cells with low discharge probability or the same discharge cell. However, there is a problem that image quality is deteriorated in a low period of time, such as image flickering or non-lighting.

As a method for solving this problem, it has been attempted to lengthen all the pulse widths or set all the pulse application voltages to be high. However, there is a problem that the occupation time becomes longer and the gradation display is restricted. Further, when the pulse application voltage is increased, there is a problem that erroneous discharge such as self-erasure occurs in a cell having a low discharge start voltage.

The present invention solves the above-mentioned conventional problems, and provides a driving method capable of shortening the occupation time of a writing period as much as possible, suppressing power consumption at the time of addressing as much as possible, and obtaining a stable writing.

[0015]

A plurality of opposing first and second display electrodes are provided between a pair of parallel substrates, and a data electrode disposed so as to be orthogonal to the first display electrode. In a plasma display panel in which a voltage is applied between the first display electrode and the data electrode to perform a writing operation, the voltage is applied at the time of writing between lines, between subfields, or between lines having a low discharge probability in a field. How to increase the voltage pulse width, or
A method of increasing the applied voltage or shortening the pulse width of the voltage applied at the time of writing on a line having a high probability of discharging or lowering the applied voltage is used.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of a PDP panel used in the present invention is basically the same as that of a conventional PDP panel. Less than,
An embodiment of the present invention will be described with reference to FIGS.

(Embodiment 1) Claims 1 and 2 of the present invention
The driving method of the AC type plasma display panel described in 1 above will be described. FIG. 4 shows an operation drive timing chart. One field period includes first to n-th subfields having an initialization period, a writing period, a sustaining period, and an erasing period. The pulse width at the time of writing is set to be long on a line having a low discharge probability in one subfield or short on a line having a high discharge probability. By increasing the pulse width, the formation of wall charges during that period is completed, the probability of discharge increases, and stable writing can be obtained. In cells with high discharge probability,
By shortening the pulse width, the writing time can be reduced. For a line with a high discharge probability (95% or more), the pulse width is 300 ns to 3 μs, and a line with a low discharge probability (70%
In the following line, stable writing is realized by setting the pulse width to 500 ns to 5 μs in the line and 500 ns to 3 μs in the middle line. More preferably, in a line having a high discharge probability, the pulse width is set to 300 ns to 1 μm.
s, the pulse width is 2 μs to 5
μs, and in the middle line, 1 μs to 2 μs is desirable.

In particular, stable driving can be realized by applying to a place where erroneous discharge or non-light is likely to occur in a line such as a dark line, a bright line, or a color unevenness of a phosphor.

(Embodiment 2) Claims 3 and 4 of the present invention
The driving method of the AC type plasma display panel described in 1 above will be described. FIG. 5 shows an operation drive timing chart. The applied voltage at the time of writing is set to be high in a line having a low discharge probability or low in a line having a high discharge probability in one subfield. By increasing the applied voltage, the probability of discharge increases, and stable writing can be obtained. In a cell having a high discharge probability, erroneous discharge such as self-erasure and power consumption can be reduced by lowering the applied voltage. High discharge probability (95% or more)
In the line, the applied voltage is 20 V to 70 V, and in the line with a low discharge probability (70% or less), the applied voltage is 40 V to 90 V.
V, in the middle line, the applied voltage is 30V-80V
By doing so, stable writing is realized. More preferably, in a line having a high discharge probability, the applied voltage is 30 V
ラ イ ン 60V, the line with low discharge probability has an applied voltage of 50
V to 80 V, the applied voltage is 40 V
~ 70V is desirable.

In the subfield, the first embodiment
The same effect can be obtained by combining with a pulse width as shown in FIG.

In particular, stable driving can be realized by applying the present invention to a place where erroneous discharge or non-light is likely to occur in a line such as a dark line, a bright line, or a color unevenness of a phosphor.

(Embodiment 3) Claims 5 and 7 of the present invention
, 9, 11 and 13 will be described. FIG.
The operation drive timing chart is shown in FIG. An example of a subfield in which the immediately preceding subfield is lit and a subfield that is not lit are shown as (m) subfield and (m + 1) subfield, respectively. The lit cell has a shorter pulse width because the discharge probability increases due to the influence of priming and the like, and the unlit cell has a longer pulse width. In the figure, the applied voltage and the pulse width in the sub-field are all the same, but the pulse width can be changed also in the sub-field as in the first embodiment, or the pulse width can be changed in the sub-field as in the second embodiment. Changing the applied voltage at the same time has the same effect.

As an example of a subfield having an initialization period and a subfield having no initialization period, (m + 1)
The subfield is shown as (m + 2) subfield. Here, the pulse width of the applied voltage in the subfield without initialization is long, but the amount of wall charge accumulated on the electrode is determined by the potential of the falling part of the initialization voltage, and the cell Since the voltage inside is determined and the discharge probability can be adjusted, for the subfield with initialization,
It can be relatively short. This is also effective in combination with the first and second embodiments, similarly to the above.

As an example of a subfield having an erasing period and a subfield having no erasing period in the immediately preceding subfield, (m + 1) subfield and (m + 3) subfield are shown, respectively. In the (m + 3) subfield, an example in combination with the first embodiment is described. Since the discharge probability changes depending on the pulse width of the erasing period, the presence or absence of the subsequent initialization period, and the potential of the falling portion of the applied voltage during the initialization period, the pulse width of the applied voltage is
Depending on the setting, it can be made longer or shorter. This is also effective in combination with the first and second embodiments, similarly to the above.

In particular, the present invention can be applied to a period in which erroneous discharge or no light is likely to occur in gradation display.

(Embodiment 4) Claims 6 and 8 of the present invention
, 10, 12 and 14 will be described. FIG. 7 shows an operation drive timing chart. An example of a subfield in which the immediately preceding subfield is lit and a subfield that is not lit are shown as (m) subfield and (m + 1) subfield, respectively. The applied voltage of the lit cell is low because the probability of discharge increases due to the influence of priming and the like, and the unlit cell is high. In the figure, the applied voltage and the pulse width in the subfield are all the same, but the pulse width can be changed also in the subfield as in the first embodiment.
The same effect can be obtained by changing the applied voltage within the subfield as in the second embodiment, or by combining the same with the third embodiment.

As an example of a subfield having an initialization period and a subfield having no initialization period, (m + 1)
The subfield is shown as (m + 2) subfield. Here, the applied voltage of the subfield without initialization is set high, but the potential of the falling portion of the initialization voltage determines the amount of wall charges accumulated on the electrode, and thereby the voltage in the cell. Is determined, and the discharge probability can be adjusted. Therefore, it is possible to set a relatively low value for a subfield having initialization. This is also effective in combination with the first, second, and third embodiments similarly to the above.

As an example of a subfield having an erasing period and a subfield having no erasing period in the immediately preceding subfield, (m + 1) subfield and (m + 3) subfield are shown, respectively. In the (m + 3) subfield, an example in combination with the first embodiment is described. Since the discharge probability changes depending on the pulse width of the erase period, the presence or absence of the initialization period, and the potential of the falling portion of the applied voltage in the initialization period, the applied voltage at the time of writing is set higher by the setting. It can be lower or lower. This is also effective in combination with the first, second, and third embodiments similarly to the above.

In particular, the present invention can be applied to a period in which erroneous discharge or no light is likely to occur in gradation display.

(Embodiment 5) A method of driving an AC type plasma display panel according to claims 15 and 16 of the present invention will be described. Since the discharge probability changes between the fields depending on the low gradation latent image and the high gradation latent image, it is effective to change the applied voltage and the pulse width at the time of writing. This is also effective in combination with the first, second, third, and fourth embodiments similarly to the above.

[0031]

As described above, according to the present invention, the discharge probability at the time of writing discharge can be improved with the optimum writing time and the optimum power consumption, and the writing defect can be remarkably improved to realize stable driving.

[Brief description of the drawings]

FIG. 1 is an AC type plasma display panel (PDP).
Perspective view showing the outline of

FIG. 2 is an electrode arrangement diagram

FIG. 3 is a timing chart of a conventional driving waveform.

FIG. 4 is an operation drive timing chart showing a method for driving an AC plasma display panel according to a first embodiment of the present invention;

FIG. 5 is an operation drive timing chart showing a method for driving an AC plasma display panel according to a second embodiment of the present invention;

FIG. 6 is an operation drive timing chart showing a method for driving an AC plasma display panel according to a third embodiment of the present invention;

FIG. 7 is an operation drive timing chart showing a method of driving an AC plasma display panel according to a fourth embodiment of the present invention.

[Explanation of symbols]

 FP front panel BP back panel 21 front panel glass 22 scan electrode 23 sustain electrode 24 dielectric film 25 protective film 26 back panel glass 27 data electrode 28 partition wall 29 discharge space 30 phosphor (R) 31 phosphor (G) 32 phosphor (B) 33 dielectric film

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) H04N 5/66 101 G09G 3/28 H (72) Inventor Shigeyuki Okumura 1006 Kazuma, Kazuma, Kazuma, Osaka Matsushita Electric Industrial Co., Ltd. (72) Inventor Ryuji Kurata 1006 Kazuma, Kazuma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.F-term (reference)

Claims (20)

[Claims] A plurality of first and second display electrodes opposed to each other between a pair of parallel substrates; and a data electrode arranged to be orthogonal to the first display electrodes. In a plasma display panel performing a writing operation by applying a voltage between the display electrode and the data electrode, the pulse width of the voltage applied at the time of writing is increased in a line having a low discharge probability in the subfield, or A method for driving a plasma display panel, comprising shortening a line with a high probability of discharge in the panel. A plurality of first and second display electrodes facing each other between a pair of parallel substrates; and a data electrode disposed so as to be orthogonal to the first display electrodes. In a plasma display panel performing a writing operation by applying a voltage between the display electrode and the data electrode, the voltage applied at the time of writing is increased in a line having a low discharge probability in the subfield, or the discharge in the subfield is increased. A method for driving a plasma display panel, characterized in that a line having a high probability is lowered. A plurality of first and second display electrodes opposed to each other between a pair of parallel substrates; and a data electrode disposed so as to be orthogonal to the first display electrode. A plasma display panel performing a write operation by applying a voltage between the display electrode and the data electrode, wherein the pulse width of the voltage applied at the time of writing is changed between subfields. . 4. A method comprising: providing a plurality of first and second display electrodes facing each other between a pair of parallel substrates; and a data electrode disposed to be orthogonal to the first display electrodes. A method for driving a plasma display panel, comprising: applying a voltage between a display electrode and a data electrode to perform a writing operation, wherein the voltage applied during writing is changed between subfields. 5. A semiconductor device comprising: a plurality of first and second display electrodes opposed to each other between a pair of parallel substrates; and a data electrode arranged to be orthogonal to the first display electrodes. In a plasma display panel performing a write operation by applying a voltage between the display electrode and the data electrode, the pulse width of the voltage applied at the time of writing is changed between a subfield with an initialization period and a subfield without an initialization period. Characteristic driving method of a plasma display panel. 6. A method according to claim 1, further comprising: providing a plurality of opposed first and second display electrodes between a pair of parallel substrates; and a data electrode arranged to be orthogonal to the first display electrodes. In a plasma display panel performing a writing operation by applying a voltage between the display electrode and the data electrode, the voltage applied at the time of writing is changed between a subfield with an initialization period and a subfield without an initialization period. A method for driving a plasma display panel. 7. A semiconductor device comprising: a plurality of first and second display electrodes facing each other between a pair of parallel substrates; and a data electrode arranged to be orthogonal to the first display electrodes. In the plasma display panel performing a write operation by applying a voltage between the display electrode and the data electrode, the pulse width of the voltage applied at the time of writing is set to a subfield having an erasing period in the immediately preceding subfield and a subfield having no erasing period. A method for driving a plasma display panel, characterized in that the driving method is changed between the two. 8. A semiconductor device comprising: a plurality of first and second display electrodes facing each other between a pair of parallel substrates; and a data electrode arranged to be orthogonal to the first display electrodes. In a plasma display panel performing a write operation by applying a voltage between the display electrode and the data electrode, the voltage applied at the time of writing is changed between a subfield having an erasing period in the immediately preceding subfield and a subfield having no erasing period. A method for driving a plasma display panel. 9. A semiconductor device comprising: a plurality of first and second display electrodes opposed to each other between a pair of parallel substrates; and a data electrode arranged to be orthogonal to the first display electrodes. In a plasma display panel in which a voltage is applied between a display electrode and a data electrode to perform a writing operation, the pulse width of the voltage applied at the time of writing is set to be the same as the subfield in which the immediately preceding subfield was lit. A method for driving a plasma display panel, wherein the method changes between subfields. 10. A semiconductor device comprising: a plurality of first and second display electrodes facing each other between a pair of parallel substrates; and a data electrode arranged to be orthogonal to the first display electrodes. In a plasma display panel performing a write operation by applying a voltage between the display electrode and the data electrode, the voltage applied at the time of writing is set to a subfield where the previous subfield was turned on and a subfield which was not turned on. A method for driving a plasma display panel, characterized in that the driving method is changed between the two. 11. The method according to claim 3, wherein a pulse width of a voltage applied at the time of writing is increased on a line having a low discharge probability in a subfield or is shortened on a line having a high discharge probability in a subfield. 11. The method for driving a plasma display panel according to any one of items 10 to 10. 12. The method according to claim 3, wherein a voltage applied at the time of writing is increased on a line having a low discharge probability in a subfield, or is decreased on a line having a high discharge probability in a subfield. A driving method of the plasma display panel according to any one of the above. 13. A semiconductor device comprising: a plurality of opposed first and second display electrodes provided between a pair of parallel substrates; and a data electrode disposed so as to be orthogonal to the first display electrodes. A method of driving a plasma display panel, comprising: applying a voltage between a display electrode and a data electrode to perform a writing operation, wherein the pulse width of the voltage applied at the time of writing is changed between fields. 14. A semiconductor device comprising: a plurality of first and second display electrodes facing each other between a pair of parallel substrates; and a data electrode disposed to be orthogonal to the first display electrodes. A method for driving a plasma display panel, comprising: applying a voltage between a display electrode and a data electrode to perform a writing operation, wherein the voltage applied during writing is changed between fields. 15. The method according to claim 13, wherein a pulse width of a voltage applied at the time of writing is changed between subfields. 16. The method according to claim 13, wherein a voltage applied at the time of writing is changed between subfields. 17. The method according to claim 15, wherein a pulse width of a voltage applied at the time of writing is lengthened on a line having a low discharge probability in a subfield, or shortened on a line having a high discharge probability in the subfield. Or 16
The method for driving a plasma display panel according to any one of the above. 18. The method according to claim 15, wherein the voltage applied at the time of writing is increased on a line having a low discharge probability in a subfield, or is decreased on a line having a high discharge probability in a subfield. A driving method of the plasma display panel according to any one of the above. 19. The method of driving a plasma display panel according to claim 1, wherein a pulse width of a voltage applied at the time of writing is set to 500 ns to 5 μs. 20. A voltage applied at the time of writing is 10 V to
The voltage is set to 90 V.
19. The method for driving a plasma display panel according to any one of items 18.