KR100484113B1 - Method of driving a plasma display panel - Google Patents

Abstract

In the method of driving a plasma display panel according to the present invention, a plasma display panel in which discharge cells are formed in an area where address electrode lines intersect with respect to sustain electrode line pairs in which first and second sustain electrode lines are alternately arranged side by side For a reset cycle for initializing all discharge cells, an address cycle for forming wall charges in selected discharge cells, and a sustain discharge cycle for maintaining discharge for gray scale display in discharge cells in which wall charges are formed in the address cycle, It is provided. When the two levels of voltages applied to the first and second sustain electrode lines are mutually changed in the sustain discharge period in which two different levels of voltage are alternately applied to the first and second sustain electrode lines. The high level voltage of the second storage electrode lines is changed to a low level voltage after the low level voltage of the first storage electrode lines is changed to a high level voltage. According to the present invention, the self-erase discharge generated when the sustain pulses applied to the pair of sustain electrodes cross each other in the sustain discharge cycle can be suppressed.

Description

Method of driving a plasma display panel

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of driving a plasma display panel, and more particularly, to improve a waveform of a sustain pulse applied to a sustain electrode in a sustain discharge cycle, thereby eliminating self-erasing generated when a pair of sustain electrodes cross each other. A driving method of a plasma display panel that can suppress discharge.

1 shows a structure of a conventional three-electrode surface discharge plasma display panel. FIG. 2 shows an example of one discharge cell of the panel of FIG. 1.

Referring to the drawings, between the front and rear glass substrates 10 and 13 of the conventional surface discharge plasma display panel 1, the address electrode lines A _R1 , A _G1 , ..., A _Gm , A _Bm ), Dielectric layers 11 and 15, Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), fluorescent layer 16, partition wall 17 ) And a magnesium monoxide (MgO) layer 12 as a protective layer.

The address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is entirely applied in front of the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . These partitions 17 function to partition the discharge area of each discharge cell and to prevent optical cross talk between each discharge cell. The fluorescent layer 16 is formed between the partition walls 17.

The X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) are the address electrode lines (A _R1 , A _G1 , ..., A _Gm , A _Bm ) is formed in a predetermined pattern on the back of the front glass substrate 10 to be orthogonal to each other. Each intersection sets a corresponding discharge cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) is a transparent electrode line of a transparent conductive material such as indium tin oxide (ITO) or the like (FIG. 2). X _na , Y _na ) and a metal electrode line (X _nb , Y _nb of FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

As a driving method of the plasma display panel 1 having the structure described above, an address-display separation driving method which is mainly used is disclosed in US Pat.

FIG. 3 illustrates a conventional address-display separation driving method for Y electrode lines of the plasma display panel of FIG. 1.

Referring to the drawing, a unit frame is divided into eight subfields SF1, ..., SF8 to realize time division gray scale display. Each subfield SF1, ..., SF8 is divided into a reset period (not shown), an address period A1, ..., A8, and a sustain discharge period S1, ..., S8. do.

In each address period A1, ..., A8, a display data signal is applied to the address electrode lines (A _R1 , A _G1 , ..., A _Gm , A _{Bm in} FIG. 1) and each Y electrode line Scan pulses corresponding to (Y ₁ , ..., Y _n ) are applied sequentially.

In each sustain discharge period S1, ..., S8, display is performed on all Y electrode lines Y ₁ , ..., Y _n and all X electrode lines X ₁ , ..., X _n . The discharge pulses are alternately applied to cause display discharge in discharge cells in which wall charges are formed in corresponding address periods A1, ..., A6.

Therefore, the luminance of the plasma display panel is proportional to the length of the sustain discharge periods S1, ..., S8 occupied in the unit frame. The lengths of the sustain discharge cycles S1, ..., S8 occupy a unit frame are 255T (T is the unit time). At this time, a time corresponding to 2 ⁿ is set in the sustain discharge period Sn of the nth subfield SFn. Accordingly, when the subfield to be displayed among the eight subfields is appropriately selected, it can be seen that display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

According to the above-described address-display separation driving method, since the time domains of the subfields SF1, ..., SF8 are separated from each other in the unit frame, the address period and the address period of each subfield SF1, ..., SF8 are separated. The time domains of the display periods are also separated from each other. Therefore, in the address period, after each XY electrode line pair has been addressed, it has to wait until all other XY electrode line pairs are addressed. As a result, since the time period occupied by the address period becomes longer for each subfield, the display period becomes relatively short. Therefore, the luminance of light emitted from the plasma display panel is relatively low. In order to remedy this problem, a known method is an Address-While-Display driving method as shown in FIG.

FIG. 4 shows a conventional Address-While-Display driving method for the Y electrode lines of the plasma display panel of FIG. 1.

Referring to the drawing, the unit frame is divided into _eight sub-fields SF ₁ ,..., SF ₈ for time division gray scale display. Here, each unit sub-field overlaps each other based on the driven Y electrode lines Y ₁ ,..., Y n to form a unit frame. Therefore, since all sub-fields SF ₁ ,..., SF ₈ are present at all time points, an address time slot is set between each display discharge pulse for performing each address step.

Reset, address and sustain discharge steps are performed in each sub-field, and the time allocated to each sub-field is determined by the display discharge time corresponding to the gray scale. For example, in the case of displaying 256 gray levels in frame units as 8-bit image data, if a unit frame (typically 1/60 second) consists of 256 units of time, driving is performed according to the image data of the least significant bit (Least Significant Bit). Times corresponding to 2 ⁿ are set in the sustain discharge period Sn of the n th subfield SFn. That is, since the sum of the unit times allocated to each sub-field is 255 unit time, 255 gray scale display is possible, and when the gray level in which no display discharge is performed in any sub-field is included, 256 gray scale display is possible.

5 illustrates a general driving apparatus of the plasma display panel of FIG. 1.

Referring to the drawings, a typical driving apparatus of the plasma display panel 1 includes an image processor 66, a controller 62, an address driver 63, an X driver 64, and a Y driver 65. The image processing unit 66 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The controller 62 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 66. The address driver 63 processes the address signal S _A among the drive control signals S _A , S _Y , and S _X from the controller 62 to generate a display data signal, and generates the generated display data signal. Applied to the address electrode lines. The X driving unit 64 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the control unit 62, and applies the X driving control signal S _X to the X electrode lines. The Y driver 65 processes the Y driving control signal S _Y among the driving control signals S _A , S _Y , and S _X from the controller 62 and applies the Y driving control signal S _Y to the Y electrode lines.

FIG. 6 shows driving signals applied to the panel of FIG. 1 in a unit sub-field by the address-display separation driving method of FIG. 3.

In FIG. 6, reference numeral S _{AR1 ..ABm} denotes a driving signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 ..Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to. FIG. 7 shows the wall charge distribution of one discharge cell immediately after a gradual rising voltage is applied to the Y electrode lines Y ₁ , ... Y _n in the reset period PR of FIG. 6. 8 illustrates a wall charge distribution of one discharge cell at the end of the reset period PR of FIG. 6. 7 and 8, the same reference numerals as used in FIG. 2 indicate the objects of the same function.

Referring to FIG. 6, in the reset period PR of the unit sub-field SF, first, a voltage applied to the X electrode lines X ₁ ,..., X _n is _first divided from the ground voltage V _G. 2 voltage (V _S ), for example, continuously rising to 155 volts (V). Here, the ground voltage V _G is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, between the X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), and the X electrode lines (X ₁ , ..., X) A weak discharge occurs between _n ) and the address electrode lines A ₁ , ..., A _m , and negative wall charges are formed around the X electrode lines X ₁ , ..., X _n . .

Next, the voltage applied to the Y electrode lines Y ₁ ,..., Y _n is third from the second voltage V _S , for example, from 155 volts V to a second voltage than the second voltage V _S. The highest voltage V _SET + V _{S that} is as high as the voltage V _SET is continuously raised to, for example, 355 volts (V). Here, the ground voltage V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , A weaker discharge occurs between ..., Y _n ) and the address electrode lines A _R1 , ..., A _Bm . Here, Y electrode lines _{(Y 1, ..., Y n} ) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _The reason why the discharge between _n ) and the X electrode lines (X ₁ , ..., X _n ) becomes stronger is that the negative wall charges around the X electrode lines (X ₁ , ..., X _n ) Because they were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 7).

Next, in the state where the voltage applied to the X electrode lines X ₁ ,..., X _n is maintained at the second voltage V _S , the Y electrode lines Y ₁ ,..., Y _n The voltage applied to) is continuously lowered from the second voltage V _S to the ground voltage V _G. Here, the ground voltage V _G is applied to the address electrode lines A _R1 ,..., A _Bm . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around..., Y _n ) move around the X electrode lines X ₁ ,..., X _n (see FIG. 8). Further, the address electrode lines (A _R1, ..., A _Bm) is so applied with a ground voltage (V _G), the address electrode lines are positive wall charges around the (A _R1, ..., A _Bm) Slightly increased.

Accordingly, in a subsequent addressing period PA, the display data signal is applied to the address electrode lines, and the Y electrode lines Y ₁ biased to the fourth voltage V _SCAN lower than the second voltage V _S. As a scan signal of the ground voltage V _G is sequentially applied to the ..., Y _n ), smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , ..., A _Bm is applied with the positive address voltage V _A when the discharge cell is selected and the ground voltage V _G when the discharge cell is not selected. do. Accordingly, when the display data signal of the positive address voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, wall charges are formed by the address discharge in the corresponding discharge cell. Wall charges do not form. Here, the second voltage (V _S) on to the more accurate and efficient address discharge, the X electrode lines (X _1, ... X _n) applied.

In the sustain discharge period PS that follows, the display of the second voltage V _S is maintained on all the Y electrode lines Y ₁ , ... Y _n and the X electrode lines X ₁ , ... X _n . The pulses are alternately applied, causing a discharge for maintaining the display in the discharge cells in which wall charges are formed in the corresponding address period PA.

FIG. 9 is a timing diagram illustrating a part of a driving signal applied to electrodes in a conventional sustain discharge cycle in the address-display separation driving method of FIG. 6.

Referring to the drawings, the address electrode (A electrode) is maintained at a predetermined level of voltage (0V), and two different levels of voltage (0V, Vs) are alternately applied to the X electrode and the Y electrode, respectively. When the two levels of voltage (0V, Vs) applied to each of the and Y electrodes are mutually changed, after the high voltage (Vs) applied to the X electrode is changed to a low voltage (0V), the low voltage applied to the Y electrode ( 0V) is changed to the high voltage Vs.

The time difference t1 may occur from the time when the voltage applied to the X electrode starts to fall from Vs to 0 V and the voltage applied to the Y electrode starts to rise from 0 V to Vs, thereby causing the potential of the X electrode and the Y electrode to rise. A zero potential time period t2 occurs at which the potentials of all become 0V.

As shown in the figure, in the waveform of the sustain pulse of the conventional sustain discharge cycle, since the zero potential time period t2 is larger than 0, the next pulse is applied after the application of the preceding pulse is finished. In this case, the address electrode acts as the anode and the X electrode acts as the cathode, whereby self-erasing discharge may occur.

FIG. 10 is a timing diagram schematically illustrating a potential change of each electrode in the conventional sustain discharge cycle of FIG. 9.

Referring to the drawings, when the applied voltage of the address electrode is set to 0 V equal to the low voltage of the sustain voltage in the conventional sustain waveform, the applied voltage of each of the X and Y electrodes, the wall potential change and the applied voltage formed on each electrode, The change in potential, which adds up the wall potential, is shown. At this time, for convenience of illustration, the X electrode application potential and the Y electrode application potential do not consider a rising time and a falling time.

In the stabilized sustain discharge, the potential on the address electrode (A electrode) side mainly seeks an intermediate value between the voltages of the X electrode side and the Y electrode side on which the sustain discharge occurs. That is, when a sustain pulse is applied between 0V and Vs, wall charges of ions are formed on the address electrode (A electrode) to which 0V is applied, thereby forming a positive wall voltage. In the case of the sustain electrodes (the X electrode and the Y electrode), a negative wall voltage is formed by the electrons on the electrode that was the anode in the previous sustain discharge, and a positive wall charge is formed by the ions on the electrode that was the cathode in the previous sustain discharge.

As shown in the figure, when both the X electrode and the Y electrode are maintained at 0V, the potential difference of Vas is caused by the positive wall voltage formed on the address electrode (A electrode) and the negative wall voltage formed on one sustain electrode. . For example, if Vs is 180V and the wall voltage change amount ΔVw of one sustaining electrode is 160V, Vas ≒ (Vs + ΔVw) / 2 = 170V, and Vas is slightly smaller than the sustaining voltage Vs. . In this case, the address electrode (A electrode) becomes the anode and one of the sustain electrodes becomes the cathode (which may vary depending on the height of the barrier rib and the cell structure), and in general, the discharge start voltage between the address electrode (A electrode) and the sustain electrode. Vf_as may be lower than the discharge start voltage Vf_ss between sustain electrodes, and in some cases, may be lower than sustain voltage Vs. For example, when Vf_as is about 150V and Vas_170V, a self-erasing discharge is formed between the address electrode and the Y electrode in the 0V applied voltage section.

As described above, when the length of the high level voltage section and the length of the low level voltage section are the same as in the conventional sustain pulse, there is a problem that self-discharge discharge may occur.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and by improving the waveform of the sustain pulse applied to the sustain electrode in the sustain discharge cycle, it is possible to suppress the self-erase discharge generated when the sustain pulses cross between the pair of sustain electrodes. It is an object of the present invention to provide a method of driving a plasma display panel.

In order to achieve the above object, a method of driving a plasma display panel according to the present invention includes discharging a region in which address electrode lines cross with respect to a pair of sustain electrode lines in which first and second sustain electrode lines are alternately arranged side by side. For a plasma display panel in which cells are formed, a reset period for initializing all discharge cells, an address period in which wall charges are formed in selected discharge cells, and gray scale display in discharge cells in which wall charges are formed in the address period are provided. A sustain discharge cycle in which discharge is maintained is provided.

When the two levels of voltages applied to the first and second sustain electrode lines are mutually changed in the sustain discharge period in which two different levels of voltage are alternately applied to the first and second sustain electrode lines. The high level voltage of the second storage electrode lines is changed to a low level voltage after the low level voltage of the first storage electrode lines is changed to a high level voltage.

It is preferable that the time for which the high level voltage is applied among the two different levels of voltages applied to the first and second sustain electrode lines is longer than the time for which the low level voltage is applied.

A high level voltage applied to the first sustain electrode lines and a high level voltage applied to the second sustain electrode lines are the same, and a low level voltage applied to the first sustain electrode lines and the first voltage. It is preferable that the low level voltage applied to the two sustain electrode lines is the same.

It is preferable that the lower voltage among the two different levels of voltages applied to the first and second sustain electrode lines is the ground voltage.

The voltages of the two levels applied to the first and second sustain electrode lines each have a magnitude of half of the voltage difference between the high level and the low level, and the polarities are opposite to each other.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 11 is a timing diagram schematically showing a driving signal applied to each electrode in the address-display separation driving method to which the present invention is applied as a preferred embodiment of the present invention. FIG. 12 is a timing diagram schematically showing a drive signal applied to each electrode in a sustain discharge cycle according to the present invention in the address-display separation driving method of FIG.

Referring to the drawings, in the method of driving a plasma display panel according to the present invention, discharge cells are formed in an area where address electrode lines cross with respect to sustain electrode line pairs in which first and second sustain electrode lines are alternately arranged side by side. As a method of driving a three-electrode surface discharge type plasma display panel as shown in FIG. 1, the method may be applied to the address-display separation driving method shown in FIG. 6.

The plasma display panel driving method according to the present invention is not limited to the case where the three-electrode surface discharge type plasma display panel is driven by the address-display separation driving method. The present invention may be applied to any type of plasma panel and its driving method for driving the plasma display panel using a sustain pulse in which a high level voltage and a low level voltage are alternately applied to the sustain electrode.

However, the present embodiment will be described with reference to the case of driving the three-electrode surface discharge type plasma display panel by the address-display separation driving method as an example.

In the method of driving a plasma display panel according to the present invention, a unit frame is divided into eight subfields for time division gray scale display, and each unit subfield is a reset period PR, an address period PA, and a sustain period. It is preferable to comprise the discharge period PS.

In the reset period PR, all discharge cells are initialized. In the address period PA, wall charges are formed in discharge cells to be displayed. In the sustain discharge period PS, discharge for gray scale display is maintained in discharge cells in which wall charges are formed in the address period PA.

In the sustain discharge period PS, a drive signal having a shape as shown in FIG. 11 is applied to each of the address electrode A electrode and the first and second sustain electrode lines X electrode and Y electrode. That is, the address electrode (A electrode) is maintained at a predetermined level of voltage, and two different levels of voltage are alternately applied to each of the first and second sustain electrode lines (the X electrode and the Y electrode). In this case, the first and second sustain electrode lines form a pair of sustain electrodes (X electrode, Y electrode).

In particular, when two levels of voltages applied to each of the sustain electrodes of the pair of sustain electrodes (X electrode and Y electrode) are mutually changed, the voltage of the low level of one sustain electrode (X electrode or Y electrode) is changed. After (V _X2 or V _Y2 ) is changed to a high level of voltage (V _X1 or V _Y1 ), the high level voltage V _Y1 or V _X1 of the other sustaining electrode (Y electrode or X electrode) becomes low level. Is changed to a voltage V _Y2 or V _X2 .

In this case, a time t _{h at} which a high level voltage V _X1 or V _Y1 is applied among two different levels of voltages applied to each of the pair of sustain electrodes X and Y electrodes is low. It is preferable that the voltage V _X2 or V _Y2 is longer than the time t _l that is applied.

Referring to FIG. 12, before the voltage applied to the X electrode starts to fall from the high level voltage V _X1 to the low level voltage V _X2 , the voltage applied to the Y electrode is the low level voltage V _Y2 ) rises to the high level of the voltage (V _Y1 ). Therefore, the zero potential time period (t2 in FIG. 9) that can occur in the conventional sustain waveform does not occur.

On the contrary, in the present invention, after the Y electrode rises from the low level voltage V _Y2 to the high level voltage V _Y1 , the X electrode goes from the high level voltage V _X1 to the low level voltage V _X2 . A period t4 occurs in which both the X electrode and the Y electrode maintain a high level of voltage until they start to fall.

Further, after the Y electrode rises from the low level voltage (V _Y2 ) to the high level voltage (V _Y1 ) until the X electrode falls from the high level voltage (V _X1 ) to the low level voltage (V _X2 ). A period t3 occurs in which neither the X electrode nor the Y electrode has a low level of voltage. Therefore, an operating voltage margin is generated for sustain electrodes (X electrode, Y electrode) for that much self-discharge discharge.

That is, it is preferable that the sustain waveform according to the present invention has a shape of the sustain pulse waveform such that the section t3 in which neither the X electrode nor the Y electrode has a low level voltage becomes a value larger than zero (t3? 0). The present invention can achieve the object of the present invention even when the X and Y electrodes have a shape of a sustain pulse waveform in which a period t4 for maintaining a high level of voltage becomes a value greater than 0 (t4? 0). Could be.

As shown in the figure, in the waveform of the sustain pulse of the sustain discharge cycle according to the present invention, since the section in which both the X electrode and the Y electrode maintain the low level voltage does not occur, the next pulse is applied before the end of the application of the preceding pulse. . In this case, the address electrode acts as the cathode, and the X electrode acts as the anode, so that the possibility of self-erasing discharge can be much reduced.

In addition, among the pair of sustain electrodes (X electrode, Y electrode), a high level voltage V _X1 or V _Y1 applied to one sustain electrode (X electrode or Y electrode) and the other sustain electrode ( The high level voltage (V _Y1 or V _X1 ) applied to the Y electrode or the X electrode is the same, and the low level voltage (V _X2 or V _Y2 ) applied to one sustaining electrode (X electrode or Y electrode). It is preferable that the low level voltage V _Y2 or V _X2 applied to the other sustaining electrode (Y electrode or X electrode) is the same.

In this case, 180 V (Vs) may be applied to the high level voltage V _X1 or V _Y1 . In addition, ground voltages 0V may be applied to the low-level voltages V _X2 or V _Y2 , respectively.

In addition, each of the pair of sustain electrodes (X electrode, Y electrode) may have a voltage having a magnitude of half of a voltage difference between a high level and a low level, respectively, and having a polarity opposite to each other. That is, if the voltage difference between the high level voltage and the low level voltage is Vs for both the X electrode and the Y electrode, a high level voltage V _X1 or V _Y1 is applied to Vs / 2 for both the X electrode and the Y electrode. , A low level voltage (V _X2 or V _Y2 ) may be applied at -Vs / 2.

Hereinafter, with respect to the present invention, the same voltage Vs (180V) is applied to the X electrode and the Y electrode as the high level voltages V _X1 and V _Y1 , and the low level voltages V _Y2 or V _X2 are applied. A description will be given based on the embodiment to which the same voltage ground voltage (0V) is applied.

In this case, each unit subfield overlaps each other based on the driven Y electrode lines to form a unit frame. Therefore, since all subfields exist at all time points, an address time slot is set between each sustain discharge pulse to perform each address period.

Reset periods, address periods, and discharge sustain periods are performed in each subfield, and the time allocated to each subfield is determined by the sustain discharge time corresponding to the gray scale.

All the discharge cells are initialized in the reset period PR. That is, first, the voltage applied to the X electrode lines is continuously raised from the ground voltage (0V) to Vs (180V). Ground voltage (0V) is applied to the Y electrode lines and the address electrode (A electrode) lines. Subsequently, with weak discharge occurring between the X electrode lines and the Y electrode lines, and between the X electrode lines and the address electrode lines, negative wall charges are formed around the X electrode lines.

Next, the voltage applied to the Y electrode lines is continuously raised from Vs (180V) to a higher voltage higher than this, for example 380V. At this time, a weak discharge occurs between the Y electrode lines and the X electrode lines, and a weaker discharge occurs between the Y electrode lines and the address electrode (A electrode) lines. Accordingly, a large number of negative wall charges are formed around the Y electrode lines, positive wall charges are formed around the X electrode lines, and less positive wall charges are formed around the address electrode (A electrode) lines. .

Next, while the voltage applied to the X electrode lines is maintained at Vs, the voltage applied to the Y electrode lines is continuously lowered to the ground voltage (0 V), and the ground voltage is applied to the address electrode (A electrode) lines. (0V) is applied. Accordingly, due to the weak discharge between the X electrode lines and the Y electrode lines, some of the negative wall charges around the Y electrode lines move around the X electrode lines, and around the address electrode (A electrode) lines The positive wall charges of are slightly increased.

In the address period PA, wall charges are formed in discharge cells to be displayed. That is, the display data signal is applied to the address electrode (A electrode) lines, and the scan signal is sequentially applied to each of the Y electrode lines. In addition, a predetermined voltage Vs is applied to the X electrode lines for more accurate and efficient address discharge.

In this case, when the discharge cell is selected, a positive address voltage is applied to the display data signal, and a ground voltage (0V) is applied to the cell that is not selected. In addition, the scan signal of the ground voltage (0V) is sequentially applied to the Y electrode lines biased at a voltage lower than Vs (180V) as the scan signal. As a result, wall charges for sustain discharge are formed only in the selected discharge cell.

In the sustain discharge period PS, discharge for gray scale display is maintained in discharge cells in which wall charges are formed in the address period PA. That is, display sustain pulses of Vs (180V) are alternately applied to all the Y electrode lines and the X electrode lines, thereby causing discharge for display maintenance in discharge cells in which wall charges are formed in the address period PA.

FIG. 13 is a timing diagram schematically illustrating a potential change of each electrode in a sustain discharge cycle according to the present invention of FIG. 12.

Referring to the drawings, in the sustain waveform according to the present invention, when the applied voltage of the address electrode is 0 V, which is the same as the low voltage of the sustain voltage, the applied voltage of each of the X electrode and the Y electrode and the change in the wall potential formed on each electrode and the application thereof. The change in potential, the sum of the voltage and the wall potential, is shown. At this time, for convenience of illustration, the X electrode application potential and the Y electrode application potential do not consider a rising time and a falling time.

In the stabilized sustain discharge, the potential on the address electrode (A electrode) side mainly seeks an intermediate value between the voltages of the X electrode side and the Y electrode side on which the sustain discharge occurs. That is, when a sustain pulse is applied between 0V and Vs, wall charges of ions are formed on the address electrode (A electrode) to which 0V is applied, thereby forming a positive wall voltage. In the case of the X electrode and the Y electrode, a negative wall voltage is formed by the electrons on the electrode which was the anode in the previous sustain discharge, and a positive wall charge is formed by the ions on the electrode which was the cathode in the previous sustain discharge.

As shown, before the voltage applied to the X electrode starts to fall from the high level voltage (Vs) to the low level voltage (0 V), the voltage applied to the Y electrode is first high at the low level voltage (0 V). Raise to the voltage of the level (Vs). Therefore, in the conventional sustaining waveform, neither the X electrode nor the Y electrode capable of generating the self-erasing discharge has a section having a low level of voltage (0V).

On the contrary, in the present invention, after the Y electrode rises from the low level voltage (0V) to the high level voltage (Vs), the X electrode starts to fall from the high level voltage (Vs) to the low level voltage (0V). An interval (t4 in FIG. 12) occurs in which both the X electrode and the Y electrode maintain a high level of voltage.

In this case, when power is applied to the sustain electrode (X electrode and Y electrode) lines so as to have a sustain waveform as shown in the drawing, the address electrode (A electrode) is provided in a section in which both the X electrode and the Y electrode maintain a high level of voltage. A voltage of about Vsa is applied between the electrode and one of the sustain electrodes (X electrode in FIG. 13).

For example, if Vs is 180V and the wall voltage variation ΔVw of one sustaining electrode is 160V, Vsa ≒ (Vs + ΔVw) / 2 = 170V, but Vsa is slightly smaller than the sustaining voltage Vs. , Has the same size as Vas of FIG. 10. In this case, generally, the discharge start voltage Vf_as between the address electrode A electrode and the sustain electrode is lower than the discharge start voltage Vf_ss between the sustain electrodes, and in some cases, may be lower than the sustain voltage Vs.

In this case, however, the address electrode (A electrode) becomes the cathode, and one of the sustain electrodes (X electrode) becomes the anode, and the address electrode (A electrode) becomes the anode in the conventional sustain waveform (Fig. 10), and the sustain Unlike the case where one of the electrodes (X electrode) becomes the cathode, the possibility of the self-erasing discharge is significantly reduced.

In the case of the sustain waveform according to the present invention, when the address electrode (A electrode) acting as a cathode is compared with the sustain electrode side to which MgO is usually applied, the phosphor is coated on the side of the address electrode (A electrode), thereby emitting very low secondary electrons. Has a coefficient.

Therefore, when the address electrode A electrode is the cathode, the discharge start voltage Vf_sa with the sustain electrode is very high, and the discharge start voltage Vf_as with the sustain electrode when the address electrode A electrode is the anode. It is much larger than this, and in this case the relationship of Vf_sa> Vs> Vas can be established. Therefore, no self-erasing discharge is formed in the section in which both the X electrode and the Y electrode maintain a high level of voltage (t4 in FIG. 12).

In FIG. 12, the case where both the X electrode and the Y electrode maintain a high level of voltage (t4 in FIG. 12) is larger than zero is the content of the present invention. In addition, the case in which at least one of the X electrode and the Y electrode maintains a high level of voltage (t3 in FIG. 12) is greater than 0 is also included in the present invention. That is, the screen of the plasma display panel can be displayed without generating the self-erasing discharge even in the sustain discharge section corresponding to the section in which at least one of the X electrode and the Y electrode maintains a high level of voltage (t3 in FIG. 12). Could be.

Even in the conventional sustain waveform, the possibility of occurrence of the self-erasing discharge can be reduced by reducing the period in which both the X electrode and the Y electrode maintain a high level of voltage (t2 in FIG. 9), but after the pulse OFF of one electrode, In the sustain waveform in which the pulse of the electrode is ON, there is a rise time and a fall time of the pulse, so that there is a time in which the address electrode (A electrode) operates as an anode with respect to the sustain electrode, and thus there is a possibility of occurrence of self-erase discharge. do.

Basically, when the address electrode (A electrode) is the positive electrode, the discharge start voltage with the sustain electrode is low, but when the address electrode (A electrode) is the negative electrode, the discharge start voltage with the sustain electrode is very high. Although the voltage relationship between the sustain electrodes in the sustain waveform according to the invention is similar, there is a very large difference in the relationship with the address electrode (A electrode). That is, the sustain discharge may be affected in the conventional sustain waveform, but such self-erasing discharge is essentially suppressed in the sustain waveform according to the present invention.

According to the sustain waveform according to the present invention, the amount of wall charges between the sustain electrodes due to the self-erase discharge is not reduced, and the sustain voltage margin is not reduced. In the first half of the sustain discharge period, the time when the potential of the address electrode (A electrode) is at a lower potential (cathode) than the potential of the sustain electrode is long, so that the probability of loss of ions accumulated on the address electrode is reduced, which is advantageous for subsequent reset. Therefore, the operation margin such as the address voltage and the sustain voltage can be increased, and the contrast can be improved by reducing the amount of back light emission.

In addition, the generation of discharge spots due to the luminance difference in the panel caused by such self-erasing discharge is suppressed only in a part of the panel depending on the driving conditions and the unevenness of the panel inevitably. That is, by essentially eliminating the self-erasing discharge in the sustain discharge section, the uniformity of the sustain discharge is increased and the occurrence of discharge spots resulting therefrom is suppressed.

According to the driving method of the plasma display panel according to the present invention, the self-erase discharge generated when the sustain pulses applied to the pair of sustain electrodes cross each other in the sustain discharge cycle can be suppressed.

Therefore, it is possible to solve the problem of impairing the stabilization of the sustain discharge due to the self-erasing discharge occurring in the sustain discharge cycle and the problem of asymmetric discharge.

In addition, the problem that the intensity of the sustain discharge is weakened to decrease the brightness, the margin of the operating voltage is reduced, and the problem that discharge stains may occur due to spatially nonuniform sustain discharge can be solved.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible. Could be. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

1 is a perspective view showing an internal structure of a conventional three-electrode surface discharge plasma display panel.

2 is a view showing an example of one discharge cell of the panel of FIG.

3 is a timing diagram illustrating a conventional address-display separation driving method for Y electrode lines of the plasma display panel of FIG. 1.

4 is a timing diagram illustrating a conventional address-display simultaneous driving method for Y electrode lines of the plasma display panel of FIG. 1.

5 is a block diagram illustrating a general driving device of the plasma display panel of FIG. 1.

FIG. 6 is a timing diagram illustrating driving signals applied to a panel of FIG. 1 in a unit sub-field of the address-display separation driving method of FIG. 3.

FIG. 7 is a cross-sectional view illustrating a wall charge distribution of one display cell immediately after a gradual rising voltage is applied to the Y electrode lines in the reset cycle of FIG. 6.

8 is a cross-sectional view illustrating a wall charge distribution of one discharge cell at the end of the reset cycle of FIG. 2.

FIG. 9 is a timing diagram illustrating a part of a driving signal applied to electrodes in a conventional sustain discharge cycle in the address-display separation driving method of FIG. 6.

FIG. 10 is a timing diagram schematically illustrating a potential change of each electrode in the conventional sustain discharge cycle of FIG. 9.

FIG. 11 is a timing diagram schematically showing a driving signal applied to each electrode in the address-display separation driving method to which the present invention is applied as a preferred embodiment of the present invention.

FIG. 12 is a timing diagram schematically showing a drive signal applied to each electrode in a sustain discharge cycle according to the present invention in the address-display separation driving method of FIG.

FIG. 13 is a timing diagram schematically illustrating a potential change of each electrode in a sustain discharge cycle according to the present invention of FIG. 12.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ..., X _n ... X electrode line, Y ₁ , ..., Y _n ... Y electrode line,

A ₁ , ..., A _m ... address electrode line, X _na , Y _na ... transparent electrode line,

X _nb , Y _nb ... metal electrode line, SF ₁ , ... SF ₈ ... sub-field,

S _Y1 , ..., S _Yn ... Y electrode drive signal, V _G ... ground voltage,

S _X1 , ..., S _Xn ... X electrode drive signal, SF ... unit sub-field,

S _AR1 .. _ABm ... display data signal, 62 ... logical control,

63..Address drive, 64 ... X drive,

65 ... Y drive unit, 66 ... image processing unit,

Claims (5)

A reset period for initializing all discharge cells for a plasma display panel in which discharge cells are formed in an area where the address electrode lines cross with respect to the pair of sustain electrode lines in which the first and second sustain electrode lines are alternately arranged side by side, and selected A driving method of a plasma display panel comprising: an address period in which wall charges are formed in discharge cells, and a sustain discharge period in which discharge for gray scale display is maintained in discharge cells in which wall charges are formed in the address period. In the sustain discharge period in which voltages of two different levels of low and high levels are alternately applied to the first and second sustain electrode lines, sustain discharge is generated in a sustain pulse to which the high level voltage is applied. , When the two levels of voltage applied to the first and second sustain electrode lines are mutually changed, the second sustain after the low level voltage of the first sustain electrode lines is changed to a high level voltage of the sustain pulse. And a high level voltage of the sustain pulses of the electrode lines is changed to a low level voltage. The method of claim 1, The method of driving a plasma display panel according to claim 1, wherein a time for applying a high level voltage is longer than a time for applying a low level voltage among two different levels of voltages applied to the first and second sustain electrode lines. The method of claim 1, A high level voltage applied to the first sustain electrode lines and a high level voltage applied to the second sustain electrode lines are the same, and a low level voltage applied to the first sustain electrode lines and the first voltage. 2. A method of driving a plasma display panel, wherein the low level voltages applied to the sustain electrode lines are the same. The method of claim 1, And a low level voltage among the two different levels of voltages applied to the first and second sustain electrode lines is a ground voltage. The method of claim 1, The voltage of two levels applied to the first and second sustain electrode lines has a magnitude of half of a voltage difference between a high level and a low level, respectively, and the polarities thereof are opposite to each other.