KR100647674B1 - Method for plasma display device being addressed by middle electrode lines - Google Patents

Abstract

The present invention relates to a method of driving a plasma display device addressed by intermediate electrode lines. The present invention has a front substrate and a rear substrate spaced apart from each other, the X electrode lines and Y electrode lines are alternately formed in parallel between the substrate, the address for the X electrode lines and Y electrode lines The display cells are set in regions where the electrode lines cross each other, and M electrodes are formed between the X electrode lines and the Y electrode lines and between the Y electrode lines and the X electrode lines. In the method, the unit frame applied to the plasma display device is composed of a plurality of sub-fields, the sub-fields are divided into a reset step, an addressing step and a display-holding step, respectively, during the display-holding step, Alternately applying sustain discharge pulses having a positive voltage to the X electrode lines and the Y electrode lines. The sustain discharge of the plasma display apparatus is stably performed by applying a positive voltage to the address electrode lines and applying a positive voltage to the M electrode lines.

Description

Method for driving plasma display device addressed by intermediate electrode lines {Method for plasma display device being addressed by middle electrode lines}

A brief description of each drawing is provided in order to provide a thorough understanding of the drawings referred to in the detailed description of the invention.

1 is a perspective view showing the internal structure of a four-electrode surface discharge plasma display apparatus for applying the present invention.

FIG. 2 is a cross-sectional view of one of the display cells included in the plasma display device shown in FIG. 1.

3 is a block diagram of the plasma display device shown in FIG. 1 and a driving device for driving the same.

4 illustrates a structure of a unit frame applied to the plasma display device shown in FIG. 1.

5 is a waveform diagram of signals for explaining a method of driving a plasma display device according to the present invention.

<Explanation of symbols for main parts of the drawings>

101; A plasma display device 110; Front glass substrate

111,115; Dielectric layer 112; Protective layer

113; Rear glass substrate, 114; Discharge space

116; Fluorescent layer, 117; septum

M1 _- M2n _-1 ; M electrode lines, X1 to Xn; X electrode lines

Y1 to Yn; Y electrode lines AR1 to ABm; Address electrode lines

Xna, Yna; Transparent electrode lines, Xnb, Ynb; Metal electrode lines

362; Logic control section, 363; Address driver

364; X drive, 365; Y drive

366; An image processor 367; M drive

Sx1 to Sxn; X electrode drive signals, Sy1 to Syn; Y electrode driving signals

Sm1 _- Sm2n _-1 ; M electrode drive signals, SAR1 to SABm; Address drive signals

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display device, and more particularly, to a method of driving a plasma display device for stabilizing sustain discharge by applying a positive voltage to address electrode lines during a display-holding step of a plasma display device having a 4-electrode surface discharge structure. will be.

The conventional plasma display device has a three-electrode surface discharge structure composed of X electrode lines, Y electrode lines, and address electrode lines. In order to drive the plasma display apparatus, unit frames including driving information are applied to the plasma display apparatus. Accordingly, the plasma display apparatus is driven to display time-division gray scales by discharging selected display cells among the display cells included in the plasma display apparatus. .

The unit frame consists of a reset step, an addressing step and a display-hold step. The X electrode lines and the Y electrode lines and the address electrode lines are initialized during the reset step, and the addressing is performed between the Y electrode lines and the address electrode lines during the addressing step, and the Y electrode lines and the X electrode during the display-holding step. A sustain discharge is generated in selected display cells among the display cells between the electrode lines to represent time division gray scales.

Here, the X electrode lines and the Y electrode lines each belong to only one XY electrode line pair and do not belong to the other electrode line pair. Therefore, the non-discharge regions inevitably present between the XY electrode line pairs are factors that lower the luminous efficiency and luminance of the plasma display apparatus.

The present invention provides a plasma display device having a four-electrode surface discharge structure, the method of driving a plasma display device for preventing low discharge of sustain discharge generated during the display-maintenance step of a unit frame applied to the plasma display device. The purpose is to provide.

The present invention to achieve the above technical problem

And a front substrate and a rear substrate spaced apart from each other, wherein X electrode lines and Y electrode lines are alternately formed in parallel between the substrates, and address electrode lines are formed with respect to the X electrode lines and Y electrode lines. In the driving method of the plasma display apparatus in which the display cells are set in the areas formed to intersect, M electrodes are formed between the X electrode lines and Y electrode lines and between the Y electrode lines and X electrode lines. The unit frame applied to the plasma display apparatus includes a plurality of subfields, and each of the subfields is divided into a reset step, an addressing step, and a display-holding step. During the display-holding step, the X electrode line Alternately applying sustain discharge pulses having a positive voltage to the electrodes and the Y electrode lines, and Provides a method of driving a plasma display apparatus, it characterized in that for applying a positive voltage to the electrode lines of dresses.

Preferably, during the display-holding step, a positive voltage is applied to the M electrode lines to generate a trigger discharge between the X electrode lines and the M electrode lines, and the X electrode lines and the Y electrode lines. Generating a long gap discharge therebetween to sustain discharge the display cells selected in the addressing step; during the addressing step, a positive voltage is applied to the X electrode lines and a ground voltage is applied to the Y electrode lines; Scan pulses are sequentially applied to the lines, and data pulses are applied to the address electrode lines selected from the address electrode lines.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

FIG. 1 is a perspective view showing an internal structure of a four-electrode surface discharge type plasma display device for applying the present invention, and FIG. 2 is a cross-sectional view of one of the display cells included in the plasma display device shown in FIG. 1. 1 and 2, the plasma display apparatus 101 having a four-electrode surface discharge structure for applying the present invention includes address electrode lines AR1 to ABm formed between the front and rear glass substrates 110 and 113. ), Dielectric layers 111 and 115, Y electrode lines Y1 to Yn, M electrode lines M1 to M _2n-1 , X electrode lines X1 to Xn, phosphor 116, partition 117, and A magnesium monoxide (MgO) layer 112 serving as a protective layer is provided.

The address electrode lines AR1 to ABm are formed in a predetermined pattern on the front side of the rear glass substrate 113. The lower dielectric layer 115 is coated on the entire surface in front of the address electrode lines AR1 to ABm. The barrier ribs 117 are formed in a direction parallel to the address electrode lines AR1 to ABm in front of the lower dielectric layer 115. The partition walls 117 function to partition the discharge area of each display cell and to prevent optical cross talk between each display cell. The fluorescent layer 116 is applied between the partition walls 117.

At the rear of the front glass substrate 110, the X electrode lines X1 to Xn and the Y electrode lines Y1 to Yn are alternately formed side by side to form the XY electrode line pairs X1Y1 to XnYn, before YX. The pole line pairs Y1X2 to Yn-1Xn are alternately shaped. For reference, when the number of XY electrode line pairs X1Y1 to XnYn is n, the number of YX electrode line pairs Y1X2 to Yn-1Xn is n-1. Accordingly, (2n-1) M electrode lines M1 to M2n-1 are formed between all the XY electrode line pairs X1Y1 to XnYn and all the YX electrode line pairs Y1X2 to Yn-1Xn. The address electrode lines AR1 to ABm are formed to cross the X, M, and Y electrode lines, so that the crossing areas form display cells.

The M electrode lines M1 to M _2n-1 , the X electrode lines X1 to Xn, and the Y electrode lines Y1 to Yn are transparent electrode lines made of a transparent conductive material such as indium tin oxide (ITO), or the like. M _2n-1 a, Xna, and Yna and metal electrode lines M _2n-1 b, Xnb, and Ynb to increase conductivity are formed.

The front dielectric layer 111 is formed by coating the entire surface behind the X electrode lines X1 to Xn, the M electrode lines M1 to M _2n-1 , and the Y electrode lines Y1 to Yn. . A protective layer 112 for protecting the plasma display apparatus 101 from a strong electric field, for example, a magnesium monoxide (MgO) layer is formed by applying a front surface to the back of the front dielectric layer 111. The plasma forming gas is sealed in the discharge space 114.

In order to drive the plasma display apparatus 101, a unit frame composed of subfields consisting of a reset step, an addressing step, and a display-holding step is sequentially provided to the plasma display device 101. Is approved. All display cells have a constant wall charge state during the reset step. During the addressing step, a predetermined wall voltage is generated in the selected display cells. A predetermined alternating voltage is applied to all XY electrode line pairs during the display-holding phase, so that sustain discharge occurs in the display cells in which the wall voltage is formed during the addressing step. During the display-holding step, plasma is formed in the discharge space 114 of the selected display cells causing the sustain discharge, that is, the gas layer, and the fluorescent layer 116 is excited by the ultraviolet radiation to generate light.

3 is a block diagram of a driving device for driving the plasma display device shown in FIG. 1 and a plasma display device connected thereto. Referring to FIG. 3, the driving apparatus of the plasma display apparatus includes an image processor 366, a logic controller 362, an address driver 363, an M driver 367, an X driver 364, and a Y driver 365. do.

The image processor 366 processes the external image signal to generate an internal image signal including red (R), green (G), and blue (B) digital image data, a clock signal, and vertical and horizontal synchronization signals. The logic controller 362 generates the driving control signals SA, SM, SY, and SX according to the internal image signal output from the image processor 366. The address driver 363 processes the address drive control signal SA output from the logic controller 362 to generate a display data signal, and applies the generated display data signal to the address electrode lines AR1 to ABm. . The M driver 367 operates in accordance with the M drive control signal SM output from the logic controller 362 to drive the M electrode lines M1 to M _2n-1 . The X driver 364 operates according to the X driving control signal SX output from the logic controller 362 to drive the X electrode lines X1 to Xn. The Y driver 364 operates according to the Y driving control signal SY output from the logic controller 362 to drive the Y electrode lines Y1 to Yn.

Here, scanning pulses are sequentially applied to each of the M electrode lines M1 to M _2n-1 , and addressing is performed to apply data pulses to address electrode lines selected from the address electrode lines AR1 to ABm. For example, the scanning order of the M electrode lines M1 to M _2n-1 is M1->M2->...->Mn-1->Mn->...-> M _2n-1 . Next, an alternating voltage is applied between all the X electrode lines X1 to Xn and all the Y electrode lines Y1 to Yn so that the display cells selected by the addressing cause sustain discharge.

Accordingly, the display cells may be set by all the XY electrode line pairs X1Y1 to XnYn and all the YX electrode line pairs Y1X2 to Yn-1Xn.

Further, by the addressing, wall charges necessary for sustain discharge are formed on both the X and Y electrodes of the selected display cell, and wall charges required for the sustain discharge on at least one of the X and Y electrodes of the unselected display cell. Is not formed. For example, in four M electrode lines arranged in series, if there are two display cells that are not selected between two selected display cells, one of the X and Y electrodes of each of the two unselected display cells No wall charge necessary for sustain discharge is formed.

Therefore, while the display cells are set by all of the XY electrode line pairs X1Y1 to XnYn and all the YX electrode line pairs Y1X2 to Yn-1Xn, a progressive driving method can be used, so that luminous efficiency and luminance can be used. Flickering can be suppressed while increasing.

Additionally, since all the X electrode lines X1 to Xn and the Y electrode lines Y1 to Yn do not directly participate in addressing, when the partitions are formed in the same direction as the length direction of the XY electrode line pairs, all X and Metal electrode lines of Y electrode lines may be positioned on the barrier ribs. Accordingly, since the metal electrode lines of all the X and Y electrode lines do not block the emitted light, the luminous efficiency and luminance of the discharge display device may be higher.

The effects may increase as the resolution of the discharge display apparatus 101 increases.

Those skilled in the art may configure the plasma display apparatus in various ways in addition to the configuration shown in FIG. 3.

FIG. 4 is a diagram illustrating a structure of a unit frame applied to the plasma display device shown in FIG. 1. Referring to FIG. 4, each of all unit frames is divided into eight subfields SF1 to SF8 to realize time division gray scale display. The subfields SF1 to SF8 are divided into reset steps R1 to R8, addressing steps A1 to A8 and display-holding steps S1 to S8, respectively.

The discharge conditions of all the display cells are made uniform in the reset steps R1 to R8 while being suitable for the addressing to be performed in the next step.

In the addressing steps A1 to A8, the display data signals are applied to the address electrode lines AR1 to ABm in FIG. 1 and the scan pulses corresponding to the M electrode lines M1 to M _{2n-1 in} FIG. Are applied sequentially. Accordingly, when high level display data signals are applied while the scan pulse is applied, wall charges are formed by addressing discharge in the corresponding display cell, and wall charges are not formed in the other display cell.

In the display-holding steps S1 to S8, pulses for sustain discharge are alternately applied to all the Y electrode lines (Y1 to Yn in FIG. 1) and all the X electrode lines (X1 to Xn in FIG. 1). In the corresponding addressing steps A1 to A8, sustain discharge is caused in the display cells in which the wall charges are formed. Thus, the luminance of the plasma display device 101 (in FIG. 1) is proportional to the length of the display-holding steps S1 to S8 occupy in the unit frame. The length of the display-holding steps S1 to S8 occupying a unit frame is 255T (T is unit time). Therefore, it can be displayed in 256 gray scales, even if it is not displayed once in a unit frame.

Here, in the display-maintaining step S1 of the first subfield SF1, the time 1T corresponding to 2 ⁰ corresponds to 2 ¹ in the display-maintaining step S2 of the second subfield SF2. The time 2T corresponds to 2 ² in the display-holding step S3 of the third subfield SF3, and ² in the display-holding step S4 of the fourth subfield SF4. ^The time 8T corresponding to ³ is the display-holding step S5 of the fifth subfield SF5. The time 16T corresponding to 2 ⁴ is the display-holding step of the sixth subfield SF6. In S6), the time 32T corresponding to 2 ⁵ , the display-maintaining step S7 of the seventh subfield SF7 includes the time 64T corresponding to 2 ⁶ , and the time of the eighth subfield SF8. In the display-holding step S8, a time 128T corresponding to 2 ⁷ is set, respectively.

Accordingly, if the subfield to be displayed among the eight subfields SF1 to SF8 is appropriately selected, the display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed on any of the subfields.

5 is a waveform diagram of signals for explaining a method of driving a plasma display device according to the present invention. In FIG. 5, the address electrode driving signals SAR1 to ABm are applied to the address electrode lines AR1 to ABm of FIG. 1, and the X electrode driving signals SX1 to Xn are the X electrode lines (X1 of FIG. 1). is applied to ~Xn), M electrode driving signals (SM1~SM _2n-1)) is the M electrode lines (applied to the M1~M _2n-1) in Fig. 1, Y electrode driving signal (SY1~SYn ) Is applied to the Y electrode lines (Y1 to Yn in FIG. 1).

An operation of driving signals performed in one subfield SFa among the subfields SF1 to SF8 of FIG. 4 will be described with reference to FIG. 5. The subfield SFa is divided into a reset step Ra, an addressing step Aa and a display-holding step Sa.

Just before the initial time point t0 of the subfield SFa, the last sustain discharge pulse of the previous stage is applied to the X electrode lines (X1 to Xn in FIG. 1), and a positive voltage Vs is applied to the M electrode lines. In the address electrode lines AR1 to ABm of FIG. 1, a positive voltage Va is applied. Therefore, at the initial time t0 of the subfield SFa, the X electrode lines (X1 to Xn in FIG. 1), the M electrode lines (M1 to M _{2n-1 in} FIG. ₁ ), and the address electrode lines (FIG. Negative wall charges are accumulated around AR1 to ABm of 1, and positive wall charges are accumulated around Y electrode lines (Y1 to Yn in FIG. 1).

During the wall charge erase time t0 to t1 of the reset step Ra, the X electrode driving signals Sx1 to Sxn, the M electrode driving signals Sm1 to Sm _2n-1 , and the Y electrode driving signals Sy1 to Syn) and the address electrode driving signals SAR1 to SABm are all maintained at the ground voltage Vg.

During the wall charge accumulation time t1 to t2 of the reset step Ra, the X electrode driving signals Sx1 to Sxn, the Y electrode driving signals Sy1 to Syn and the address electrode driving signals SAR1 to SABm are All are kept at the ground voltage Vg, and the M electrode driving signals Sm1 to Sm _2n-1 rise from the ground voltage Vg to the high voltage Vset. Accordingly, a weak discharge occurs between the electrodes of all display cells, and more negative wall charges are accumulated around the M electrode lines (M1 to M _{2n-1 in} FIG. ₁ ), and the X electrode lines (FIG. Positive wall charges are accumulated around X1 to Xn of 1, Y electrode lines (Y1 to Yn of FIG. 1), and address electrode lines (AR1 to ABm of FIG. 1).

During the wall charge distribution time t2 to t3 of the reset step Ra, the X electrode driving signals Sx1 to Sxn, the Y electrode driving signals Sy1 to Syn and the address electrode driving signals SAR1 to SABm are All are maintained at the ground voltage Vg, and the M electrode driving signals Sm1 to Sm _2n-1 are continuously lowered to the negative voltage Vnf. Then, a weak discharge occurs between the electrodes of all the display cells, so that some of the negative wall charges accumulated around the M electrode lines (M1 to M _{2n-1 in} FIG. ₁ ) become X electrode lines (FIG. 1). By moving around the X1 to Xn, Y electrode lines (Y1 to Yn in FIG. 1) and address electrode lines (AR1 to ABm in FIG. 1), M electrode lines (M1 to M _{2n-1 in} FIG. ), The number of negative wall charges that have accumulated in

Accordingly, the wall electric-potential of the address electrode lines AR1 to ABm in FIG. 1 is higher than the wall potential of the M electrode lines M1 to M _{2n-1 in} FIG. This lowers the addressing voltage required for the counter discharge between the address electrode lines (AR1 to ABm in FIG. 1) and the M electrode lines (M1 to M _{2n-1 in} FIG. 1) selected in the subsequent addressing step Aa. .

During the addressing step Aa, display data signals are applied to the address electrode lines AR1 to ABm in FIG. 1, and the M electrode lines biased to a voltage higher than the voltage Vnf and lower than the ground voltage Vg ( Scan pulses of the negative voltage Vnf are sequentially applied to M1 to M _2n- 1 of FIG. 1. The display data signals applied to the address electrode lines AR1 to ABm in FIG. 1 have a positive addressing voltage Va when the display cell is selected and a ground voltage Vg when the display cell is not selected. As described above, while the scan pulse of the negative voltage Vnf is applied to the M electrode lines M1 to M _2n-1 of FIG. 1, the positive addressing voltage Va is applied to the address electrode lines AR1 to ABm of FIG. 1. When display data signals are applied, addressing discharge occurs in the selected display cells. Accordingly, due to the addressing discharge, positive wall charges are formed around the M electrode lines (M1 to M2n-1 in FIG. 1) of the selected display cells, and the address electrode lines (AR1 to ABm in FIG. 1) of the selected display cells are formed. ) And around the X electrode lines (X1 to Xn in FIG. 1), negative wall charges are formed.

Here, a positive voltage Vs is applied to the X electrode lines X1 to Xn of FIG. 1 to accumulate negative wall charges around the X electrode lines X1 to Xn of FIG. 1. This helps the sustain discharge to be performed smoothly in the subsequent display-holding step Sa.

At the initial time t4 to t5 of the sustain discharge step Sa, the ground voltage Vg is applied to the X electrode lines X1 to Xn in FIG. 1, and the M electrode lines M1 to M _{2n in} FIG. _-1 ) and a positive voltage Vs and a positive voltage Va are applied to the address electrode lines AR1 to ABm of FIG. 1, respectively, and a positive pulse is applied to the Y electrode lines Y1 to Yn of FIG. Is authorized. Accordingly, trigger discharge occurs between the M electrode lines (M1 to M _{2n-1 in} FIG. 1) and the X electrode lines (X1 to Xn in FIG. 1), and thus the X electrode lines (X1 to FIG. 1 in FIG. 1). Long gap discharge occurs between Xn and the Y electrode lines (Y1 to Y2 in FIG. 1). In this state, the addressing step Aa by alternately applying sustain discharge pulses having a positive voltage Vs to the X electrode lines X1 to Xn in FIG. 1 and the Y electrode lines Y1 to Yn in FIG. Sustain discharge occurs in the display cells in which the wall charges were formed.

During the display-holding step Sa, a positive voltage Vs is continuously applied to the address electrode lines AR1 to ABm in FIG. Accordingly, a large amount of negative wall charges are accumulated around the address electrode lines AR1 to ABm in FIG. 1, thereby improving the discharge margin, thereby stably performing sustain discharge.

During the display-holding step Sa, pulse signals applied to the X electrode lines (X1 to Xn in FIG. 1) and the Y electrode lines (Y1 to Yn in FIG. 1) are applied so as not to overlap each other.

The best embodiments have been disclosed in the drawings and the specification, and the terminology used herein is for the purpose of describing the invention only and is not intended to be limiting of the scope of the invention as defined in the appended claims or claims. Therefore, those skilled in the art will be capable of various modifications and other equivalent embodiments from this, and therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

As described above, in the plasma display device 101 having the four-electrode surface discharge structure, the positive voltage Va is applied to the address electrode lines AR1 to ABm in FIG. 1 during the display-holding step Sa. The discharge margin is improved to stabilize the sustain discharge.

Claims (4)

And a front substrate and a rear substrate spaced apart from each other, wherein X electrode lines and Y electrode lines are alternately formed in parallel between the substrates, and address electrode lines are formed with respect to the X electrode lines and Y electrode lines. In the driving method of the plasma display apparatus in which the display cells are set in the areas formed to intersect, M electrodes are formed between the X electrode lines and Y electrode lines and between the Y electrode lines and X electrode lines. , The unit frame applied to the plasma display device is composed of a plurality of subfields, and the subfields are divided into a reset step, an addressing step, and a display-hold step, respectively. During the display-holding step, sustain discharge pulses having a positive voltage are alternately applied to the X electrode lines and the Y electrode lines, a positive voltage is applied to the address electrode lines, and the M electrode lines. A method of driving a plasma display device, characterized by applying a positive voltage. delete The method of claim 1, wherein, during the addressing step, a positive voltage is applied to the X electrode lines, a ground voltage is applied to the Y electrode lines, and a scan pulse is sequentially applied to the M electrode lines. A method of driving a plasma display apparatus, comprising applying a data pulse to address electrode lines selected from among address electrode lines. The method of claim 3, wherein the scan pulse is a pulse having a negative voltage.

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