KR100603371B1 - Method for driving plasma display panel on which pulses having mutually different rising time are applied - Google Patents

Abstract

The present invention relates to a driving method of a plasma display panel for applying a pulse having a different rise time for each address electrode line. The present invention is a front substrate and a rear substrate spaced apart from each other, the X electrode lines and Y electrode lines are alternately arranged between the substrates to form XY electrode line pairs, green address electrode line for the XY electrode line pairs In the method of driving a plasma display panel in which display cells are formed in areas where the red address electrode lines and the blue address electrode lines cross each other, the unit frame applied to the plasma display panel is divided into a plurality of subfields. The subfields each perform a reset step, an addressing step and a display-hold step, wherein the reset step comprises: (a) applying a gradually rising positive reset pulse to the Y electrode lines; (b) applying a positive pulse to the red address electrode lines and the blue address electrode lines at an initial stage of the rising of the positive reset pulse; And (c) applying a positive pulse to the green address electrode lines at a later half of the rising of the positive reset pulse, wherein the red address electrode lines, the blue address electrode lines, and the green address electrode are applied. The magnitude of the voltage applied to the lines is the same to prevent low discharge of the green address electrode lines during the reset step.

Description

Method for driving plasma display panel on which pulses having mutually different rising time are applied}

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a waveform diagram of signals applied to electrode lines of a conventional plasma display panel.

2 is an internal perspective view of a three-electrode surface discharge plasma display panel according to the present invention.

3 is a cross-sectional view illustrating one of a plurality of display cells included in the plasma display panel illustrated in FIG. 2.

FIG. 4 is a block diagram of the plasma display panel shown in FIG. 2 and a driving device for driving the same.

FIG. 5 shows a structure of a frame applied to the plasma display panel shown in FIG. 2.

6 is a waveform diagram of signals applied to electrode lines of a plasma display panel according to an exemplary embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

201; A plasma display panel 210; Front glass substrate

211/215; Dielectric layer, 212; Protective layer

213; Rear glass substrate, 214; Discharge space

216r; Red fluorescent layer, 216b; Blue fluorescent layer

216g; Green fluorescent layer, 217; septum

X1 to Xn; X electrode lines, Y1 to Yn; Y electrode lines

AR1-ARm; Red address electrode lines

AB1-ABm; Blue address electrode lines

AG1-AGm; Green address electrode lines

X _na / Y _na ; Transparent electrode lines, X _nb / Y _nb ; Metal electrode lines

411; An address driver 421; X drive

431; Y drive 441; Logic control

451; An image processing unit, SF _{1 to} SF ₈ ; Subfields

Sx1 to Sxn; X electrode drive signals, Sy1 to Syn; Y electrode driving signals

Sar1-Sarm; Red Address Electrode Driving Signals

Sab1-Sabm; Blue address electrode driving signals

Sag1-Sagm; Green address electrode driving signals

The present invention relates to a method of driving a plasma display panel. More particularly, the present invention relates to a red address electrode line and a blue address in which pulses applied to green address electrode lines are reset in a subfield reset step. The present invention relates to a driving method of a plasma display panel which is applied with a difference between a pulse applied to electrode lines and a rise time.

1 is a waveform diagram of signals applied to electrode lines of a conventional plasma display panel. The unit frame applied to the plasma display panel is divided into a plurality of sub-fields for time division gray scale display.

Referring to FIG. 1, the subfield SFn is divided into a reset step Rn, an addressing step An, and a display-sustain step Sn. In FIG. 1, reference numerals Sa1 to Sam denote driving signals applied to the address electrode lines, reference numerals Sx1 to Sxn denote driving signals applied to the X electrode lines, and reference numerals Sy1 to Syn denote the Y electrode lines. Indicates drive signals.

In the reset step Rn, the X electrode driving signals Sx1 to Sxn are maintained at the ground potential Vg for the period t0 to t2 and then rise to the potential Vs for the period t2 to t4. The Y electrode driving signals Sy1 to Syn are maintained at the ground potential Vg during the period t0 to t1, and then rapidly rise to the potential Vs at the time point t1 and then continuously rise to the potential Vset. After rapidly descending to the potential Vs at t2, the voltage is continuously lowered to the ground potential Vg from the time point t3 to the time point t4. The address electrode driving signals Sa1 to San are held at the ground potential Vg.

In the addressing step An, the address electrode driving signals Sa1 to San are applied as pulse signals having a positive potential Va to the selected address electrode lines, and the Y electrode driving signals Sy1 to Syn are ground potentials. It is applied sequentially as scan signals having (Vg). Thus, smooth addressing can be performed. The address electrode driving signals Sa1 to San are applied as the positive potential Va to the address electrode lines corresponding to the display cell selection, and as the ground potential Vg otherwise.

In the display-holding step Sn, the Y electrode driving signals Sy1 to Syn and the X electrode driving signals Sx1 to Sxn are alternately applied as a pulse signal having a potential Vs, so as to correspond to the corresponding addressing step. Discharge for display-holding occurs in display cells in which wall charges have accumulated.

However, in the reset step Rn, since the address electrode driving signals Sa1 to San are applied as the ground potential Vg, ion shock occurs in the phosphors formed in the display cells. In order to prevent this, even when a pulse is applied to the address electrode lines during the reset step Rn, the time that the actual ion bombardment is applied is the green phosphor formed in the green cell, the red phosphor formed in the red cell and blue Since the blue phosphors formed in the (blue) cells are different, low discharge may occur in the green phosphors.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a method of driving a plasma display panel that not only prevents ion bombardment of phosphors formed in display cells, but also prevents low discharge of green phosphors.

The present invention to achieve the above technical problem,

X electrode lines and Y electrode lines are alternately arranged between the substrates and the front substrate and the rear substrate spaced apart from each other to form XY electrode line pairs, and green address electrode lines and red are drawn on the XY electrode line pairs. A method of driving a plasma display panel in which display cells are formed in regions where address electrode lines and blue address electrode lines cross each other, wherein a unit frame applied to the plasma display panel is divided into a plurality of subfields. The fields respectively perform a reset step, an addressing step and a display-hold step, wherein the reset step comprises: (a) applying a gradually rising positive reset pulse to the Y electrode lines; (b) applying a positive pulse to the red address electrode lines and the blue address electrode lines at an initial stage of the rising of the positive reset pulse; And (c) applying a positive pulse to the green address electrode lines at a later half of the rising of the positive reset pulse, wherein the red address electrode lines, the blue address electrode lines, and the green address electrode are applied. The driving method of the plasma display panel is characterized in that the magnitude of the voltage applied to the lines is the same.

Preferably, the positive pulse applied to the green address electrode lines is applied when the rising slope of the positive reset pulse applied to the Y electrode lines is 60 to 90%.

Preferably, a ground voltage is applied to the X electrode lines while a positive reset pulse is applied to the Y electrode lines.

Preferably, the positive reset pulse applied to the Y electrode lines gradually decreases after reaching a predetermined voltage level, and a positive voltage is applied to the X electrode lines while the positive reset pulse is reduced. The ground voltage is applied to the address electrode lines.

According to the present invention, it is possible to prevent low discharge of the green address electrode lines during the reset step.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a perspective view illustrating a three-electrode surface discharge plasma display panel according to the present invention, and FIG. 3 is a cross-sectional view illustrating one of a plurality of display cells included in the plasma display panel shown in FIG. 2. 2 and 3, red address electrode lines AR1 to ARm and blue address are formed between the front and rear glass substrates 210 and 213 of the conventional surface discharge plasma display panel 201. Electrode lines AB1 to ABm, green address electrode lines AG1 to AGm, dielectric layers 211 and 215, Y electrode lines Y1 to Yn, and X electrode lines X1 to Xn. , Red phosphors 216r, blue phosphors 216b, green phosphors 216g, barrier ribs 217, and a magnesium monoxide (MgO) layer 212 as a protective layer are formed.

The red / blue / green address electrode lines AR1 to ARm / AB1 to ABm / AG1 to AGm are formed in a predetermined pattern on the front side of the rear glass substrate 213. The lower dielectric layer 215 is applied to the front of the red / blue / green address electrode lines AR1 to ARm / AB1 to ABm / AG1 to AGm. In front of the lower dielectric layer 215, the partition walls 217 are formed in a direction parallel to the red / blue / green address electrode lines AR1 to ARm / AB1 to ABm / AG1 to AGm. These partitions 217 define a discharge area of each display cell and prevent optical cross talk between each display cell. Red / blue / green fluorescent layers 216r / 216b / 216g are applied between the partitions 217.

The X electrode lines X1 to Xn and the Y electrode lines Y1 to Yn cross the front glass substrate 210 so as to intersect the red / blue / green address electrode lines AR1 to ARm / AB1 to ABm / AG1 to AGm. The back side of) is formed in a uniform pattern, and display cells corresponding to each intersection point are formed. The X electrode lines X1 to Xn and the Y electrode lines Y1 to Yn are transparent electrode lines Xna and Yna made of a transparent conductive material such as indium tin oxide (ITO), and metal electrode lines for increasing conductivity. (Xnb, Ynb) is formed by combining. The front dielectric layer 211 is formed by coating the entire surface on the back of the X electrode lines X1 to Xn and the Y electrode lines Y1 to Yn. A protective layer 212 for protecting the panel 201 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 211. The plasma forming gas is sealed in the discharge space 214.

In the driving method basically applied to such a discharge display panel, a reset step, an addressing step, and a display-sustain step are sequentially performed in the unit subfield. In the reset phase, the charge states of all display cells are uniform. In the addressing step, a predetermined wall voltage is generated in the selected display cells. In the display-holding step, a predetermined alternating voltage is applied to all XY electrode line pairs so that the display cells to which the wall voltage is applied in the addressing step cause display-holding discharges. In the display-holding step, plasma is formed in the discharge space 214 of the selected display cells causing the display-holding discharge, that is, the gas layer, and the fluorescent layer 216 is excited by the ultraviolet radiation to generate light.

FIG. 4 is a block diagram of the plasma display panel shown in FIG. 2 and a driving device for driving the same. Referring to FIG. 4, a typical driving apparatus of the plasma display panel 201 includes an image processor 451, a logic controller 441, an address driver 411, an X driver 421, and a Y driver 431. .

The image processing unit 451 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 441 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 451. The address driver 411 generates a display data signal by processing the address signal S _A among the driving control signals S _A , S _Y , and S _X from the logic controller 441, and generates the display data signal. Applied to the address electrode lines. The X driver 421 processes the X driving control signal S _X from the driving control signals S _A , S _Y , and S _X from the logic controller 441, and applies the X driving control signal S _X to the X electrode lines. The Y driver 431 processes the Y driving control signal S _Y from the driving control signals S _A , S _Y , and S _X from the logic controller 441, and applies the Y driving control signal S _Y to the Y electrode lines.

FIG. 5 shows a structure of a frame applied to the plasma display panel shown in FIG. 2. Referring to FIG. 5, each of the frames is divided into _eight subfields SF ₁ to SF 8 to realize time division gray scale display. In addition, the subfields SF ₁ to SF ₈ are divided into reset steps R ₁ to R ₈ , addressing steps A _{1 to} A ₈ , and display-holding steps S ₁ to S ₈ . do.

The discharge conditions of all the display cells become uniform in the reset steps R ₁ to R ₈ while being suitable for the addressing to be performed in the next step. In the addressing steps A _{1 to} A ₈ , a display data signal is applied to the address electrode lines AR1 to ARm, AB1 to ABm, and AG1 to AGm in FIG. 1 and simultaneously to the Y electrode lines Y1 to Yn. Corresponding scan pulses are applied sequentially. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are generated by the addressing discharge in the corresponding discharge cell, and wall charges are not generated in the discharge cell that is not.

In the display-holding steps S1 to S8, a display-holding pulse is alternately applied to all the Y electrode lines Y1 to Yn and all the X electrode lines X1 to Xn, so that in the corresponding addressing step, Wall charges cause display discharge in the accumulated discharge cells. Therefore, the luminance of the plasma display panel 201 of FIG. 2 is proportional to the length of the display-holding steps S1 to Sn occupying in the unit frame. The length of the display-holding steps S1 to Sn occupying the unit frame is 255T (T is the unit time). Therefore, the gray level of the image can be displayed in 256 steps, including the case where it has never been displayed in the unit frame.

Here, the first sub-field display (SF ₁₎ - time (1T), which is equivalent to ²⁰ holding step (S1) is the second display of the sub-fields (SF ₂₎ -, the holding step (S2) 2 ¹ time (2T) that corresponds to the third sub-field (SF ₃₎ the display of the-hold stage (S2), the time (4T) corresponding to ²² is, in the fourth display of the sub-fields (SF _4)-holding step In operation S4, a time 8T corresponding to 2 ³ is represented, and in the display-maintaining step S5 of the fifth subfield SF ₅ , a time 16T corresponding to 2 ⁴ is represented by a sixth subfield SF _6. In the display-holding step S6 of), the time 32T corresponding to 2 ⁵ , and in the display-holding step S7 of the seventh subfield SF ₇ , the time 64T corresponding to 2 ⁶ , and In the display-holding step S8 of the eighth subfield SF ₈ , a time 128T corresponding to 2 ⁷ is set.

Accordingly, if the subfield to be displayed among the eight subfields SF1 to SF8 is appropriately selected, 256 gray levels can be displayed including all zero (zero) grays not displayed in any of the subfields.

6 is a waveform diagram illustrating signals for describing a method of driving a plasma display panel according to an exemplary embodiment of the present invention. In FIG. 6, the X electrode driving signals Sx1 to Sxn are signals applied to the X electrode lines (X1 to Xn in FIG. 2), and the Y electrode driving signals Sy1 to Syn are Y electrode lines (FIG. The Y driving signals applied to the Y1 to Yn of 2 and the red address electrode driving signals Sar1 to Sarm are the signals applied to the red address electrode lines AR1 to ARm of FIG. 2, and the blue address electrode driving signal. The signals Sab1 to Sabm are applied to the blue address electrode lines (AB1 to ABm in FIG. 2), and the green address electrode driving signals Sag1 to Sagm are the green address electrode lines (AG1 to AGm in FIG. 2). Are the signals that are applied.

The driving method of the plasma display panel 201 of FIG. 2 will be described through operations of the driving signals Sx1 to Sxn, Sy1 to Syn, Sar1 to Sarm, Sab1 to Samm, and Sag1 to Samm shown in FIG. 6. .

During the initial time t0 to t1 of the reset step Rn, the X electrode driving signals Sx1 to Sxn and the Y electrode driving signals Sy1 to Syn and the address electrode driving signals Sar1 to Arm and Sab1 to Samb , Sag1 to Sagm are maintained at the ground potential Vg.

During the wall charge accumulation time t1 to t4 of the reset step Rn, the X electrode driving signals Sx1 to Sxn are kept at the ground potential Vg, and the Y electrode driving signals Sy1 to Syn are positive. It is applied as a polarity reset pulse, i.e., after rising rapidly to the potential Vs, it continuously rises to a higher potential Vset, and the address electrode driving signals Sar1 to Sarm, Sad1 to Sadm, and Sag1 to Sagm are positive. It is applied as a positive pulse having a voltage Va. Accordingly, the X electrode lines (X1 to Xn in FIG. 2) and the Y electrode lines (Y1 to Yn in FIG. 2), and the Y electrode lines (Y1 to Yn in FIG. 2) and the address electrode lines (FIG. 2). Discharge occurs between AR1 to ARm, AB1 to ABm, and AG1 to AGm of the Y electrode lines (Y1 to Yn in FIG. 2) and the address electrode lines (AR1 to ARm, AB1 to ABm, and AG1 to FIG. A lot of negative wall charges are accumulated around AGm), and positive wall charges are accumulated around X electrode lines (X1 to Xn in FIG. 2).

Here, the red address electrode driving signals Sar1 to Sarn and the blue address electrode driving signals Sab1 to Sabn are initially increased when the Y electrode driving signals Sy1 to Syn rise from the potential Vs to the potential Vset. Rises to the positive potential Va. In addition, the green address electrode driving signals Sag1 to Sagn rise to the positive potential Va in the second half of the rise of the Y electrode driving signals Sy1 to Syn from the potential Vs to the potential Vset. Preferably, that is, when the Y electrode driving signals Sy1 to Syn are 60% to 90% of the time taken to reach the potential Vs from the potential Vset, the green address electrode line (Ag1 to Fig. 2). A pulse having a voltage Va is applied to Agm).

In this manner, the reset discharge is applied by applying a positive voltage Va to the address electrode lines AR1 to ARm, AB1 to ABm, and AG1 to AGm in FIG. 2 during the wall charge accumulation time t1 to t4 of the reset step Rn. To prevent ion bombardment of the phosphors (216 of FIG. 2).

In addition, the voltage Va applied to the green address electrode lines AG1 to AGm of FIG. 2 is represented by the red address electrode lines AR1 to ARm of FIG. 2 and the blue address electrode lines AB1 to ABm of FIG. 2. By applying a voltage later than the voltage Va applied thereto, low discharge can be prevented from occurring in the green address electrode lines AG1 to AGm of FIG. 2. In other words, since the green phosphor has negative characteristics, the green phosphor has a characteristic of being discharged at the highest voltage. Accordingly, the voltage Va applied to the green address electrode lines AG1 to AGm of FIG. 2 is represented by the red address electrode lines AR1 to ARm of FIG. 2 and the blue address electrode lines AB1 to ABm of FIG. 2. By applying later than the voltage applied to the voltage Va, the time discharged from the green phosphor and the time discharged from the red phosphor and the blue phosphor become the same, so that the green address electrode lines (AG1 to AGm in FIG. Low discharge does not occur.

During the potential conversion time t4 to t5 of the reset step Rn, the X electrode driving signals Sx1 to Sxn rise from the ground potential Vg to the potential Vs, and the address electrode driving signals Sar1 to Sarm. , Sab1 to Samb, Sag1 to Sagm are lowered from the potential Va to the ground potential Vg, and the Y electrode lines (Y1 to Yn in FIG. 2) are suddenly changed from the potential Vset to the potential Vs. Descend. As described above, since the potentials of the Y electrode driving signals Sy1 to Syn decrease rapidly from the potential Vset to the potential Vs, the Y electrode lines (Y1 to Yn in FIG. 2) and the address electrode lines (FIG. The average voltage between AR1 to ABm of 2 may be reduced to prevent excessive discharge, thereby improving contrast performance of the plasma display panel 201 of FIG. 2.

During the wall charge distribution time t5 to t6 of the reset step Rn, the X electrode driving signals Sx1 to Sxn are kept at the potential Vs, and the address electrode driving signals Sar1 to Sarm, Sab1 to Sabm , Sag1 to Sagm are kept at the ground potential Vg, and the Y electrode driving signals Sy1 to Syn are continuously falling from the potential Vs to the ground potential Vg. As a result, the positive wall charges accumulated in the X electrode lines (X1 to Xn in FIG. 2) disappear, and the Y electrode lines (Y1 to Yn in FIG. 2) and the address electrode lines (AR1 to ARm and AB1 in FIG. 2). The negative wall charges accumulated in ˜ABm, AG1 to AGm) disappear.

In the addressing step An, pulse signals having a positive potential Va are applied to the address electrode lines AR1 to ARm, AB1 to ABm, and AG1 to AGm in FIG. 2, and the Y electrode lines Y1 in FIG. ? N), as the pulse signals of the ground potential Vg are sequentially applied, smooth addressing is performed. The address electrode driving signals Sar1 to Sarm, Sab1 to Samb, and Sag1 to Sagm applied to the address electrode lines AR1 to ARm, AB1 to ABm, and AG1 to AGm in FIG. 2 have positive potential Va to the selected display cells. Is applied as a pulse signal, and is applied as a ground potential Vg to unselected display cells. The Y electrode driving signals Sy1 to Syn having the ground potential Vg are applied to the selected display cells, and the address electrode driving signals Sar1 to Sarm, Sab1 to Samb, Sag1 to Sagm having a positive potential Va. When applied, wall charges are accumulated in the selected display cells by addressing discharge, and wall charges are not accumulated in the unselected display cells.

In the display-hold step Sn, the ground potential Vg is applied to the address electrode lines AR1 to ARm, AB1 to ABm, and AG1 to AGm in FIG. 2, and the Y electrode lines Y1 to Yn in FIG. The display-maintaining discharge is made to the selected display cells by alternating application of pulse signals having a positive potential Vs).

The best embodiments have been disclosed in the drawings and the specification, and the terminology used herein is for the purpose of describing the invention only and is not intended to be limiting of the scope of the invention as defined in the appended claims or claims. Therefore, those skilled in the art will be capable of various modifications and other equivalent embodiments from this, and therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

As described above, according to the present invention, pulses applied to the green address electrode lines AG1 to AGm of FIG. 2 are transferred to the red address electrode lines AR1 to ARm of FIG. 2 and the blue address electrode lines of FIG. 2. By applying later than the pulses applied to AB1 to ABm, not only the ion bombardment of the phosphors 216 of FIG. 2 is prevented, but also the low discharge of the green address electrode lines AG1 to AGm of FIG. 2 is prevented.

Claims (4)

X electrode lines and Y electrode lines are alternately arranged between the substrates and the front substrate and the rear substrate spaced apart from each other to form XY electrode line pairs, and green address electrode lines and red are drawn on the XY electrode line pairs. A method of driving a plasma display panel in which display cells are formed in areas where address electrode lines and blue address electrode lines cross each other, The unit frame applied to the plasma display panel is divided into a plurality of subfields, and each of the subfields performs a reset step, an addressing step, and a display-holding step. The reset step (a) applying a positively rising positive reset pulse to the Y electrode lines; (b) applying a positive pulse to the red address electrode lines and the blue address electrode lines at an initial stage of the rising of the positive reset pulse; And (c) applying a positive pulse to the green address electrode lines in the second half of the rising of the positive reset pulse; And the voltages applied to the red address electrode lines, the blue address electrode lines, and the green address electrode lines are the same. The plasma display panel of claim 1, wherein the positive polarity pulse applied to the green address electrode lines is applied when the rising slope of the positive reset pulse applied to the Y electrode lines is 60 to 90%. Method of driving. The method of claim 1, wherein a ground voltage is applied to the X electrode lines while a positive reset pulse is applied to the Y electrode lines. The method of claim 1, wherein the positive reset pulse applied to the Y electrode lines gradually decreases after reaching a predetermined voltage level, and a positive voltage is applied to the X electrode lines while the positive reset pulse is reduced. And applying a ground voltage to the address electrode lines.

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