KR100615306B1 - Method for driving plasma display panel to stabilize rapidly sustaining discharge - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel for rapidly stabilizing sustain discharge. The present invention is a front substrate and a rear substrate spaced apart from each other, X electrode lines and Y electrode lines are alternately arranged between the substrates to form XY electrode line pairs, the XY electrode line pairs and the address electrode lines intersect. A method of driving a plasma display panel in which display cells are formed in regions where the display cells are formed, the unit frame applied to the plasma display panel is divided into a plurality of subfields, each of which is a reset step, an addressing step, and a display- Performing sustain steps, alternately applying pulses to the X electrode lines and the Y electrode lines during the display-holding step, and applying pulses to the X electrode lines for an initial predetermined time At least a portion of the pulses applied to the Y electrode lines overlap each other. Thus, the sustain discharge is stabilized quickly during the display-hold phase.

Description

Method for driving plasma display panel to stabilize rapidly sustaining discharge

BRIEF DESCRIPTION OF THE DRAWINGS In order to better understand the drawings cited in the detailed description of the invention, a brief description of each drawing is provided.

1 is a waveform diagram of signals applied to a conventional plasma display panel.

2 is an internal perspective view of a three-electrode surface discharge plasma display panel according to the present invention.

3 is a cross-sectional view illustrating one of a plurality of display cells included in the plasma display panel illustrated in FIG. 2.

FIG. 4 is a block diagram of the plasma display panel shown in FIG. 2 and a driving device for driving the same.

FIG. 5 illustrates a structure of a unit frame applied to the plasma display panel shown in FIG. 2.

6 is a waveform diagram of signals for explaining a method of driving a plasma display panel according to the present invention.

<Explanation of symbols for the main parts of the drawings>

201; A plasma display panel 210; Front glass substrate

211,215; Dielectric layer, 212; Protective layer

213; Rear glass substrate, 214; Discharge space

216; Fluorescent layer, 217; septum

X1 to Xn; X electrode lines, Y1 to Yn; Y electrode lines

AR1-ARm; Address electrode lines, X _na , Y _na ; Transparent electrode lines

X _nb , Y _nb ; Metal electrode lines, 411; Address driver

421; X driver 431; Y drive

441; Logic controller 451; Image processor

SF _{1 to} SF ₈ ; Subfields, Sy1-Syn; Y drive signals

Sa1-Sam; Address signals Sx1 to Sxn; X drive signals

P1; Sustain discharge optical waveform

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a plasma display panel, and more particularly, to a method of driving a plasma display panel that rapidly stabilizes sustain discharge occurring during a display-holding step.

1 is a waveform diagram of signals applied to electrode lines of a conventional plasma display panel. The plasma display panel includes X electrode lines, Y electrode lines, and address electrode lines, and display cells are formed at points where they cross each other. Frames including information are applied to the plasma display panel, and each unit frame is divided into a plurality of sub-fields for time division gray scale display.

Referring to FIG. 1, each subfield SFa is divided into a reset step Ra, an addressing step Aa, and a display-sustain step Sa. In FIG. 1, reference numerals Sx1 to Sxn denote X driving signals applied to the X electrode lines of the plasma display panel, and reference numerals Sy1 to Syn denote Y driving signals applied to the Y electrode lines of the plasma display panel. Sam denotes address signals applied to address electrode lines of the plasma display panel.

The operation of the driving signals Sx1 to Sxn, Sy1 to Syn, Sa1 to Sam is schematically described as follows.

During the reset step Ra, the Y drive signals Sy1 to Syn are raised to the potential Vset and then lowered to the ground potential Vg, and the X drive signals Sx1 to Sxn are initially applied to the potential Ve at the time t0. After rising to), it is again applied as the potential Vs at the time point t2, and the address signals Sa1 to San are applied as the ground potential Vg. Accordingly, negative wall charges are accumulated in the Y electrode lines and the X electrode lines, and positive wall charges are reduced in the address electrode lines to prepare for addressing.

During the addressing step Aa, the address signals Sa1 to Sam are applied as pulse signals having a positive potential Va to the address electrode lines, and the Y driving signals Sy1 to Syn are grounded to the Y electrode lines. Smooth addressing is performed by sequentially applying the scan signals having the voltage Vg. The address signals Sa1 to Sam are applied as the positive potential Va to the address electrode lines corresponding to the display cell selection, and the ground potential Vg to the address electrode lines not applicable.

During the display-holding step Sa, the Y drive signals Sy1 to Syn and the X drive signals Sx1 to Sxn are alternately applied as pulse signals having a potential Vs, thus addressing step Aa. In the display cells in which wall charges are accumulated, a sustain discharge for display-holding is generated and maintained.

Here, during the display-holding step Sa, a pulse is applied non-overlapping to the X electrode lines and the Y electrode lines. That is, the pulse applied to the X electrode lines starts to rise when the pulses applied to the Y electrode lines start to fall, and the pulse applied to the Y electrode lines when the pulse applied to the X electrode lines starts to fall. Begins to rise.

The result of measuring the optical waveform generated in the display cell to show the time taken for the sustain discharge to stabilize during the display-maintaining step Sa is shown as the signal P1. As indicated by the signal P1, the time ts1 takes for the sustain discharge to stabilize.

As such, during the display-maintenance step Sa of the conventional plasma display panel, the time ts1 takes a long time for the initial sustain discharge to stabilize by non-overlapping the pulses applied to the Y electrode lines and the X electrode lines. For this reason, the discharge efficiency of the plasma display panel is low.

SUMMARY OF THE INVENTION The present invention solves the problems of the prior art, and provides a method of driving a plasma display panel that shortens the time taken for the initial sustain discharge to stabilize during the display-holding step.

The present invention to achieve the above technical problem

Front and rear substrates spaced apart from each other, and X electrode lines and Y electrode lines are alternately arranged between the substrates to form XY electrode line pairs, and regions where the XY electrode line pairs and the address electrode lines cross each other. A method of driving a plasma display panel having display cells formed thereon, wherein the unit frame applied to the plasma display panel is divided into a plurality of subfields, and each of the subfields includes a reset step, an addressing step, and a display-holding step. And alternately applying pulses to the X electrode lines and the Y electrode lines during the display-holding step, and applying the pulses to the X electrode lines and the Y electrode line for an initial predetermined time. Plastic, characterized in that at least a portion of the pulses applied to the It provides a method of driving a display panel, e.

Preferably, the predetermined time is set as the time taken until the sustain discharge occurring during the display-hold discharge step is stabilized.

Preferably, during the initial predetermined time, the rise times of the pulses applied to the X electrode lines and the fall times of the pulses applied to the Y electrode lines overlap each other, and are applied to the X electrode lines. Fall times of the pulses and rise times of the pulses applied to the Y electrode lines overlap each other.

According to the present invention, the luminance of the plasma display panel is improved.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings denote like elements.

2 is a perspective view illustrating a three-electrode surface discharge plasma display panel according to the present invention, and FIG. 3 is a cross-sectional view illustrating one of a plurality of display cells included in the plasma display panel shown in FIG. 2. 2 and 3, address electrode lines AR1 to ARm, dielectric layers 211 and 215, and Y are formed between the front and rear glass substrates 210 and 213 of the conventional surface discharge plasma display panel 201. Electrode lines Y1 to Yn, X electrode lines X1 to Xn, phosphor 216, partition 217, and magnesium monoxide (MgO) layer 212 as a protective layer are provided.

The address electrode lines AR1 to ARm are formed in a predetermined pattern on the front side of the rear glass substrate 213. The lower dielectric layer 215 is entirely coated on the front side of the address electrode lines AR1 to ARm. The barrier ribs 217 are formed in a direction parallel to the address electrode lines AR1 to ARm in front of the lower dielectric layer 215. The partition walls 217 function to partition the discharge area of each display cell and prevent optical cross talk between each display cell. The fluorescent layer 216 is applied between the partitions 217.

The X electrode lines X1 to Xn and the Y electrode lines Y1 to Yn are formed in a predetermined pattern on the back of the front glass substrate 210 so as to intersect the address electrode lines AR1 to ARm, and the X electrode lines And the gap dk between the X1 to Xn and Y electrode lines Y1 to Yn is 200 [um] or more. Each intersection sets a corresponding display cell. The X electrode lines X1 to Xn and the Y electrode lines Y1 to Yn are transparent electrode lines Xna and Yna made of a transparent conductive material such as indium tin oxide (ITO), and metal electrode lines for increasing conductivity. (Xnb, Ynb) is formed by combining. The front dielectric layer 211 is formed by coating the entire surface on the back of the X electrode lines X1 to Xn and the Y electrode lines Y1 to Yn. A protective layer 212 for protecting the panel 201 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 211. The plasma forming gas is sealed in the discharge space 214.

In the driving method basically applied to the plasma display panel 201, the reset step, the addressing step, and the display-sustain step are sequentially performed in the unit subfield. In the reset phase, the charge states of all display cells are uniform. In the addressing step, a predetermined wall voltage is generated in the selected display cells. In the display-holding step, a predetermined alternating voltage is applied to all XY electrode line pairs so that the display cells to which the wall voltage is applied in the addressing step cause display-holding discharges. In the display-holding step, plasma is formed in the discharge space 214 of the selected display cells causing the display-holding discharge, that is, the gas layer, and the fluorescent layer 216 is excited by the ultraviolet radiation to generate light.

FIG. 4 is a block diagram of the plasma display panel shown in FIG. 2 and a driving device for driving the same. Referring to FIG. 4, a typical driving apparatus of the plasma display panel 201 includes an image processor 451, a logic controller 441, an address driver 411, an X driver 421, and a Y driver 431. .

The image processing unit 451 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 441 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 451. The address driver 411 generates the display data signal by processing the address signal S _A among the driving control signals S _A , S _Y , and S _X from the logic controller 441, and generates the display data signal. Is applied to the address electrode lines (AR1 to ARm in FIG. 2). The X driver 421 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the logic controller 441 to process the X electrode lines (X1 to Xn in FIG. 2). ) Is applied. The Y driver 431 processes the Y drive control signal S _Y among the drive control signals S _A , S _Y , and S _X from the logic controller 441 to process the Y electrode lines (Y1 to Yn in FIG. 2). ) Is applied.

FIG. 5 illustrates a structure of a unit frame applied to the plasma display panel shown in FIG. 2. Referring to FIG. 5, each of the unit frames is divided into _eight subfields SF ₁ to SF 8 to realize time division gray scale display. Further, the subfields SF ₁ to SF ₈ are divided into reset steps R ₁ to R ₈ , addressing steps A _{1 to} A ₈ , and display-holding steps S ₁ to S ₈ . do.

In the reset steps R ₁ to R ₈ , the discharge conditions of all the display cells become uniform and at the same time are adapted to the addressing to be performed in the next step.

In the addressing steps A _{1 to} A ₈ , a display data signal is applied to the address electrode lines AR1 to ARm in FIG. 2 and a scan pulse corresponding to the Y electrode lines Y1 to Yn in FIG. It is applied sequentially. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are generated by the addressing discharge in the corresponding discharge cell, and wall charges are not generated in the discharge cell that is not.

In the display-holding steps S ₁ -S ₈ , the display-holding pulses are alternately applied to all the Y electrode lines (Y1 to Yn in FIG. 2) and all the X electrode lines (X1 to Xn in FIG. 2). Is applied, causing display discharge in discharge cells in which wall charges have accumulated in a corresponding addressing step. The luminance of the plasma display panel 201 of FIG. 2 is proportional to the length of the display-holding steps S ₁ to S ₈ occupy in the unit frame. The length of the display-holding steps S ₁ -S ₈ occupying a unit frame is 255T (T is unit time). Therefore, it can be displayed in 256 gray scales, even if it is not displayed once in a unit frame.

Here, in the display-holding step S ₁ of the first subfield SF ₁ , a time 1T corresponding to 2 ⁰ is present, and in the display-holding step S _{2 of} the second subfield SF ₂ . In the display-maintaining step S ₃ of the third subfield SF ₃ , the time 2T corresponding to 2 ¹ is represented by the time 4T corresponding to 2 ² , and the display of the fourth subfield SF ₄ . In the holding step S ₄ , a time 8T corresponding to 2 ^3, in the display-holding step S ₅ of the fifth subfield SF ₅ , a time 16T corresponding to 2 ⁴ , In the display-holding step S ₆ of the subfield SF ₆ , a time 32T corresponding to 2 ⁵ corresponds to 2 ⁶ in the display-holding step S ₇ of the seventh subfield SF ₇ . The time 64T and the time 128T corresponding to 2 ⁷ are set in the display-holding step S ₈ of the eighth subfield SF ₈ , respectively.

Accordingly, if a subfield to be displayed is appropriately selected from the _eight subfields SF ₁ to SF ₈ , display of 256 gray levels may be performed including all zero (zero) gray levels that are not displayed on any of the subfields. .

6 is a waveform diagram of signals for explaining a method of driving a plasma display panel according to the present invention. In FIG. 6, the signals Sy1 to Syn are Y driving signals applied to the Y electrode lines (Y1 to Yn in FIG. 2), and the signals Sx1 to Sxn are X electrode lines (X1 to Xn in FIG. 2). Are X driving signals applied to the signal lines, and the signals Sa1 to Sam are address signals applied to the address electrode lines AR1 to ARm of FIG. 2.

A driving method of the plasma display panel 201 of FIG. 2 illustrated in FIG. 6 will be described with reference to FIGS. 2 through 5.

During the initial time t0 to t1 of the reset step Ra, both the Y driving signals Sy1 to Syn and the address signals Sa1 to Sa480 are applied as the ground potential Vg, and the X driving signals Sxa Sxn) is applied as the potential Ve. Accordingly, the positive wall charges accumulated in the X electrode lines (X1 to Xn in FIG. 2) during the previous display-maintenance step are reduced.

During the wall charge accumulation time t1 to t2 of the reset step Ra, the Y drive signals Sy1 to Syn are rapidly increased to the positive potential Vs and then continuously rise to the high voltage Vset, and the X drive signal And Sx1 to Sxn and address signals Sa1 to San are held at ground potential Vg. Accordingly, between the Y electrode lines (Y1 to Yn in FIG. 2) and the X electrode lines (X1 to Xn in FIG. 2), and the Y electrode lines (Y1 to Yn in FIG. 2) and the address electrode lines (FIG. Strong discharge occurs between AR1 to ARm of 2, so that a lot of negative wall charges are accumulated in the Y electrode lines (Y1 to Yn in FIG. 2), and the X electrode lines (X1 to Xn in FIG. 2) and the address electrode Positive wall charges are accumulated in the lines AR1 to ARm in FIG. 2.

During the wall charge distribution time t2 to t3 of the reset step Ra, the Y drive signals Sy1 to Syn are rapidly reduced to the potential Vs and then continuously reduced to the ground potential Vg, and the X drive signals (Sx1 to Sxn) are applied as the positive potential Ve, and the address signals Sa1 to Sa480 are continuously applied as the ground potential Vs. Then, a weak discharge is generated between the X electrode lines (X1 to Xn in FIG. 2) and the Y electrode lines (Y1 to Yn in FIG. 2), and the negative charge accumulated in the Y electrode lines (Y1 to Yn in FIG. 2). Wall charges are greatly reduced, and weak negative wall charges are accumulated in the X electrode lines (X1 to Xn in FIG. 2). Also, between the address electrode lines AR1 to ARm in FIG. 2 and the Y electrode lines Y1 to Yn in FIG. 2 and the address electrode lines AR1 to ARm in FIG. 2 and the X electrode lines in FIG. The positive wall charges accumulated in the address electrode lines (AR1 to ARm in Fig. 2) disappear due to the discharge between X1 to Xn. Therefore, the wall potential of the X electrode lines (X1 to Xn in FIG. 2) is lower than the wall potential of the address electrode lines (AR1 to ARm in FIG. 2), and the wall of the Y electrode lines (Y1 to Yn in FIG. 2). It will be higher than the potential. As a result, the addressing voltage Va-Vg required for the counter discharge between the selected address electrode lines and the Y electrode lines in the subsequent addressing step Aa is lowered.

In the addressing step Aa, pulses having a positive potential Va are applied to the address electrode lines AR1 to ARm in FIG. 2, and the ground potential Vg to the Y electrode lines Y1 to Yn in FIG. 2. As pulses with s are applied sequentially, an addressing operation is performed. At this time, the address signals Sa1 to Sam are applied to the unselected display cells as the ground potential Vg, and the Y driving signals Sy1 to Syn are lower than the potential Vs to the unselected display cells. Is applied as (Vsch). Accordingly, negative wall charges are accumulated in the X electrode lines (X1 to Xn in FIG. 2), positive wall charges are accumulated in the Y electrode lines (Y1 to Yn in FIG. 2), and address electrode lines (FIG. 2). AR1 to ARm have a smaller number of negative wall charges than X electrode lines (X1 to Xn in FIG. 2).

During the display-holding phase Sa, the Y drive signals Sy1 to Syn and the X drive signals Sx1 to Sxn are alternately applied as positive pulses having the voltages Vs and Ve, thereby In the corresponding addressing step, sustain discharge for display-holding occurs in display cells in which wall charges have accumulated.

During the display-holding step Sa, pulses are alternately applied to the X electrode lines (X1 to Xn in FIG. 2) and the Y electrode lines (Y1 to Yn in FIG. 2). At this time, the pulses applied to the X electrode lines (X1 to Xn in FIG. 2) and the Y electrode lines (Y1 to Yn in FIG. 2) are overlapped with each other during an initial predetermined time ts2. That is, while the pulses applied to the Y electrode lines (Y1 to Yn in FIG. 2) rise to the potential level Vs, the pulses applied to the X electrode lines (X1 to Xn in FIG. 2) are ground level Vg. And the pulse applied to the X electrode lines (X1 to Xn in FIG. 2) becomes the potential level (W) while the pulse applied to the Y electrode lines (Y1 to Yn in FIG. 2) falls to the ground level Vg. Rise to Vs).

This process is repeated continuously for a predetermined time ts2, that is, until the sustain discharge is stabilized.

After the predetermined time ts2 has passed, the pulses applied to the X electrode lines (X1 to Xn in FIG. 2) and the Y electrode lines (Y1 to Yn in FIG. 2) are not overlapped. That is, after the pulse applied to the Y electrode lines (Y1 to Yn in FIG. 2) drops from the potential level Vs to reach the ground potential Vg, the pulses are applied to the X electrode lines (X1 to Xn in FIG. 2). The applied pulse starts to rise to the potential level Ve at the ground potential Vg, and the pulse applied to the X electrode lines (X1 to Xn in FIG. 2) falls at the potential level Ve so that the ground potential Vg is reached. After reaching, the pulse applied to the Y electrode lines (Y1 to Yn in FIG. 2) starts to rise from the ground potential Vg to the potential level Vs.

The predetermined time ts2 is set as the time taken until the sustain discharge occurring in the display cells is stabilized during the display-holding step Sa.

The result of measuring the optical waveform generated in the display cell in order to know the time taken for the sustain discharge to stabilize during the display-holding step Sa is shown as the signal P2. As shown in the signal P2, the time ts2 takes for the sustain discharge to stabilize is very short compared to the conventional time (ts1 in Fig. 1).

In this way, the pulses are applied to the Y electrode lines (Y1 to Yn in FIG. 2) and the X electrode lines (X1 to Xn in FIG. 2) by overlapping the pulses during the initial predetermined time ts2 of the display-holding step Sa. By doing so, the time ts2 for stabilizing the sustain discharge is shortened.

Here, if it contributes to the stabilization of sustain discharge, the superimposed waveform may be designed to be carried out at the beginning, the middle, or the end of the display-maintenance step Sa. It is also possible to use most of the superimposed waveforms and to add a small amount of non-overlapping waveforms.

The best embodiments have been disclosed in the drawings and the specification, and the terminology used herein is for the purpose of describing the invention only and is not intended to be limiting of the scope of the invention as defined in the appended claims or claims. Therefore, those skilled in the art will be capable of various modifications and other equivalent embodiments from this, and therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

 According to the present invention, the Y electrode lines (Y1 to Yn in FIG. 2) and the X electrode lines (X1 to Xn in FIG. 2) during the initial predetermined time ts2 of the display-holding step Sa of each subfield. By superimposing the pulses applied to), the time ts2 taken for the sustain discharge to stabilize is shortened. Thus, the discharge efficiency of the plasma display panel 201 of FIG. 2 is improved, and quality problems that may be caused by the weak discharge are eliminated.

Claims (4)

Front and rear substrates spaced apart from each other, and X electrode lines and Y electrode lines are alternately arranged between the substrates to form XY electrode line pairs, and regions where the XY electrode line pairs and the address electrode lines cross each other. A method of driving a plasma display panel on which display cells are formed, The unit frame applied to the plasma display panel is divided into a plurality of subfields, and each of the subfields performs a reset step, an addressing step, and a display-holding step. During the display-holding step, pulses are alternately applied to the X electrode lines and the Y electrode lines, and pulses are applied to the X electrode lines and the Y electrode lines during an initial predetermined time. At least some of the pulses overlap each other. The method of driving a plasma display panel according to claim 1, wherein the predetermined time is a time taken until the sustain discharge occurring during the display-sustain discharge step is stabilized. The method of claim 1, wherein the pulses applied to the X electrode lines and the Y electrode lines are non-overlapping after the predetermined time. The method of claim 1, wherein, during the initial predetermined time, rise times of pulses applied to the X electrode lines and fall times of pulses applied to the Y electrode lines overlap each other, The falling time of the pulses to be applied and the rise time of the pulses applied to the Y electrode lines overlap each other.

Images