KR100537610B1 - Method of driving plasma display panel wherein frequency of display sustain pulses varies - Google Patents

Abstract

The present invention provides an initialization step of uniformizing the state of charge of display cells to be driven, an address step of forming wall charges of a predetermined voltage only in display cells to be subjected to display discharge, and wall charge by applying an alternating pulse to all display cells. Display-holding step of performing display discharge only in the display cells in which the cells are formed, in the unit subfield, and dividing the unit frame into a plurality of subfields to give the number of pulses of the display-holding step allocated to each subfield. The time division driving is performed, but a pause time proportional to the number of display cells performing display discharge in a unit frame is a driving method of the plasma display panel. Here, the frequency is lowered while the number of pulses of the display-holding step allocated to the subfield immediately before the pause time is not changed, so that the display-holding step assigned to the subfield immediately before the pause time is extended to the pause time. .

Description

Method of driving plasma display panel wherein frequency of display sustain pulses varies}

The present invention relates to a method of driving a plasma display panel, and more particularly, by dividing a unit frame into a plurality of subfields and time-division driving by the number of pulses of the display-holding step allocated to each subfield. The present invention relates to a method of driving a plasma display panel in which a downtime proportional to the number of display cells performing display discharge in a unit frame is present in the unit frame.

1 shows a structure of a conventional three-electrode surface discharge plasma display panel. FIG. 2 shows an example of one display cell of the panel of FIG. 1. 1 and 2, between the front and rear glass substrates 10 and 13 of the conventional surface discharge plasma display panel 1, the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm ), dielectric layers 11 and 15, Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), fluorescent layer 16, The partition 17 and the magnesium monoxide (MgO) layer 12 as a protective layer are provided.

The address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is entirely applied in front of the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . These partitions 17 function to partition the discharge area of each display cell and prevent optical cross talk between each display cell. The fluorescent layer 16 is formed between the partition walls 17.

The X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) are the address electrode lines (A _R1 , A _G1 , ..., A _Gm , A _Bm ) is formed in a predetermined pattern on the back of the front glass substrate 10 to be orthogonal to each other. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) is a transparent electrode line of a transparent conductive material such as indium tin oxide (ITO) or the like (FIG. 2). X _na , Y _na ) and a metal electrode line (X _nb , Y _nb of FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

The driving method generally applied to such a plasma display panel is a method in which the initialization, address, and display-maintaining steps are sequentially performed in the unit sub-field. In the initialization step, the charge states of the display cells to be driven are made uniform. In the address step, the charge state of display cells to be selected and the charge state of display cells not to be selected are set. In the display-holding step, display discharge is performed in the display cells to be selected. At this time, a plasma is formed from the plasma forming gas of the display cells that perform display discharge, and the fluorescent layer 16 of the display cells is excited by ultraviolet radiation from the plasma to generate light.

Here, since the unit sub-fields are included in the unit frame, the desired gray level can be displayed by the display-hold times of each sub-field.

Referring to FIG. 3, a typical driving device of the plasma display panel (1 of FIG. 1) may include an image processor 66, a controller 62, an address driver 63, an X driver 64, and a Y driver 65. Include. The image processing unit 66 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The controller 62 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 66. The address driver 63 processes the address signal S _A among the driving control signals S _A , S _Y , and S _X from the controller 62 to generate a display data signal, and generates the generated display data signal. Applied to the address electrode lines. The X driving unit 64 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the control unit 62, and applies the X driving control signal S _X to the X electrode lines. The Y driver 65 processes the Y driving control signal S _Y among the driving control signals S _A , S _Y , and S _X from the controller 62 and applies the Y driving control signal S _Y to the Y electrode lines.

FIG. 4 shows a conventional address-display separation driving method for the Y electrode lines Y ₁ ,..., Y _n of the plasma display panel 1 of FIG. 1. Referring to FIG. 4, a unit frame is divided into eight subfields SF1,..., SF8 to realize time division gray scale display. Here, the idle time T _ID is proportional to the number of display cells performing display discharge in the unit frame. For example, there is a pause time T _ID proportional to the load rate of the unit frame. Here, the load ratio of the unit frame is a ratio of the number of display cells performing display discharge in the unit frame with respect to the total number of display cells of the plasma display panel 1. The reason why the idle time T _ID is present is to protect the plasma display panel 1 from excessive driving power.

Each subfield SF1, ..., SF8 is divided into address periods A1, ..., A8 and display-hold periods S1, ..., S8.

In the initial time of each address period A1, ..., A8, an initialization step is performed to make the charge state of the display cells to be driven uniform. In the main address period following the progress of this initial time, the display data signal is applied to the address electrode lines (A _R1 , A _G1 , ..., A _Gm , A _{Bm in} FIG. 1) and at the same time, each Y electrode line Y Scan pulses corresponding to ₁ , ..., Y _n ) are sequentially applied. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are formed by the address discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

In each display-hold period S1, ..., S8, all Y electrode lines Y ₁ , ..., Y _n and all X electrode lines X ₁ , ..., X _n The display discharge pulses are alternately applied, causing display-maintaining discharge in discharge cells in which wall charges are formed in corresponding address periods A1, ..., A8. Therefore, the luminance of the plasma display panel is proportional to the length of the display-hold periods S1, ..., S8 occupied in the unit frame. The length of the display-hold periods S1, ..., S8 occupying a unit frame is 255T (T is unit time). Therefore, it can be displayed in 256 gray levels, including the case where it is not displayed once in a unit frame.

Here, the time 1T corresponding to 2 ⁰ in the display-hold period S1 of the first subfield SF1 corresponds to 2 ¹ in the display-hold period S2 of the second subfield SF2. Time 2T corresponds to 2 ² in the display-hold period S3 of the third subfield SF3 and ² in the display-hold period S4 of the fourth subfield SF4. ^The time 8T corresponding to ³ corresponds to the time 16T corresponding to 2 ⁴ in the display-hold period S5 of the fifth subfield SF5, and the display-hold period of the sixth subfield SF6. In S6), the time 32T corresponding to 2 ⁵ , the display-maintenance period S7 of the seventh subfield SF7 includes the time 64T corresponding to 2 ⁶ , and the time of the eighth subfield SF8. In the display-hold period S8, a time 128T corresponding to 2 ⁷ is set, respectively.

Accordingly, when the subfield to be displayed among the 8 subfields is appropriately selected, it can be seen that display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

According to the above-described address-display separation driving method, since the time domains of the subfields SF1, ..., SF8 are separated from each other in the unit frame, the address period and the address period of each subfield SF1, ..., SF8 are separated. The time domain of the display-hold period is also separated from each other. Therefore, in the address period, after each XY electrode line pair has been addressed, it has to wait until all other XY electrode line pairs are addressed. As a result, the time period occupied by the address period for each subfield becomes longer, and thus the display-maintenance period becomes relatively short. Therefore, the luminance of light emitted from the plasma display panel is relatively low. In order to remedy this problem, a known method is an Address-While-Display driving method as shown in FIG.

FIG. 5 shows a conventional Address-While-Display driving method for the Y electrode lines Y ₁ ,..., Y _n of the plasma display panel 1 of FIG. 1. Referring to FIG. 5, a unit frame is divided into _eight subfields SF ₁ ,..., SF ₈ for time division gray scale display. Here, each unit subfield overlaps each other based on the driven Y electrode lines Y ₁ ,..., Y n to form a unit frame. Therefore, since all subfields SF ₁ , ..., SF ₈ exist at all time points, an address time slot is set between each display discharge pulse to perform each address step. Of course, the idle time T _ID is proportional to the number of display cells performing display discharge in the unit frame. The reason is as described above.

Initialization, address and display-hold steps are performed in each subfield, and the time allocated to each subfield is determined by the display discharge time corresponding to the gray scale. For example, in the case of displaying 256 gray levels in frame units as 8-bit image data, if a unit frame (typically 1/60 second) consists of 255 units of time, driving is performed according to the image data of the least significant bit. The first subfield SF ₁ is 1 (2 ⁰ ) unit time, the second subfield SF ₂ is 2 (2 ¹ ) unit time, and the third subfield SF ₃ is 4 (2 ² ) unit time. Time, the fourth subfield SF ₄ is 8 (2 ³ ) unit time, the fifth subfield SF ₅ is 16 (2 ⁴ ) unit time, and the sixth subfield SF ₆ is 32 (2 ⁵ ) The unit time, the seventh subfield SF ₇ is 64 (2 ⁶ ) unit time, and the eighth subfield SF ₈ driven according to the image data of the most significant bit is 128 (2 ⁷ ) units. Each has a time. That is, since the sum of the unit times allocated to each subfield is 255 unit times, 255 gray scale display is possible, and when gray scales in which no display discharge is performed in any subfield are included, 256 gray scale display is possible.

FIG. 6 shows driving signals at display-hold time S8 and idle time T _{ID of} the eighth subfield SF8 in the conventional address-display separation driving method of FIG. 4. . In FIG. 6, reference numeral S _{X1 ..Xn} denotes an X electrode driving signal applied to all X electrode lines (X ₁ ,..., X _{n in} FIG. 1), and S _Y1 to S _Yn denote respective Y electrode lines. Y electrode driving signals applied to (Y ₁ ,..., Y _{n in} FIG. 1), V _S denotes a sustain discharge voltage, and V _G denotes a ground voltage, respectively.

Referring to FIG. 6, in the display-hold time S8, the display room is displayed on all Y electrode lines Y ₁ ,..., Y _n and all X electrode lines X ₁ ,..., X _n . Dedicated pulses are alternately applied, causing display discharge in discharge cells in which wall charges are formed in the address period A8. In the subsequent dwell time T _ID , the ground voltage V _G is applied to all of the Y electrode lines Y ₁ , ..., Y _n and all of the X electrode lines X ₁ , ..., X _n . Applied, no discharge occurs.

As described with reference to FIGS. 4 to 6, according to the conventional driving method of suppressing excessive power of the plasma display panel by the idle time, no discharge occurs in the idle time. Accordingly, since some of the wall charges and the space charges present in the respective display cells disappear at rest time, there is a problem that the initialization operation of the sub-field immediately after the rest time is not stable and the accuracy of addressing is inferior.

SUMMARY OF THE INVENTION An object of the present invention is a driving method for suppressing excessive power of a plasma display panel by an idle time, wherein the initialization operation of a sub-field immediately after an idle time is stabilized so that an accuracy of addressing can be increased. To provide.

It is still another object of the present invention to provide a driving method for suppressing excessive power of a plasma display panel by an idle time, wherein the plasma display panel can be effective for a plasma display apparatus without a heat radiating fan by effectively reducing the amount of heat generated from the driving circuit. It is to provide a driving method.

The present invention for achieving the above object is an initialization step of uniformizing the charge state of the display cells to be driven, an address step to form wall charges of a predetermined voltage only in the display cells to perform the display discharge, and an alternating pulse in all the display cells The display-holding step of performing display discharge only in the display cells in which the wall charges are formed by applying a is performed in the unit subfield, and divides the unit frame into a plurality of subfields and assigns the display to each subfield. A time division driving is performed by the number of pulses in the maintenance step, but a pause time proportional to the number of display cells performing display discharge in a unit frame is present in the unit of the plasma display panel. Here, the frequency of the display-maintenance step allocated to the subfield immediately before the idle time is not changed, and the frequency is lowered, so that the display-maintenance step allocated to the subfield immediately before the idle time is the idle time. Extended to

Accordingly, in the driving method of suppressing excessive power of the plasma display panel by the idle time, the following effects can be obtained.

First, since the frequency is lowered while the number of pulses of the display-holding step is not changed, the display-holding step is extended to the downtime, so that the pause without affecting power suppression by the downtime. Sustained display-keeping discharge can be performed in time. Accordingly, since the wall charges and the space charges are sufficiently present in the respective display cells immediately after the idle time, the initialization operation of the sub-field immediately after the idle time is stabilized, so that the accuracy of addressing can be increased.

Second, since the frequency is lowered while the number of pulses in the display-holding step is not changed, the switching frequency of the driving circuit is lowered in the display-holding step. Accordingly, the amount of heat generated from the driving circuit can be effectively reduced without affecting the gradation display, and thus it can be effective for a plasma display apparatus without a heat radiating fan.

Hereinafter, embodiments according to the present invention will be described in detail.

FIG. 7 illustrates an address-display separation driving method of the present invention with respect to the Y electrode lines Y ₁ ,..., Y _n of the plasma display panel 1 of FIG. 1. FIG. 8 shows the Address-While-Display driving method of the present invention for the Y electrode lines Y ₁ ,..., Y _n of the plasma display panel 1 of FIG. 1. 9 shows driving signals according to the address-display separation driving method of the present invention.

Referring to FIGS. 7 to 9, the present invention provides an initialization step (PR) of uniformizing the state of charge of display cells to be driven, and an address step (PA) of forming wall charges of a predetermined voltage only in display cells to perform display discharge. ), And the display-holding step (S1 to S8, S _N ) for performing display discharge only in the display cells in which wall charges are formed by applying an alternating pulse to all the display cells, the unit subfields SF1 to SF8, SF _1. To SF ₈ , SF _N , SF _{N + 1} ). The unit frame is divided into a plurality of subfields, and time division driving is performed by the number of pulses of the display-holding steps S1 to S8 and S _N assigned to each subfield. In addition, an idle time T _ID is proportional to the number of display cells performing display discharge in a unit frame. Here, the frequency is lowered while the number of pulses of the display-holding steps S8 and S _N allocated to the subfields SF8, SF ₈ , SF _N immediately before the idle time T _ID is not changed, so that the idle time is carried out extends to the stop time (T _ID) holding step _{(S8, S N) - (} T ID) of the display assigned to the subfield immediately before.

7 and 8 are the same as those of the conventional driving method described above with reference to FIGS. 4 and 5 except for the features of the present invention, and thus description thereof is omitted.

When the driving signals of FIG. 9 are applied to the driving method of FIG. 7, SF _N of FIG. 9 corresponds to the eighth subfield SF8 of FIG. 7, and SF _{N + 1} of FIG. 9 corresponds to the first sub-frame of the next frame. Corresponds to field SF1. Of course, A _N of FIG. 9 corresponds to the address period A8 of the eighth subfield SF8 of FIG. 7, and S _N of FIG. 9 corresponds to the display-hold period of the eighth subfield SF8 of FIG. 7. S8). However, the idle time T _ID may be set at a start time or an intermediate time of a unit frame in some cases.

In FIG. 9, reference numeral S _{AR1 ..ABm} denotes a drive signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 ..Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to. FIG. 10 illustrates a wall charge distribution of one display cell at a point in time after a gradual rising voltage is applied to the Y electrode lines Y ₁ ,... Y _n in the initialization period PR of FIG. 9. FIG. 11 illustrates a wall charge distribution of one display cell at the end of the initialization period PR of FIG. 9. 10 and 11, the same reference numerals as used in FIG. 2 indicate objects of the same function.

9, in the initialization period (PR) of the units of the sub-fields (SF _N, SF _{N + 1),} ground voltage, the voltage applied to the first to the X electrode lines _{(X 1, ..., X n} ) ( V _G ) is continuously raised from the second voltage V _S to, for example, 155 volts (V). Here, the ground voltage V _G is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, between the X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), and the X electrode lines (X ₁ , ..., X) A weak discharge occurs between _n ) and the address electrode lines A ₁ , ..., A _m , and negative wall charges are formed around the X electrode lines X ₁ , ..., X _n . .

Next, the voltage applied to the Y electrode lines Y ₁ ,..., Y _n is third from the second voltage V _S , for example, from 155 volts V to a second voltage than the second voltage V _S. The highest voltage V _SET + V _{S that} is as high as the voltage V _SET is continuously raised to, for example, 355 volts (V). Here, the ground voltage V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , A weaker discharge occurs between ..., Y _n ) and the address electrode lines A _R1 , ..., A _Bm . Here, Y electrode lines _{(Y 1, ..., Y n} ) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _The reason why the discharge between _n ) and the X electrode lines (X ₁ , ..., X _n ) becomes stronger is that the negative wall charges around the X electrode lines (X ₁ , ..., X _n ) Because they were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 10).

Next, in the state where the voltage applied to the X electrode lines X ₁ ,..., X _n is maintained at the second voltage V _S , the Y electrode lines Y ₁ ,..., Y _n The voltage applied to) is continuously lowered from the second voltage V _S to the ground voltage V _G. Here, the ground voltage V _G is applied to the address electrode lines A _R1 ,..., A _Bm . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around..., Y _n ) move around the X electrode lines X ₁ ,..., X _n (see FIG. 11). Further, the address electrode lines (A _R1, ..., A _Bm) is so applied with a ground voltage (V _G), the address electrode lines are positive wall charges around the (A _R1, ..., A _Bm) Slightly increased.

Thus, the in the subsequent main address period (PA), an address is applied to the display data signal to the electrode line, the second voltage (V _S) lower fourth voltage (V _SCAN) to bias the Y-electrode line than the (Y _As the scan signals of the ground voltage V _G are sequentially applied to ₁ , ..., Y _n ), smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , ..., A _Bm is applied with the positive address voltage V _A when the display cell is selected and the ground voltage V _G when the display cell is not selected. do. Accordingly, when the display data signal of the positive address voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, wall charges are formed by the address discharge in the corresponding display cell. Wall charges do not form. Here, the second voltage (V _S) on to the more accurate and efficient address discharge, the X electrode lines (X _1, ... X _n) applied.

Subsequent display-sustain period (S _N) in, all the Y electrode lines (Y _1, ... Y _n) and the X-electrode line of the second voltage (V _S) to (X _1, ... X _n) Display-hold pulses are alternately applied, causing discharge for display-hold in display cells in which wall charges are formed in the corresponding address period PA. Here, the frequency is lowered while the number of pulses of the display-maintaining step S _N allocated to the subfield SF _N just before the idle time T _ID is not changed, so that the sub immediately before the idle time T _ID is reduced. The display-holding step S _N assigned to the field is performed extended to the idle time T _ID .

For this purpose, the number of pulses of the display-hold time S _N that have already been set is m (sum of the number of pulses commonly applied to the X electrode lines and the number of pulses commonly applied to the Y electrode lines). If, stop time (T _ID) of the display assigned to the sub-fields (SF _N) just before - the width T _wIDTH is equation 1 below, which will be applied during the sustain period (S _N) and stop time (T _ID) unit pulse Can be obtained.

Therefore, a period T _S, in which one pulse is applied to all of the X electrode lines and the Y electrode lines, respectively, may be obtained by Equation 2 below as 2 (T _WIDTH ).

Therefore, the frequency f _{S, which} is the inverse of the period T _S , can be obtained by Equation 3 below.

That is, the frequency f _S from Equation 3 in the state in which the number m of pulses of the display-holding step S _N allocated to the subfield SF _N immediately before the idle time T _ID is not changed. is applied, the stop time (T _ID) assigned to the subfield immediately before the display - a holding step (S _N) is carried out extends to the stop time (T _ID).

As described above, according to the driving method according to the present invention, in the driving method for suppressing excessive power of the plasma display panel by the idle time, the following effects can be obtained.

First, since the frequency is lowered while the number of pulses of the display-holding step is not changed, the display-holding step is performed to extend the downtime, so that the continuous display at the downtime without affecting the power suppression by the downtime- Sustained discharge can be performed. Accordingly, since the wall charges and the space charges are sufficiently present in the respective display cells immediately after the idle time, the initialization operation of the sub-field immediately after the idle time can be stabilized and the accuracy of addressing can be increased.

Second, since the frequency is lowered while the number of pulses in the display-holding phase is not changed, the switching frequency of the drive circuit in the display-holding phase is lowered. As a result, the amount of heat generated from the driving circuit can be effectively reduced without affecting the gradation display, which can be effective for a plasma display apparatus without a heat radiating fan.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

1 is a perspective view showing an internal structure of a conventional three-electrode surface discharge plasma display panel.

FIG. 2 is a cross-sectional view illustrating an example of one display cell of the panel of FIG. 1.

3 is a block diagram illustrating a conventional driving device of the plasma display panel of FIG. 1.

FIG. 4 is a timing diagram illustrating a conventional address-display separation driving method for Y electrode lines of the plasma display panel of FIG. 1.

FIG. 5 is a timing diagram illustrating a conventional Address-While-Display driving method for the Y electrode lines of the plasma display panel of FIG. 1.

FIG. 6 is a timing diagram illustrating driving signals at display-hold time and idle time of an eighth subfield in the conventional address-display separation driving method of FIG. 4.

FIG. 7 is a timing diagram illustrating an address-display separation driving method of the present invention for the Y electrode lines of the plasma display panel of FIG. 1.

8 is a timing diagram illustrating an address-display-display driving method of the present invention for the Y electrode lines of the plasma display panel of FIG. 1.

9 is a timing diagram showing driving signals according to the address-display separation driving method of the present invention.

FIG. 10 is a cross-sectional view illustrating a wall charge distribution of one display cell immediately after a gradual rising voltage is applied to the Y electrode lines in the initialization cycle of FIG. 9.

FIG. 11 is a cross-sectional view illustrating a wall charge distribution of one display cell at the end of the initialization cycle of FIG. 9.

<Explanation of symbols for main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ..., X _n ... X electrode line, Y ₁ , ..., Y _n ... Y electrode line,

A _R1 , ..., A _Bm ... address electrode line, X _na , Y _na ... transparent electrode line,

X _nb , Y _nb ... metal electrode line, SF ₁ , ... SF ₈ ... subfield,

S _Y1 , ..., S _Yn ... Y electrode drive signal, V _G ... ground voltage,

S _X1..Xn ... X electrode drive signal, SF ... unit subfield,

S _AR1 .. _ABm ... display data signal, 62 ... logical control,

63 ... address drive, 64 ... X drive,

65 ... Y drive unit, 66 ... image processing unit,

T _ID ... break time.

Claims (1)

The wall charges are formed by an initializing step of making the charge states of the display cells to be driven uniform, an address step of forming wall charges of a predetermined voltage only in the display cells to be subjected to display discharge, and applying an alternating pulse to all the display cells. A display-holding step of performing display discharge only in the display cells only is performed in the unit subfield, and the unit frame is divided into a plurality of subfields and time-divided by the number of pulses of the display-holding step assigned to each subfield. In the driving method, but the plasma display panel driving method in which a down time proportional to the number of display cells performing the display discharge in the unit frame is present in the unit frame, Extending the display-holding step allocated to the subfield immediately before the pause time to the idle time by lowering its frequency while the number of pulses of the display-holding step allocated to the subfield immediately before the pause time has not changed. Driving method performed by.