KR100573113B1 - Method for driving plasma display panel wherein effective resetting is performed - Google Patents

Abstract

In the method of driving a plasma display panel according to the present invention, the resetting of at least one subfield among the plurality of subfields includes first potential raising and potential lowering steps. In the first potential raising step, the potential applied to the second display electrode lines is continuously raised to the first potential. In the first potential falling step, the third potential lower than the second potential is applied to the second display electrode lines while the potential applied to the first display electrode lines is maintained at a second potential lower than the first potential. Will continue to descend. Meanwhile, resetting at least one subfield among the plurality of subfields includes second potential raising and potential falling steps. In the second potential raising step, the potential applied to the second display electrode lines is raised to the second potential. In the second potential falling step, a fourth potential lower than the second potential and higher than the third potential is higher than the third potential while the potential applied to the first display electrode lines is maintained at the second potential. Will continue to descend.

Description

Method for driving plasma display panel where effective resetting is performed}

1 is a perspective view showing an internal structure of a conventional three-electrode surface discharge plasma display panel.

FIG. 2 is a cross-sectional view illustrating an example of one display cell of the panel of FIG. 1.

3 is a block diagram illustrating a conventional driving device of the plasma display panel of FIG. 1.

FIG. 4 is a timing diagram illustrating a conventional address-display separation driving scheme for Y electrode lines of the plasma display panel of FIG. 1.

5 is a waveform diagram of signals applied to electrode lines of a plasma display panel by a conventional driving method.

6 is a waveform diagram of signals applied to electrode lines of a plasma display panel by a driving method of an embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t ₃ of FIG. 6.

FIG. 8 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t ₄ of FIG. 6.

FIG. 9 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t ₇ of FIG. 6.

FIG. 10 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t ₈ of FIG. 6.

FIG. 11 is a diagram illustrating an example in which two reset types of FIG. 6 are applied to each subfield of a unit frame.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ..., Xn ... X electrode line, Y ₁ , ..., Yn ... Y electrode line,

A _R1 , ..., A _Bm ... address electrode line, X _na , Y _na ... transparent electrode line,

X _nb , Y _nb ... metal electrode line, SF ₁ , ... SF ₈ ... subfield,

S _Y ... Y drive control signal, V _G ... ground voltage,

S _X ... X drive control signal,

S _A ... address drive control signal,

62 logic controller, 63 address drive,

64 ... X drive, 65 ... Y drive,

66 ... image processing unit, R ₁ , ..., R ₈ ... reset cycle.

The present invention relates to a method of driving a plasma display panel, and more particularly, to a plasma display panel having a three-electrode surface discharge structure, a unit frame is divided into a plurality of subfields for time division gray scale display. A method of driving a plasma display panel in which resetting, addressing, and discharge-maintaining are performed in each of the subfields.

1 shows a structure of a conventional three-electrode surface discharge plasma display panel. FIG. 2 shows an example of one display cell of the panel of FIG. 1. 1 and 2, between the front and rear glass substrates 10 and 13 of a conventional surface discharge plasma display panel 1, address electrode lines A _R1 ,..., A _Bm , a dielectric layer. (11, 15), Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), phosphor 16, partition 17 and protective layer As a magnesium monoxide (MgO) layer 12 is provided.

The address electrode lines A _R1 ,..., A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied to the entire surface in front of the address electrode lines A _R1 ,..., A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 ,..., And A _Bm . These partitions 17 function to partition the discharge area of each display cell and prevent optical cross talk between each display cell. The fluorescent layer 16 is applied between the partition walls 17.

The X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) intersect the address electrode lines (A _R1 , ..., A _Bm ). It is formed in a constant pattern on the back of the front glass substrate 10. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , ..., Xn) and each Y electrode line (Y ₁ , ..., Y _n ) is a transparent electrode line of a transparent conductive material such as indium tin oxide (ITO) or the like (see FIG. 2). X _na , Y _na ) and a metal electrode line (X _nb , Y _nb of FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ,..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

In the driving method basically applied to such a plasma display panel, the resetting, addressing, and display-sustain steps are sequentially performed in the unit subfield. In the resetting phase, the charge states of all display cells are uniform. In the addressing step, a predetermined wall voltage is generated in the selected display cells. In the discharge-hold step, a predetermined alternating voltage is applied to all the XY electrode line pairs so that display cells in which the wall voltage is formed in the addressing step cause discharge-maintain discharge. In this discharge-maintaining step, plasma is formed in the discharge space 14, i.e., the gas layer, of the selected display cells causing the discharge-maintaining discharge, and the fluorescent layer 16 is excited by the ultraviolet radiation to generate light.

FIG. 3 shows a typical driving device of the plasma display panel 1 of FIG. 1. Referring to FIG. 3, a typical driving device of the plasma display panel 1 includes an image processor 66, a logic controller 62, an address driver 63, an X driver 64, and a Y driver 65. . The image processing unit 66 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The controller 62 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 66. The address driver 63 processes the address signal S _A among the drive control signals S _A , S _Y , and S _X from the logic controller 62 to generate a display data signal, and generates the display data signal. Is applied to the address electrode lines. The X driving unit 64 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the control unit 62, and applies the X driving control signal S _X to the X electrode lines. The Y driver 65 processes the Y driving control signal S _Y among the driving control signals S _A , S _Y , and S _X from the logic controller 62, and applies the Y driving control signal S _Y to the Y electrode lines.

FIG. 4 illustrates a conventional address-display separation driving scheme for the Y electrode lines of the plasma display panel of FIG. 1. Referring to FIG. 4, each of all unit frames is divided into _eight subfields SF ₁ , SF 8 to realize time division gray scale display. In addition, each subfield SF ₁ , ..., SF ₈ has a reset time R ₁ , ..., R ₈ , an addressing time A ₁ , ..., A ₈ , and a discharge-hold It is divided by time S ₁ , ..., S ₈ .

The discharge conditions of all the display cells become uniform at each reset time R ₁ ,..., R ₈ , while being adapted to the addressing to be performed in the next step.

At each addressing time (A ₁ , ..., A ₈ ), a display data signal is applied to the address electrode lines (A _R1 , ..., A _{Bm in} FIG. 1) and at the same time, each Y electrode line (Y ₁ , ..., Y _n ), the scanning pulses are sequentially applied. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are formed by the addressing discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

At each discharge-hold time (S ₁ , ..., S ₈ ), all Y electrode lines (Y ₁ , ..., Y _n ) and all X electrode lines (X ₁ , ..., X _n) The discharge-maintenance pulses are alternately applied to generate the display discharge in the discharge cells in which the wall charges are formed at the corresponding addressing times A ₁ , ..., A ₈ . Therefore, the luminance of the plasma display panel is proportional to the length of the discharge-hold time S ₁ , ..., S ₈ occupied in the unit frame. The length of the discharge-hold time S ₁ , ..., S ₈ occupied in the unit frame is 255T (T is the unit time). Therefore, it can be displayed in 256 gray scales, even if it is not displayed once in a unit frame.

Here, the first sub-field (SF ₁₎ discharge-maintaining time (S _1), the time (1T) corresponding to ^20, the second discharge of the sub-field (SF ₂₎ - a holding time (S _2), the two the time (2T) equivalent to ^1, the third sub-field (SF ₃₎ discharge of-discharge of the sustain time period (4T) corresponding to the in ² 2 (S ₃₎ is the fourth sub-field (SF ₄₎ - In the holding time S ₄ , a time 8T corresponding to 2 ³ , and in the discharge-holding time S ₅ of the fifth subfield SF ₅ , a time 16T corresponding to 2 ⁴ , a sixth sub in time corresponding to ²⁶ the retention time (S ₇₎ - a holding time (S _6), this time (32T) corresponding to ^25, a seventh discharge of the subfield (SF ₇₎ - a field (SF ₆₎ discharge of 64T and a time 128T corresponding to 2 ⁷ are set in the discharge-hold time S ₈ of the eighth subfield SF ₈ , respectively.

Accordingly, if a subfield to be displayed among the eight subfields is appropriately selected, 256 gray levels may be displayed including all zero (zero) grays not displayed in any subfields.

FIG. 5 shows driving signals applied to electrode lines of the plasma display panel 1 of FIG. 1 in each unit subfield of FIG. 4 according to a conventional resetting method. The conventional resetting method included in the driving method of Fig. 5 is taught in Japanese Laid-Open Patent Publications 214,823 and 242,224. In FIG. 5, reference numeral S _{AR1 ..ABm} denotes a driving signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 .. Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to.

Referring to FIG. 5, in the first time t ₁ to t ₂ of the resetting time R of the unit subfield SF, the first application is applied to the X electrode lines X ₁ ,..., X _n . The potential to be increased is continuously raised from the ground potential V _G to the potential of the second potential V _S. Here, the ground potential V _G is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, between the X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), and the X electrode lines (X ₁ , ..., X) A weak discharge occurs between _n ) and the address electrode lines A ₁ , ..., A _m , and negative wall charges are formed around the X electrode lines X ₁ , ..., X _n . .

In the second time t ₂ to t ₃ as the wall charge accumulation time, the potential applied to the Y electrode lines Y ₁ ,..., Y _n is from the second potential V _S to the second potential V. _It is continuously raised to the potential of the first potential V _SET + V _{S which} is higher by the fifth potential V _SET than _S ). Here, the ground potential V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , A weaker discharge occurs between ..., Y _n ) and the address electrode lines A _R1 , ..., A _Bm . Here, Y electrode lines _{(Y 1, ..., Y n} ) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _The reason why the discharge between _n ) and the X electrode lines (X ₁ , ..., X _n ) becomes stronger is that the negative wall charges around the X electrode lines (X ₁ , ..., X _n ) Because they were formed. Accordingly, a large number of negative wall charges are formed around the Y electrode lines Y ₁ ,..., And Y _n , and a positive wall is formed around the X electrode lines X ₁ , ..., X _n . Charges are formed, and less positive wall charges are formed around the address electrode lines A _R1 ,..., A _Bm .

In the third time t ₃ to t ₄ as the wall charge distribution time, in a state where the potential applied to the X electrode lines X ₁ ,..., X _n is maintained at the second potential V _S , The potential applied to the Y electrode lines Y ₁ ,..., Y _n is continuously lowered from the second potential V _S to the ground potential V _G as the third potential. Here, the ground potential V _G is applied to the address electrode lines A _R1 ,..., A _Bm . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around .., Y _n ) move around the X electrode lines X ₁ ,..., X _n . Accordingly, the wall electric-potential of the X electrode lines X ₁ , ..., X _n is lower than the wall potential of the address electrode lines A _R1 , ..., A _Bm and the Y electrode Higher than the wall potential of the lines Y ₁ , ..., Y _n . As a result, the addressing voltage V _A -V _G required for the counter discharge between the selected address electrode lines and the Y electrode line may be lowered at the subsequent addressing time A. FIG. Meanwhile, since the ground potential V _G is applied to all the address electrode lines A _R1 ,..., And A _Bm , the address electrode lines A _R1 ,..., A _Bm are X electrode lines ( X ₁ , ..., X _n ) and the Y electrode lines Y ₁ , ..., Y _n are discharged, and the discharge causes the address electrode lines A _R1 , ..., A _Bm ), the positive wall charges around it disappear.

In the subsequent addressing time A, the display data signal is applied to the address electrode lines, and the Y electrode lines Y ₁ ,... _{Biased to} the sixth potential V _SCAN lower than the second potential V _S. , Y _n ), as the scan signals of the ground potential V _G are sequentially applied, smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , ..., A _Bm is applied with the positive addressing potential V _A when the display cell is selected and the ground potential V _G when the display cell is not selected. do. Accordingly, when the display data signal of the positive addressing potential V _A is applied while the scan pulse of the ground potential V _G is applied, wall charges are formed by the addressing discharge in the corresponding display cell. Wall charges do not form. Here, for a more accurate and efficient addressing discharge, the second potential V _S is maintained at the X electrode lines X ₁ , ... X _n .

Discharging the second electrical potential (V _S) for a holding time in the (S), all the Y electrode lines (Y _1, ... Y _n) and the X electrode lines _{(X 1, ... X n)} - leading to the discharge -The sustain pulses are applied alternately, producing a discharge for discharge-maintaining in the display cells in which wall charges are formed at the corresponding addressing time (A).

According to the conventional driving method as described above, a very high potential V _SET + V _S is applied to the Y electrode lines Y ₁ , ..., Y _n at the reset time R of each subfield. Since it is applied, there is a problem that the contrast performance of the plasma display device is lowered, the power consumption is increased, and the life is shortened.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of improving the contrast performance, reducing power consumption, and extending the life of a plasma display apparatus by performing efficient reset in the method of driving a plasma display panel. .

A method of the present invention for achieving the above object has a front substrate and a back substrate spaced apart from each other, the first and second display electrode lines are formed parallel to each other between the substrates, the address electrode lines are the first substrate And a unit frame is divided into a plurality of subfields for time division gradation display for a plasma display panel formed to intersect with the second electrode lines, and reset, addressing, and discharge-maintaining are performed in each of the subfields. A driving method of a plasma display panel is performed. The resetting of at least one subfield of the plurality of subfields includes first potential rising and potential falling steps. In the first potential raising step, the potential applied to the second display electrode lines is continuously raised to the first potential. In the first potential dropping step, the potential applied to the second display electrode lines is changed to the second potential while the potential applied to the first display electrode lines is maintained at a second potential lower than the first potential. It is continuously lowered to a lower third potential. Meanwhile, the resetting of at least one subfield among the plurality of subfields includes second potential raising and potential lowering steps. In the second potential raising step, the potential applied to the second display electrode lines is raised to the second potential. In the second potential lowering step, the potential applied to the second display electrode lines is lower than the second potential and the third potential is applied while the potential applied to the first display electrode lines is maintained at the second potential. It is continuously lowered to the fourth potential higher than the potential.

According to the driving method of the plasma display panel of the present invention, the reset is performed in the first potential raising and lowering potentials for all display cells, and only for the cells for which discharge-maintaining has been performed in the previous subfield. The reset is performed in the second potential raising and potential lowering steps. As such a proper and efficient reset is performed, the contrast performance of the plasma display device can be enhanced, the power consumption can be reduced, and the life can be extended. On the other hand, since the fourth potential in the second potential dropping step is higher than the third potential in the first potential dropping step, a more uniform wall charge despite the difference between the first and second potential rising steps. Allocation can be made.

Hereinafter, preferred embodiments according to the present invention will be described in detail.

FIG. 6 illustrates electrode lines of the plasma display panel 1 of FIG. 1 in one subfield SF _A and another subfield SF _B of FIG. 4 by a driving method of an embodiment of the present invention. Show driving signals applied to. The driving waveforms at the addressing time A and the discharge-hold time S of one subfield SF _A are the same as those in the another subfield SF _B. In FIG. 6, reference numeral S _{AR1 ..ABm} denotes a driving signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 ..Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to. FIG. 7 illustrates a wall charge distribution of one display cell at time t ₃ of FIG. 6. 8 illustrates a wall charge distribution of one display cell at time t ₄ of FIG. 6. FIG. 9 illustrates a wall charge distribution of one display cell at time t ₇ of FIG. 6. FIG. 10 illustrates a wall charge distribution of one display cell at time t ₈ of FIG. 6. 7 through 10, the same reference numerals as used in Fig. 2 indicate the objects of the same function.

6 to 8, driving signals applied to the electrode lines of the plasma display panel 1 of FIG. 1 in one subfield SF _A of FIG. 4 are described as follows.

In the first time t ₁ to t ₂ of the resetting time R _A of one unit subfield SF _A , the potential applied to the X electrode lines X ₁ ,..., X _{n first} . Is continuously raised from the ground potential V _G to the second potential V _S. Here, the ground potential V _G is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, between the X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), and the X electrode lines (X ₁ , ..., X) A weak discharge occurs between _n ) and the address electrode lines A ₁ , ..., A _m , and negative wall charges are formed around the X electrode lines X ₁ , ..., X _n . .

In the second time t ₂ to t ₃ as the wall charge accumulation time, the potential applied to the Y electrode lines Y ₁ ,..., Y _n is from the second potential V _S to the second potential V. _It is continuously raised to the first potential V _SET + V _{S which} is higher by the fifth potential V _SET than _S ). Here, the ground potential V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , A weaker discharge occurs between ..., Y _n ) and the address electrode lines A _R1 , ..., A _Bm . Here, Y electrode lines _{(Y 1, ..., Y n} ) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _The reason why the discharge between _n ) and the X electrode lines (X ₁ , ..., X _n ) becomes stronger is that the negative wall charges around the X electrode lines (X ₁ , ..., X _n ) Because they were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 7).

In the third time t ₃ to t ₄ as the wall charge distribution time, in a state where the potential applied to the X electrode lines X ₁ ,..., X _n is maintained at the second potential V _S , The potential applied to the Y electrode lines Y ₁ ,..., Y _n is continuously lowered from the second potential V _S to the third potential V _NF1 lower than the ground potential V _G. Here, the ground potential V _G is applied to the address electrode lines A _R1 ,..., A _Bm . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around..., Y _n ) move around the X electrode lines X ₁ ,..., X _n (see FIG. 8). Accordingly, the wall electric-potential of the X electrode lines X ₁ , ..., X _n is lower than the wall potential of the address electrode lines A _R1 , ..., A _Bm and the Y electrode Higher than the wall potential of the lines Y ₁ , ..., Y _n . As a result, the addressing voltage V _A -V _G required for the counter discharge between the selected address electrode lines and the Y electrode line may be lowered at the subsequent addressing time A. FIG. Meanwhile, since the ground potential V _G is applied to all the address electrode lines A _R1 ,..., And A _Bm , the address electrode lines A _R1 ,..., A _Bm are X electrode lines. Discharge is performed on (X ₁ , ..., X _n ) and Y electrode lines (Y ₁ , ..., Y _n ), and due to this discharge, the address electrode lines (A _R1 , ..., A _Bm ), the positive wall charges around it disappear (see FIG. 8).

In the subsequent addressing time A, the display data signal is applied to the address electrode lines, and the Y electrode lines Y ₁ ,... _{Biased to} the sixth potential V _{SC_H} lower than the second potential V _S. , Y _n ), as the scan signals of the seventh potential V _{SC_L} lower than the ground potential V _G are sequentially applied, smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , ..., A _Bm is applied with the positive addressing potential V _A when the display cell is selected and the ground potential V _G when the display cell is not selected. do. Accordingly, when the display data signal of the positive addressing potential V _A is applied while the scan pulse of the ground potential V _G is applied, wall charges are formed by the addressing discharge in the corresponding display cell. Wall charges do not form. Here, for a more accurate and efficient addressing discharge, the second potential V _S is maintained at the X electrode lines X ₁ , ... X _n .

In the subsequent discharge-hold time S, the second potential V _S is applied to all the Y electrode lines Y ₁ , ... Y _n and the X electrode lines X ₁ , ... X _n . Discharge-hold pulses are alternately applied, causing a discharge for discharge-hold in display cells in which wall charges are formed at a corresponding addressing time (A).

6, 9, and 10, driving signals applied to the electrode lines of the plasma display panel 1 of FIG. 1 in another subfield SF _B of FIG. 4 will be described as follows.

In the first time t ₅ to t ₆ of the resetting time R _B of the another subfield SF _B , a potential applied to the X electrode lines X ₁ ,..., X _n is _first applied. Is continuously raised from the ground potential V _G to the second potential V _S. Here, the ground potential V _G is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, in the display cells in which the sustain discharge is performed in the discharge-sustainment period S of the previous subfield, the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ,. X electrode line with weak discharge between .., Y _n ) and between X electrode lines (X ₁ , ..., X _n ) and address electrode lines (A ₁ , ..., A _m ) Negative wall charges are formed around the fields X ₁ , ..., X _n .

In the second time t ₆ to t ₇ as the wall charge accumulation time, the potential applied to the Y electrode lines Y ₁ ,..., Y _n rises to the second potential V _S. Here, the ground potential V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ..., A _Bm . Accordingly, a large number of negative wall charges are formed around the Y electrode lines Y ₁ ,..., And Y _n of the display cells that have performed the sustain discharge in the discharge-sustainment period S of the previous subfield. Positive wall charges are formed around the electrode lines X ₁ , ..., X _n , and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm ( 9).

In the third time t ₇ to t ₈ as the wall charge distribution time, in a state where the potential applied to the X electrode lines X ₁ ,..., X _n is maintained at the second potential V _S , A fourth potential (V) applied to the Y electrode lines (Y ₁ , ..., Y _n ) is lower than the ground potential (V _G ) from the second potential (V _S ) and higher than the third potential (V _NF1 ). V _NF2 ) is continuously lowered. Here, the ground potential V _G is applied to the address electrode lines A _R1 ,..., A _Bm . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around..., Y _n ) move around the X electrode lines X ₁ ,..., X _n (see FIG. 10). Accordingly, the wall electric-potential of the X electrode lines X ₁ , ..., X _n is lower than the wall potential of the address electrode lines A _R1 , ..., A _Bm and the Y electrode Higher than the wall potential of the lines Y ₁ , ..., Y _n . As a result, the addressing voltage V _A -V _G required for the counter discharge between the selected address electrode lines and the Y electrode line may be lowered at the subsequent addressing time A. FIG. Meanwhile, since the ground potential V _G is applied to all the address electrode lines A _R1 ,..., And A _Bm , the address electrode lines A _R1 ,..., A _Bm are X electrode lines ( Discharge is performed on X ₁ , ..., X _n ) and Y electrode lines (Y ₁ , ..., Y _n ), and due to the discharge, the address electrode lines (A _R1 , ..., A) _Bm ) the positive wall charges around it disappear (see FIG. 8).

As described above, in the reset cycle R _A of the first type, the potentials of the Y electrode lines Y ₁ ,..., And Y _n fall to the third potential V _NF1 , and the second In the type reset period R _B , the potentials of the Y electrode lines Y ₁ ,..., Y _n fall to the fourth potential V _NF2 higher than the third potential V _NF1 . Here, since the negative wall charges are formed around all of the Y electrode lines Y ₁ ,..., Y _{n in} the first type of reset period R _A , the Y electrode lines ( As the potential of Y ₁ , ..., Y _n is lowered to the relatively low third potential V _NF1 , negative polarity is around all of the Y electrode lines Y ₁ , ..., Y _n . Wall charges are relatively moved. On the contrary, since the negative wall charges are formed relatively around the Y electrode lines Y ₁ ,..., Y _{n in} the second type of reset period R _B , the Y electrode lines ( As the potential of Y ₁ , ..., Y _n is lowered to the relatively high fourth potential V _NF2 , negative polarity is around all of the Y electrode lines Y ₁ , ..., Y _n . Wall charges are relatively moved. Thus, a more uniform distribution of wall charges can be achieved in spite of the difference in the potential raising steps of the first and second types.

FIG. 11 shows an example in which two reset types R _A and R _B of FIG. 6 are applied to each subfield of a unit frame. Referring to FIG. 11, the second resetting type in the resetting periods R1, R6 to R8 of the subfields SF1, SF6 to SF8 of which the discharge-sustaining period S of the previous subfield is relatively long. (R _B ) is used, and the first resetting type R _B in the resetting periods R2 to R5 of the subfields SF2 to SF5 in which the discharge-maintenance period S of the previous subfield is relatively short. ) Is used. As such a proper and efficient reset is performed, the contrast performance of the plasma display device can be enhanced, the power consumption can be reduced, and the life can be extended.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

As described above, according to the driving method of the plasma display panel according to the present invention, resetting is performed in the first potential raising and lowering potentials for all display cells, and discharge-maintaining is performed in the previous subfield. Resetting is performed in the second potential rise and potential fall steps for only those cells that have been. As such a proper and efficient reset is performed, the contrast performance of the plasma display device can be enhanced, the power consumption can be reduced, and the life can be extended. On the other hand, since the fourth potential in the second potential dropping step is higher than the third potential in the first potential dropping step, a more uniform wall charge despite the difference between the first and second potential rising steps. Allocation can be made.

Claims (5)

A front substrate and a rear substrate spaced apart from each other, wherein the first and second display electrode lines are formed parallel to each other, and the address electrode lines are formed to intersect with the first and second electrode lines. A method of driving a plasma display panel in which a unit frame is divided into a plurality of subfields for time division gray scale display, and reset, addressing, and discharge-maintaining are performed in each of the subfields. The resetting of at least one subfield of the plurality of subfields, Continuously raising the potential applied to the first display electrode lines to a second potential; Continuously raising the potential applied to the second display electrode lines to a first potential higher than the second potential; And Continuously lowering the potential applied to the second display electrode lines to a third potential lower than the second potential while maintaining the potential applied to the first display electrode lines at the second potential; , The resetting of at least one subfield of the plurality of subfields, Continuously raising the potential applied to the first display electrode lines to the second potential; Raising the potential applied to the second display electrode lines to the second potential; And The potential applied to the second display electrode lines is maintained until the fourth potential lower than the second potential and higher than the third potential while the potential applied to the first display electrode lines is maintained at the second potential. A method of driving a plasma display panel comprising descending. delete delete The method of claim 1, And a polarity of the fourth potential is negative. The method of claim 4, wherein And a polarity of the third potential is negative.

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