KR20060027510A - Discharge display apparatus wherein effective resetting is performed - Google Patents

Abstract

In the discharge display apparatus according to the present invention, a plurality of subfields are included in a unit frame, and at least one of the plurality of subfields initially includes a reset period. Here, the reset period includes a time when the potential applied to the electrode lines of the discharge display panel is discontinuously changed, and a time when the potential applied to the electrode lines is continuously changed.

Description

Discharge display apparatus wherein effective resetting is performed}

1 is an internal perspective view showing the structure of a three-electrode surface discharge plasma display panel as a discharge display panel according to the present invention.

FIG. 2 is a cross-sectional view illustrating an example of one discharge cell of the plasma display panel of FIG. 1.

Figure 3 is a block diagram showing an overall discharge display device according to the present invention.

4 is a timing diagram illustrating how a discharge display panel is driven in the apparatus of FIG. 3.

5 is a waveform diagram illustrating a first example of signals applied to electrode lines of a plasma display panel by a driving method according to the present invention.

6 is a cross-sectional view illustrating a wall charge distribution of one discharge cell at time t ₄ of FIG. 5.

FIG. 7 is a cross-sectional view illustrating a wall charge distribution of one discharge cell at time t ₅ of FIG. 5.

8 is a waveform diagram illustrating a second example of signals applied to electrode lines of the plasma display panel by the driving method according to the present invention.

9 is a waveform diagram illustrating a third example of signals applied to electrode lines of the plasma display panel by the driving method according to the present invention.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ..., Xn ... X electrode line, Y ₁ , ..., Yn ... Y electrode line,

A _R1 , ..., A _Bm ... address electrode line, X _na , Y _na ... transparent electrode line,

X _nb , Y _nb ... metal electrode line, SF ₁ , ... SF ₈ ... subfield,

S _Y ... Y drive control signal, V _G ... ground potential,

S _X ... X drive control signal,

S _A ... address drive control signal,

62 logic controller, 63 address drive,

64 ... X drive, 65 ... Y drive,

66 ... image processing unit, R ₁ , ..., R ₈ ... reset cycle.

The present invention relates to a discharge display device, and more particularly, to a discharge display device in which a plurality of subfields are included in a unit frame, and a reset period is initially included in each of the plurality of subfields.

In a typical discharge display device, for example, a plasma display device, time division driving in which a unit frame includes a plurality of subfields is performed (see US Pat. No. 5,541,618). In each subfield, reset, addressing, and display-sustain cycles are performed sequentially. In the reset period, the charge states of all the discharge cells become uniform. In the addressing period, the set wall voltage is generated in the selected discharge cells. In the sustain-discharge cycle, discharge cells in which a set wall voltage is formed in the addressing cycle cause sustain-discharge.

In the driving cycles of the discharge display device as described above, the charge states of each discharge cell are not uniform at the start of the reset period, and the operation characteristics of each discharge cell are not uniform. Accordingly, there is a problem in that the charge states of each discharge cell are not uniform at the end of the reset period due to the presence of discharge cells causing low discharge in the reset period. In this case, low discharge may occur in the addressing and sustaining-discharging cycles, thereby degrading display performance.

 It is an object of the present invention to provide a discharge display apparatus in which display performance can be improved as the reset function is efficiently improved.

In the discharge display apparatus of the present invention for achieving the above object, a plurality of subfields are included in a unit frame, and a reset period is initially included in at least one of the plurality of subfields. Here, the reset period includes a time when the potential applied to the electrode lines of the discharge display panel is discontinuously changed, and a time when the potential applied to the electrode lines is continuously changed.

According to the discharge display device of the present invention, a discharge of normal intensity may occur in discharge cells in a low discharge condition because the potential applied to the electrode lines changes discontinuously, and the potential applied to the electrode lines The continuous change of may cause a discharge of normal intensity in all discharge cells under normal discharge conditions. Accordingly, the charge states of each discharge cell may be uniformly set at the end of the reset period. Accordingly, the addressing and sustaining-discharging operations following the reset period may be performed uniformly, thereby improving display performance.

Hereinafter, preferred embodiments according to the present invention will be described in detail.

1 shows a structure of a three-electrode surface discharge plasma display panel as a discharge display panel according to the present invention. FIG. 2 shows an example of one discharge cell of the panel of FIG. 1. 1 and 2, between the front and rear glass substrates 10 and 13 of the plasma display panel 1 according to the present invention, address electrode lines A _R1 ,..., A _Bm , a dielectric layer (11, 15), Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), phosphor 16, partition 17 and protective layer As a magnesium monoxide (MgO) layer 12 is provided.

The address electrode lines A _R1 ,..., A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied to the entire surface in front of the address electrode lines A _R1 ,..., A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 ,..., And A _Bm . These partitions 17 function to partition the discharge area of each discharge cell and prevent optical cross talk between each discharge cell. The fluorescent layer 16 is applied between the partition walls 17.

The X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) intersect the address electrode lines (A _R1 , ..., A _Bm ). It is formed in a constant pattern on the back of the front glass substrate 10. Each intersection sets a corresponding discharge cell. Each X electrode line (X ₁ , ..., Xn) and each Y electrode line (Y ₁ , ..., Y _n ) is a transparent electrode line of a transparent conductive material such as indium tin oxide (ITO) or the like (see FIG. 2). X _na , Y _na ) and a metal electrode line (X _nb , Y _nb of FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ ,..., Y _n ). A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

In the driving method basically applied to such a discharge display panel, the resetting, addressing, and display-sustain steps are sequentially performed in the unit subfield. In the resetting step, the charge states of all the discharge cells become uniform. In the addressing step, a predetermined wall voltage is generated in the selected discharge cells. In the display-holding step, a predetermined alternating voltage is applied to all XY electrode line pairs so that the discharge cells in which the wall voltage is formed in the addressing step cause display-holding discharges. In this display-holding step, plasma is formed in the discharge space 14, i.e., the gas layer, of the selected discharge cells causing the display-holding discharge, and the fluorescent layer 16 is excited by the ultraviolet radiation to generate light.

3 shows the discharge display apparatus according to the present invention as a whole. 1 and 3, the discharge display apparatus according to the present invention includes a plasma display panel 1, an image processor 66, a logic controller 62, an address driver 63, an X driver 64, and a Y driver ( 65). The image processing unit 66 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The controller 62 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 66. The address driver 63 processes the address signal S _A among the drive control signals S _A , S _Y , and S _X from the logic controller 62 to generate a display data signal, and generates the display data signal. Is applied to the address electrode lines A _R1 ,..., A _Bm of the plasma display panel 1. The X driving unit 64 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the control unit 62, so that the X electrode lines of the plasma display panel 1 ( X ₁ , ..., X _n ). The Y driver 65 processes the Y drive control signal S _Y among the drive control signals S _A , S _Y , and S _X from the logic controller 62 to Y electrode lines of the plasma display panel 1. Applies to (Y ₁ , ..., Y _n ).

4 shows how the discharge display panel 1 is driven in the device of FIG. 3. Referring to FIG. 4, each of all unit frames is divided into _eight subfields SF ₁ , SF 8 to realize time division gray scale display. In addition, each subfield SF ₁ , ..., SF ₈ has a reset period R ₁ , ..., R ₈ , an addressing period A ₁ , ..., A ₈ , and a display-hold period. (S ₁ , ..., S ₈ ).

The discharge conditions of all the discharge cells become uniform in each reset period (R ₁ , ..., R ₈ ) while being adapted for addressing to be performed in the next step.

In each addressing period A ₁ ,..., And A ₈ , a display data signal is applied to the address electrode lines A _R1 , ..., A _{Bm in} FIG. 1 and at the same time, each Y electrode line Y ₁ ,. ..., Y _n ), the scanning pulses are sequentially applied. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are formed by addressing discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

In each display-hold period S ₁ , ..., S ₈ , all Y electrode lines Y ₁ , ..., Y _n and all X electrode lines X ₁ , ..., X _n Display-maintenance pulses are alternately applied to generate display discharges in discharge cells in which wall charges are formed in corresponding addressing periods A ₁ , ..., A ₈ . Therefore, the luminance of the plasma display panel is proportional to the length of the display-hold periods S ₁ ,..., S ₈ occupied in the unit frame. The length of the display-hold periods S ₁ , ..., S ₈ occupied in the unit frame is 255T (T is unit time). Therefore, it can be displayed in 256 gray scales, even if it is not displayed once in a unit frame.

Here, in the display-hold period S ₁ of the first subfield SF ₁ , a time 1T corresponding to 2 ⁰ is present, and in the display-hold period S _{2 of} the second subfield SF ₂ . the liver (2T) during which corresponds to ^21, the third sub-field (SF ₃₎ display of-the sustain period two hours (4T) corresponding to the in ² 2 (S _3), the fourth sub-field (SF ₄₎ The display-hold period S ₄ has a time 8T corresponding to 2 ³ , and the display-hold period S ₅ of the fifth subfield SF ₅ has a time 16T corresponding to 2 ⁴ . The time 32T corresponding to 2 ⁵ in the display-hold period S ₆ of the sixth subfield SF ₆ corresponds to 2 ⁶ in the display-hold period S ₇ of the seventh subfield SF ₇ . The time 64T, and the time 128T corresponding to 2 ⁷ are set in the display-hold period S ₈ of the eighth subfield SF ₈ , respectively.

Accordingly, if a subfield to be displayed among the eight subfields is appropriately selected, 256 gray levels may be displayed including all zero (zero) grays not displayed in any subfields.

FIG. 5 shows a first example of driving signals applied to electrode lines of the plasma display panel 1 of FIG. 1 in the unit subfield SF of FIG. 4 by the driving method according to the present invention. In FIG. 5, reference numeral S _{AR1 ..ABm} denotes a drive signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 .. Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to. FIG. 6 shows the wall charge distribution of one discharge cell at time t ₄ of FIG. 5. FIG. 7 shows the wall charge distribution of one discharge cell at time t ₅ of FIG. 5.

5 to 7, the driving signals applied to the electrode lines of the plasma display panel 1 of FIG. 1 in the unit subfield SF of FIG. 4 will be described as follows.

The reset period R of the unit subfield SF includes a main reset time t ₁ to t ₅ and a homogenization time t ₅ to t ₈ . The main reset time t ₁ to t ₅ includes the wall charge accumulation time t ₁ to t ₄ and the wall charge distribution time t ₄ to t ₅ . The uniform time t ₅ to t ₈ includes a first uniform time t ₅ to t ₆ and a second uniform time t ₆ to t ₈ .

In the wall charge accumulation time t ₁ to t _{4 of the} main reset time t ₁ to t ₅ , the potential applied to the Y electrode lines Y ₁ ,..., Y _n is the first potential V _S. ) To the second potential V _SET + V _S. Here, the ground potential V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ,..., A _Bm . At the wall charge accumulation time t ₁ to t _{4 as} described above, the discharge is performed between the Y electrode lines Y ₁ ,..., Y _n and the X electrode lines X ₁ ,..., X _n . On the other hand, a discharge occurs between the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ..., A _Bm . Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ ,..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 6).

In addition, the wall charge accumulation time (t ₁ ~ t ₄ ) is continuously and the time (t ₂ ~ t ₃ ) that the potential applied to the Y electrode lines (Y ₁ , ..., Y _n ) changes discontinuously. Time varying from t ₃ to t ₄ . Continuous time (t ₂ ~ t ₃₎ that varies as light is a first potential (V _S) the third voltage (V _EP) at which to rapidly raised to (t ₂₎ and held in the third potential (V _EP) time (t in ₂ to t ₃ ). Accordingly, a discharge of normal intensity may occur in the discharge cells under low discharge conditions due to the discontinuous rise of the potential applied to the Y electrode lines Y ₁ ,..., And Y _n , and the Y electrode lines As the potential applied to (Y ₁ , ..., Y _n ) continuously rises, a discharge of normal intensity may occur in all discharge cells under normal discharge conditions. Accordingly, it can be a charge state of the discharge cells at the end (t ₈₎ are uniformly set in the reset period (t ₁ ~ t _8). Accordingly, the operation in the addressing and sustain-discharge periods A and S subsequent to the reset period t ₁ to t ₈ may be performed uniformly, thereby improving display performance.

In the wall charge distribution time t ₄ to t _{5 of the} main reset time t ₁ to t ₅ , the potential applied to the X electrode lines X ₁ ,..., X _n is the sixth potential V _BF. ) And Y electrode lines (Y ₁ , ..., Y) while the potential applied to the address electrode lines (A _R1 , ..., A _Bm ) is maintained at the ground potential (V _G ). _The potential applied to _n ) is continuously lowered from the first potential V _S to the fifth potential V _NF lower than the ground potential V _G. Accordingly, due to the discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,... Some of the negative wall charges around Y _n ) move around the X electrode lines X ₁ ,..., X _n (see FIG. 7). Accordingly, the wall electric-potential of the X electrode lines X ₁ , ..., X _n is lower than the wall potential of the address electrode lines A _R1 , ..., A _Bm and the Y electrode Higher than the wall potential of the lines Y ₁ , ..., Y _n . Accordingly, the addressing voltage V _A -V _{SC_L} required for the counter discharge between the selected address electrode lines and the Y electrode line in the subsequent addressing period A may be lowered.

In the first uniformization time t ₅ to t ₆ , the ground potential V is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ..., A _Bm . _In the state where _G ) is applied, the potential applied to the Y electrode lines Y ₁ ,..., Y _n rises continuously from the ground potential V _G to the third potential V _EP . Accordingly, an appropriate amount of wall charges can be erased in the discharge cells which caused the overdischarge at the main reset time t ₁ to t ₅ .

At the beginning of the second uniformization time t ₆ to t ₈ , the ground potential is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . In the state where (V _G ) is applied, the potential applied to the X electrode lines (X ₁ , ..., X _n ) rises from the ground potential (V _G ) to the third potential (V _EP ) and then the ground potential (V). Restore to _G ). Accordingly, an appropriate amount of wall charges can be erased again in the discharge cells that caused the overdischarge at the main reset time t ₁ to t ₅ .

On the other hand, in the addressing period A, the display data signal is applied to the address electrode lines A _R1 ,..., A _Bm , and biased to the seventh potential V _{SC_H} higher than the ground potential V _G. As the scan signal of the scan potential V _{SC_L} lower than the ground potential V _G is sequentially applied to the Y electrode lines Y ₁ ,..., Y _n , smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , ..., A _Bm has a positive addressing potential V _A when the discharge cells are selected, and a ground potential V _G when the discharge cells are selected. do. Accordingly, when the display data signal of the positive addressing potential V _A is applied while the scan pulse of the negative scanning potential V _{SC_L} is applied, wall charges are formed by the addressing discharge in the corresponding discharge cell. Wall charges are not formed in the cell. Here, for a more accurate and efficient addressing discharge, the fifth potential V _BA is maintained at the X electrode lines X ₁ ,... X _n .

In the following display-hold period S, the display of the first potential V _{SH at} all the Y electrode lines Y ₁ , ... Y _n and the X electrode lines X ₁ , ... X _n . -Holding pulses are alternately applied, causing a discharge for display-holding in the discharge cells in which wall charges are formed in the corresponding addressing period A. FIG.

FIG. 8 shows a second example of signals applied to electrode lines of the plasma display panel 1 of FIG. 1 by the driving method according to the present invention. In FIG. 8, the same reference numerals as used in FIG. 7 indicate objects of the same function. Only the differences between the second example of FIG. 8 and the first example of FIG. 7 will be described below.

The wall charge accumulation time (t ₁ to t ₄ ) is a time (continuously changing time t ₂ to t ₃ ) and a continuously changing potential applied to the Y electrode lines (Y ₁ ,..., Y _n ). (T ₁ to t ₂ , t ₃ to t ₄ ). Time varies discontinuously (t ₂ ~ t ₃₎ has a third potential (V _EP) a fifth potential (V _BA) at which to rapidly raised to (t ₂₎ and the maintenance of a fifth potential (V _BA) time (t in ₂ to t ₃ ). Accordingly, a discharge of normal intensity may occur in the discharge cells under low discharge conditions due to the discontinuous rise of the potential applied to the Y electrode lines Y ₁ ,..., And Y _n , and the Y electrode lines As the potential applied to (Y ₁ , ..., Y _n ) continuously rises, a discharge of normal intensity may occur in all discharge cells under normal discharge conditions. Accordingly, it can be a charge state of the discharge cells at the end (t ₈₎ are uniformly set in the reset period (t ₁ ~ t _8). Accordingly, the operation in the addressing and sustain-discharge periods A and S subsequent to the reset period t ₁ to t ₈ may be performed uniformly, thereby improving display performance.

9 shows a third example of signals applied to the electrode lines of the plasma display panel 1 of FIG. 1 by the driving method according to the present invention. In FIG. 9, the same reference numerals as used in FIG. 7 indicate objects of the same function. The difference of the third example of FIG. 9 to the first example of FIG. 7 will now be described.

In the wall charge accumulation time t ₁ to t ₂ , the potential applied to the Y electrode lines Y ₁ ,..., And Y _n is changed from the first potential V _S to the second potential V _SET + V. _{Up to S} ). Here, the ground potential V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ,..., A _Bm . At the wall charge accumulation time t ₁ to t _{4 as} described above, the discharge is performed between the Y electrode lines Y ₁ ,..., Y _n and the X electrode lines X ₁ ,..., X _n . On the other hand, a discharge occurs between the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ..., A _Bm . Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 6).

In the wall charge distribution time t ₂ to t ₅ , the potential applied to the X electrode lines X ₁ ,..., X _n is maintained at the sixth potential V _BF , and the address electrode lines ( A potential applied to the Y electrode lines Y ₁ , ..., Y _n is a first potential while the potential applied to A _R1 , ..., A _Bm is maintained at the ground potential V _G. From V _S to the fifth potential V _NF lower than the ground potential V _G is lowered. Accordingly, due to the discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,... Some of the negative wall charges around Y _n ) move around the X electrode lines X ₁ ,..., X _n (see FIG. 7). Accordingly, the wall electric-potential of the X electrode lines X ₁ , ..., X _n is lower than the wall potential of the address electrode lines A _R1 , ..., A _Bm and the Y electrode Higher than the wall potential of the lines Y ₁ , ..., Y _n . Accordingly, the addressing voltage V _A -V _{SC_L} required for the counter discharge between the selected address electrode lines and the Y electrode line in the subsequent addressing period A may be lowered.

Here, the wall charge distribution time (t ₂ ~ t ₅ ) is a time (t ₃ ~ t ₄ ) and the time when the potential applied to the Y electrode lines (Y ₁ , ..., Y _n ) is changed discontinuously And times varying from t ₂ to t ₃ , t ₄ to t ₅ . Time varies discontinuously (t ₃ ~ t ₄₎ is the time to rapidly fall to the ground potential (V _G) high eighth potential than the ground potential at the (V _F1) (V _G) lower ninth potential (V _F2) than ( t ₃ ) and the retention time t ₃ to t ₄ of the ninth potential V _F2 . Accordingly, a discharge of normal intensity may occur in the discharge cells under low discharge conditions due to the discontinuous drop of the potential applied to the Y electrode lines Y ₁ ,..., And Y _n , and the Y electrode lines Due to the continuous drop in the potential applied to (Y ₁ , ..., Y _n ), a discharge of normal intensity may occur in all discharge cells under normal discharge conditions. Accordingly, it can be a charge state of the discharge cells at the end (t ₈₎ are uniformly set in the reset period (t ₁ ~ t _8). Accordingly, the operation in the addressing and sustain-discharge periods A and S subsequent to the reset period t ₁ to t ₈ may be performed uniformly, thereby improving display performance.

As described above, according to the discharge display device according to the present invention, the discharge of the normal intensity in the discharge cells in the low discharge condition due to the discontinuous change of the potential applied to the electrode lines of the discharge display panel in the reset period. The discharge of normal intensity may occur in all the discharge cells under normal discharge conditions due to the continuous change of the potential applied to the electrode lines. Accordingly, the charge states of each discharge cell can be set uniformly at the end of the reset period. Accordingly, the addressing and sustaining-discharging operations following the reset period are performed uniformly, thereby improving display performance.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

Claims (7)

A discharge display apparatus in which a plurality of subfields are included in a unit frame and a reset period is initially included in at least one of the plurality of subfields. The reset cycle, The time at which the potential applied to the electrode lines of the discharge display panel changes discontinuously, and And a time period during which the potential applied to the electrode lines continuously changes. The method of claim 1, wherein the reset period, The time at which the potential applied to the electrode lines rises discontinuously, and And a time period when the potential applied to the electrode lines continuously rises. The method of claim 2, And the continuously rising time, the discontinuously rising time, and the continuously rising time sequentially. The method of claim 1, wherein the reset period, The time at which the potential applied to the electrode lines falls discontinuously, and And a time for the potential applied to the electrode lines to fall continuously. The method of claim 4, wherein And the continuously descending time, the discontinuously falling time, and the continuously falling time sequentially. The method of claim 1, wherein in the discharge display panel, A front substrate and a rear substrate spaced apart from each other, First and second display electrode lines are formed parallel to each other between the substrates, And a discharge display device in which address electrode lines are crossed with respect to the first and second display electrode lines. The method of claim 6, wherein the reset period, A time at which the potential applied to the second display electrode lines changes discontinuously, and And a time for changing the potential applied to the second display electrode lines continuously.

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