KR100544124B1 - Method for resetting plasma display panel wherein bias voltage is applied to address electrode ines, and method for driving plasma display panel using the resetting method - Google Patents

Abstract

The resetting method of the plasma display panel according to the present invention includes a wall charge accumulation step and a wall charge distribution step. In the wall charge accumulation step, the voltage applied to the second display electrode lines is continuously raised to the first voltage. In the wall charge distribution step, when the voltage applied to the first display electrode lines is maintained at the second voltage lower than the first voltage, the voltage applied to the second display electrode lines is lower than the second voltage. While continuously lowered to the voltage, a fourth voltage lower than the third voltage is applied to the address electrode lines.

Description

Resetting method of a plasma display panel in which bias voltage is applied to address electrode lines, and a driving method of a plasma display panel using this resetting method {Method for resetting plasma display panel wherein bias voltage is applied to address electrode ines, and method for driving plasma display panel using the resetting method}

1 is a perspective view showing an internal structure of a conventional three-electrode surface discharge plasma display panel.

FIG. 2 is a cross-sectional view illustrating an example of one display cell of the panel of FIG. 1.

3 is a block diagram illustrating a conventional driving device of the plasma display panel of FIG. 1.

FIG. 4 is a timing diagram illustrating a conventional address-display separation driving scheme for Y electrode lines of the plasma display panel of FIG. 1.

5 is a waveform diagram of signals applied to electrode lines of a plasma display panel according to a conventional resetting method.

FIG. 6 is a cross-sectional view illustrating wall charge distribution of one display cell at time t3 of FIG. 5.

FIG. 7 is a cross-sectional view illustrating wall charge distribution of one display cell at time t4 of FIG. 5.

8 is a waveform diagram of driving signals applied to electrode lines of a plasma display panel according to a resetting method of an exemplary embodiment of the present invention.

9 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t3 of FIG. 8.

FIG. 10 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t4 of FIG. 8.

FIG. 11 is a diagram illustrating a case where the resetting method of FIG. 8 is appropriately used according to the discharge-hold time in a previous sub-field.

FIG. 12 is a diagram illustrating a case in which the floating time in the resetting method of FIG. 8 is set to be proportional to the discharge-hold time of a previous sub-field.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ..., Xn ... X electrode line, Y ₁ , ..., Yn ... Y electrode line,

A _R1 , ..., A _Bm ... address electrode line, X _na , Y _na ... transparent electrode line,

X _nb , Y _nb ... metal electrode lines, SF1, ... SF8 ... sub-field,

S _Y ... Y drive control signal, V _G ... ground voltage,

S _X ... X drive control signal, S _A ... address drive control signal,

62 logic controller, 63 address drive,

64 ... X drive, 65 ... Y drive,

66 ... image processing unit, R1, ..., R8 ... reset cycle.

The present invention relates to a method for resetting a plasma display panel and a method for driving a plasma display panel using the resetting method. A reset method performed first in a field, such that the distribution of charges of all display cells becomes uniform and at the same time suitable for addressing to be performed in the next step, and a driving method of a plasma display panel using the reset method .

1 shows a structure of a conventional three-electrode surface discharge plasma display panel. FIG. 2 shows an example of one display cell of the panel of FIG. 1. 1 and 2, between the front and rear glass substrates 10 and 13 of a conventional surface discharge plasma display panel 1, address electrode lines A _R1 ,..., A _Bm , a dielectric layer. (11, 15), Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), phosphor 16, partition 17 and protective layer As a magnesium monoxide (MgO) layer 12 is provided.

The address electrode lines A _R1 ,..., A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied to the entire surface in front of the address electrode lines A _R1 ,..., A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 ,..., And A _Bm . These partitions 17 function to partition the discharge area of each display cell and prevent optical cross talk between each display cell. The fluorescent layer 16 is applied between the partition walls 17.

The X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) intersect the address electrode lines (A _R1 , ..., A _Bm ). It is formed in a constant pattern on the back of the front glass substrate 10. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , ..., Xn) and each Y electrode line (Y ₁ , ..., Y _n ) is a transparent electrode line of a transparent conductive material such as indium tin oxide (ITO) or the like (see FIG. 2). X _na , Y _na ) and a metal electrode line (X _nb , Y _nb of FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ,..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

In the driving method basically applied to such a plasma display panel, the resetting, addressing, and display-sustain steps are sequentially performed in the unit sub-field. In the resetting phase, the charge states of all display cells are uniform. In the addressing step, a predetermined wall voltage is generated in the selected display cells. In the discharge-hold step, a predetermined alternating voltage is applied to all the XY electrode line pairs so that display cells in which the wall voltage is formed in the addressing step cause discharge-maintain discharge. In this discharge-maintaining step, plasma is formed in the discharge space 14, i.e., the gas layer, of the selected display cells causing the discharge-maintaining discharge, and the fluorescent layer 16 is excited by the ultraviolet radiation to generate light.

FIG. 3 shows a typical driving device of the plasma display panel 1 of FIG. 1. Referring to FIG. 3, a typical driving device of the plasma display panel 1 includes an image processor 66, a logic controller 62, an address driver 63, an X driver 64, and a Y driver 65. . The image processing unit 66 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The controller 62 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 66. The address driver 63 processes the address signal S _A among the drive control signals S _A , S _Y , and S _X from the logic controller 62 to generate a display data signal, and generates the display data signal. Is applied to the address electrode lines. The X driving unit 64 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the control unit 62, and applies the X driving control signal S _X to the X electrode lines. The Y driver 65 processes the Y driving control signal S _Y among the driving control signals S _A , S _Y , and S _X from the logic controller 62, and applies the Y driving control signal S _Y to the Y electrode lines.

FIG. 4 illustrates a conventional address-display separation driving scheme for the Y electrode lines of the plasma display panel of FIG. 1. Referring to FIG. 4, each of all unit frames is divided into eight sub-fields SF1, ..., SF8 to realize time division gray scale display. Further, each sub-field SF1, ..., SF8 has a reset time R1, ..., R8, an addressing time A1, ..., A8, and a discharge-hold time S1,. .., S8).

The discharge conditions of all the display cells become uniform at each reset time R1, ..., R8 and at the same time are adapted to the addressing to be performed in the next step.

Each addressing time (A1, ..., A8) In, the address electrode lines (A _R1 of Fig. 1, ..., A _Bm) as soon applying a display data signal for each Y electrode lines (Y _1, at the same time. Scanning pulses corresponding to Y _n ) are sequentially applied. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are formed by the addressing discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

At each discharge-hold time (S1, ..., S8), all Y electrode lines (Y ₁ , ..., Y _n ) and all X electrode lines (X ₁ , ..., X _n ) Discharge-holding pulses are alternately applied to cause display discharge in discharge cells in which wall charges are formed at corresponding addressing times A1, ..., A8. Therefore, the brightness of the plasma display panel is proportional to the length of the discharge-hold time S1, ..., S8 occupied in the unit frame. The length of the discharge-hold time (S1, ..., S8) in the unit frame is 255T (T is the unit time). Therefore, it can be displayed in 256 gray scales, even if it is not displayed once in a unit frame.

Here, the time 1T corresponding to 2 ⁰ in the discharge-hold time S1 of the first sub-field SF1 is 2 ¹ in the discharge-hold time S2 of the second sub-field SF2. The corresponding time 2T corresponds to the time 4T corresponding to 2 ² in the discharge-holding time S3 of the third sub-field SF3, and the discharge-holding time of the fourth sub-field SF4 In S4), a time 8T corresponding to 2 ³ , a time 16T corresponding to 2 ⁴ in a discharge-hold time S5 of the fifth sub-field SF5, and a sixth sub-field SF6. The discharge-holding time S6 of the time 32T corresponding to 2 ⁵ , the discharge-holding time S7 of the seventh sub-field SF7 includes the time 64T corresponding to 2 ⁶ , and In the discharge-hold time S8 of the 8 sub-field SF8, a time 128T corresponding to 2 ⁷ is set, respectively.

Accordingly, if the sub-field to be displayed among the eight sub-fields is appropriately selected, display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the sub-fields.

5 illustrates driving signals applied to electrode lines of the plasma display panel 1 of FIG. 1 in the unit sub-field of FIG. 4 according to a conventional resetting method. The conventional resetting method included in the driving method of Fig. 5 is taught in Japanese Laid-Open Patent Publications 214,823 and 242,224. In FIG. 5, reference numeral S _{AR1 ..ABm} denotes a driving signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 .. Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to. FIG. 6 shows the wall charge distribution of one display cell at a time point t3 immediately after a gradual rising voltage is applied to all the Y electrode lines Y ₁ ,... Y _n at the reset time R of FIG. 5. Shows. FIG. 7 shows the wall charge distribution of one display cell at the end time t4 of the reset time R of FIG. 5. 6 and 7 the same reference numerals as used in FIG. 2 indicate the object of the same function.

Referring to FIG. 5, at the first times t1 to t2 of the resetting time R of the unit sub-field SF, the first application is applied to the X electrode lines X ₁ ,..., X _n . The voltage is continuously raised from the ground voltage (V _G ) to the second voltage (V _S ), for example, 155 volts (V). Here, the ground voltage V _G as the third voltage is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, between the X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), and the X electrode lines (X ₁ , ..., X) A weak discharge occurs between _n ) and the address electrode lines A ₁ , ..., A _m , and negative wall charges are formed around the X electrode lines X ₁ , ..., X _n . .

In the second time t2 to t3 as the wall charge accumulation time, the voltage applied to the Y electrode lines Y ₁ ,..., Y _n is the second voltage V _S , for example, 155 volts (V). ) Up to the first voltage V _SET + V _S , for example, 355 volts V, which is higher by the sixth voltage V _SET than the second voltage V _S. Here, the ground voltage V _G as a third voltage is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , A weaker discharge occurs between ..., Y _n ) and the address electrode lines A _R1 , ..., A _Bm . Here, Y electrode lines _{(Y 1, ..., Y n} ) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _The reason why the discharge between _n ) and the X electrode lines (X ₁ , ..., X _n ) becomes stronger is that the negative wall charges around the X electrode lines (X ₁ , ..., X _n ) Because they were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 6).

In the third time t3 to t4 as the wall charge distribution time, the Y electrode while the voltage applied to the X electrode lines X ₁ ,..., X _n is maintained at the second voltage V _S. The voltage applied to the lines Y ₁ ,..., Y _n is continuously lowered from the second voltage V _S to the ground voltage V _G as the third voltage. Here, the ground voltage V _G is applied to the address electrode lines A _R1 ,..., A _Bm . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around..., Y _n ) move around the X electrode lines X ₁ ,..., X _n (see FIG. 7). Accordingly, the wall electric-potential of the X electrode lines X ₁ , ..., X _n is lower than the wall potential of the address electrode lines A _R1 , ..., A _Bm and the Y electrode Higher than the wall potential of the lines Y ₁ , ..., Y _n . As a result, the addressing voltage V _A -V _G required for the counter discharge between the selected address electrode lines and the Y electrode line may be lowered at the subsequent addressing time A. FIG.

In this wall charge distribution time t3 to t4, the ground voltage V _G as the third voltage is applied to all the address electrode lines A _R1 , ..., A _Bm of the positive wall potential, The voltage applied to all the Y electrode lines Y ₁ ,..., Y _n of the negative wall potential is continuously lowered to the ground voltage V _G. Accordingly, discharge is performed between the address electrode lines A _R1 ,..., A _Bm and the Y electrode lines Y ₁ ,..., Y _n , and due to the discharge, the address electrode lines ( The positive wall charges around A _R1 , ..., A _Bm ) disappear (see FIGS. 6 and 7).

At the subsequent addressing time A, the display data signal is applied to the address electrode lines, and the Y electrode lines Y ₁ ,... _{Biased to} the fifth voltage V _SCAN lower than the second voltage V _S. , Y _n ), as the scan signal of the ground voltage V _G is sequentially applied, smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , ..., A _Bm is applied with the positive addressing voltage V _A when the display cell is selected and the ground voltage V _G when the display cell is not selected. do. Accordingly, when the display data signal of the positive addressing voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, wall charges are formed by the addressing discharge in the corresponding display cell. Wall charges do not form. Here, for a more accurate and efficient addressing discharge, the second voltage V _S is maintained in the X electrode lines X ₁ , X _n .

In the subsequent discharge-hold time _S , the discharge of the second voltage V _S is applied to all the Y electrode lines Y ₁ , ... Y _n and the X electrode lines X ₁ , ... X _n . -The sustain pulses are applied alternately, producing a discharge for discharge-maintaining in the display cells in which wall charges are formed at the corresponding addressing time (A).

According to the conventional resetting method as described above, the ground voltage V _G is applied to all the address electrode lines A _R1 , ..., A _Bm at the third time t3 to t4 as the wall charge distribution time. Since it is authorized, there are the following problems.

First, address electrode lines A _R1 , ..., A _{Bm are} connected to X electrode lines X ₁ , ..., X _n and Y electrode lines Y ₁ , ..., Y _n . Discharge is performed. As a result, the contrast performance of the plasma display device is lowered.

Second, due to the discharge, the positive wall charges around the address electrode lines A _R1 ,..., A _Bm disappear. Accordingly, the voltage between the address electrode lines A _R1 , ..., A _Bm and the Y electrode lines Y ₁ , ..., Y _n obtained due to the wall charges is relatively low, thus addressing. At time A, the addressing voltage V _A -V _G required for the counter discharge between the selected address electrode lines and the Y electrode line becomes relatively high.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for resetting a plasma display panel capable of enhancing contrast performance of a plasma display device and lowering a required addressing voltage, and a method for driving a plasma display panel using the reset method.

The method for resetting the plasma display panel according to the present invention for achieving the above object includes a front substrate and a rear substrate spaced apart from each other, the first and second display electrode lines are formed parallel to each other between the substrate, A method of resetting a plasma display panel having electrode lines intersecting with the first and second electrode lines, the method comprising a wall charge accumulation step and a wall charge distribution step.

In the wall charge accumulation step, the voltage applied to the second display electrode lines is continuously raised to the first voltage. In the wall charge distribution step, the voltage applied to the second display electrode lines is higher than the second voltage while the voltage applied to the first display electrode lines is maintained at a second voltage lower than the first voltage. A fourth voltage lower than the third voltage is applied to the address electrode lines while continuously lowering to a low third voltage.

According to the resetting method of the plasma display panel of the present invention, as the fourth voltage lower than the third voltage is applied to the address electrode lines in the wall charge distribution step, the following effects are obtained.

First, discharge from the address electrode lines to the second display electrode lines is suppressed in the wall charge distribution step. Accordingly, the contrast performance of the plasma display device can be enhanced.

Second, since the discharge from the address electrode lines to the second display electrode lines is suppressed in the wall charge distribution step, the positive wall charges formed around the address electrode lines in the wall charge accumulation step cause the wall charges to be discharged. It can be preserved to the maximum without being destroyed in the distribution step. Accordingly, since the positive wall potentials of the address electrode lines are not lowered, the addressing voltage required for the counter discharge between the selected address electrode lines and the second display electrode lines is increased during the addressing time following the reset time. Do not.

The driving method of the present invention for achieving the above object has a front substrate and a rear substrate spaced apart from each other, the first and second display electrode lines are formed parallel to each other between the substrate, the address electrode lines are For a plasma display panel formed to intersect with the first and second electrode lines, the unit frame is divided into a plurality of sub-fields for time division gray scale display, and each of the sub-fields resets, addresses, and discharges. A driving method of the plasma display panel in which the holding steps are performed, wherein the resetting step of at least one sub-field among the plurality of sub-fields comprises the resetting method of the present invention.

Hereinafter, preferred embodiments according to the present invention will be described in detail.

FIG. 8 illustrates driving signals applied to electrode lines of the plasma display panel 1 of FIG. 1 in the unit sub-field of FIG. 4 according to the driving method including the resetting method of the embodiment of the present invention. In FIG. 8, the same reference numerals as used in FIG. 5 indicate objects of the same function. FIG. 9 is any one at a time point t3 immediately after a gradual rising voltage is applied to the Y electrode lines Y ₁ ,... Y _n as second display electrode lines at the reset time R of FIG. 8. The wall charge distribution of the display cell is shown. FIG. 10 shows the wall charge distribution of one display cell at the end time t4 of the reset time R of FIG. 8. 9 and 10, the same reference numerals as used in FIG. 2 indicate objects of the same function.

Referring to FIG. 8, in the first times t1 to t2 of the resetting time R of the unit sub-field SF, first applied to the X electrode lines X ₁ ,..., X _n . The voltage is continuously raised from the ground voltage V _G to the second voltage V _S , for example 155 volts (V). Here, the Y electrode lines Y ₁ ,..., Y _n as second display electrode lines and the address electrode lines A _R1 , ..., A _Bm are ground voltages V _G as a third voltage. ) Is applied. Accordingly, between the X electrode lines X ₁ ,..., X _n as the first display electrode lines and the Y electrode lines Y ₁ ,..., Y _n , and the X electrode lines X. A weak discharge occurs between ₁ , ..., X _n ) and the address electrode lines A ₁ , ..., A _m , and is negatively connected around the X electrode lines X ₁ , ..., X _n . Polar wall charges are formed.

In the second time t2 to t3 as the wall charge accumulation time, the voltage applied to the Y electrode lines Y ₁ ,..., Y _n is the second voltage V _S , for example, 155 volts (V). ) Up to the first voltage V _SET + V _S , for example, 355 volts V, which is higher by the sixth voltage V _SET than the second voltage V _S. Here, the ground voltage V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , A weaker discharge occurs between ..., Y _n ) and the address electrode lines A _R1 , ..., A _Bm . Here, Y electrode lines _{(Y 1, ..., Y n} ) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _The reason why the discharge between _n ) and the X electrode lines (X ₁ , ..., X _n ) becomes stronger is that the negative wall charges around the X electrode lines (X ₁ , ..., X _n ) Because they were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 9).

In the third time t3 to t4 as the wall charge distribution time, the Y electrode while the voltage applied to the X electrode lines X ₁ ,..., X _n is maintained at the second voltage V _S. The voltage applied to the lines Y ₁ ,..., Y _n is continuously lowered from the second voltage V _S to the ground voltage V _G as the third voltage. Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around..., Y _n ) move around the X electrode lines X ₁ ,..., X _n (see FIG. 10). Accordingly, the wall electric-potential of the X electrode lines X ₁ , ..., X _n is lower than the wall potential of the address electrode lines A _R1 , ..., A _Bm and the Y electrode Higher than the wall potential of the lines Y ₁ , ..., Y _n . As a result, the addressing voltage V _A -V _G required for the counter discharge between the selected address electrode lines and the Y electrode line may be lowered at the subsequent addressing time A. FIG.

In this wall charge distribution time t3 to t4, the negative polarity as the fourth voltage lower than the ground voltage V _G is applied to all the address electrode lines A _R1 , ..., A _Bm of the positive wall potential. The voltage V _AB is applied. Accordingly, when the voltage applied to all the Y electrode lines (Y ₁ ,..., Y _n ) of the negative wall potential is continuously lowered to the ground voltage (V _G ) as the third voltage, the fourth Discharge from address electrode lines A _R1 , ..., A _Bm to Y electrode lines Y ₁ , ..., Y _n during the application time T _AB of the negative voltage V _AB as a voltage Since this is suppressed, the following effects can be obtained.

First, the contrast performance of the plasma display device can be enhanced.

Second, the positive wall charges formed around the address electrode lines A _R1 ,..., And A _Bm at the second time t2 to t3 as the wall charge accumulation time are at the wall charge distribution time t3 to t4. It can be preserved as much as possible without being destroyed. Accordingly, since the positive wall potentials of the address electrode lines A _R1 ,..., And A _Bm are not lowered, the address electrode lines and the Y electrodes selected at the addressing time A subsequent to the reset time R are obtained. The addressing voltage required for the opposing discharge between the lines does not increase.

At the subsequent addressing time A, the display data signal is applied to the address electrode lines, and the Y electrode lines Y ₁ ,... _{Biased to} the fifth voltage V _SCAN lower than the second voltage V _S. , Y _n ), as the scan signal of the ground voltage V _G is sequentially applied, smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , ..., A _Bm is applied with the positive addressing voltage V _A when the display cell is selected and the ground voltage V _G when the display cell is not selected. do. Accordingly, when the display data signal of the positive addressing voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, wall charges are formed by the addressing discharge in the corresponding display cell. Wall charges do not form. Here, for a more accurate and efficient addressing discharge, the second voltage V _S is maintained at the X electrode lines X ₁ ,... X _n .

In the subsequent discharge-hold time _S , the discharge of the second voltage V _S is applied to all the Y electrode lines Y ₁ , ... Y _n and the X electrode lines X ₁ , ... X _n . -The sustain pulses are applied alternately, producing a discharge for discharge-maintaining in the display cells in which wall charges are formed at the corresponding addressing time (A).

On the other hand, basically, when the discharge-hold time S of one sub-field is set relatively short, wall charges are formed relatively insufficient at the next reset time R of the sub-field SF. . Accordingly, wall charges are insufficiently formed in the display cells selected at the addressing time A, and thus, the discharge at the discharge-hold time S may be weakened. That is, the uniformity and stability of the display may be degraded. This fundamental problem can also be improved as follows by the application of the resetting method according to the present invention.

FIG. 11 shows a case where the resetting method of FIG. 8 is appropriately used according to the discharge-hold time S1 to S8 in the previous sub-field. In FIG. 11, the same reference numerals as used in FIGS. 4 and 8 indicate the objects of the same function. 11 and 8, whether or not the negative voltage V _AB is applied in the current sub-field is set according to the discharge-holding time S1 to S8 in the previous sub-field.

The wall charge distribution time of FIG. 8 for the reset time R6 to R8 and R1 of the sub-fields SF6 to SF8 and SF1 having a relatively long discharge-hold time S5 to S8 of the previous sub-field. A negative voltage V _AB as a fourth voltage is applied to the address electrode lines A _R1 ,..., and A _Bm at some time T _AB during the times t3 to t4. Further, in the resetting time R2 to R5 of the sub-fields SF2 to SF5 of which the discharge-sustaining time S1 to S4 of the previous sub-field is relatively short, the address electrode lines A _R1,. .., A _Bm ) is continuously applied with the ground voltage V _G as the third voltage. Accordingly, the discharge-hold time S1 to S8 of the previous sub-field can more uniformly affect the operation of the current sub-field.

FIG. 12 illustrates a time T _AB during which the negative voltage V _AB as the fourth voltage is applied to the address electrode lines A _R1 ,..., A _Bm in the resetting method of FIG. 8. Shows a case where it is set to be proportional to the discharge-hold time (S1 to S8). In Fig. 12, the same reference numerals as in Figs. 4 and 8 indicate the objects of the same function. 12 and 8, in the resetting time R1 to R8 of each of the sub-fields SF1 to SF8, the negative-voltage application time T included in the wall charge distribution time t3 to t4. _AB is proportional to the discharge-hold time S8, S1 to S7 of the previous sub-fields SF8, SF1 to SF7. For example, in the reset time R1 of the first sub-field SF1 having the longest discharge-hold time S8 of the previous sub-field SF8, the address electrode lines A _R1 ... , A _Bm ), the negative-voltage application time T _AB occupies all of the wall charge distribution times t3 to t4. In addition, in the resetting time R2 of the second sub-field SF2 having the shortest discharge-holding time S1 of the previous sub-field SF1, the address electrode lines A _R1 ... , A _Bm ), the negative-voltage application time T _AB is not present within the wall charge distribution time t3 to t4. Accordingly, the discharge-hold time S1 to S8 of the previous sub-field can more uniformly affect the operation of the current sub-field.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

As described above, according to the resetting method of the plasma display panel and the driving method of the plasma display panel using the resetting method according to the present invention, in the wall charge distribution step, the address electrode lines are lower than the third voltage. As the fourth voltage is applied, the following effects are obtained.

First, discharge from the address electrode lines to the Y electrode lines is suppressed in the wall charge distribution step. Accordingly, the contrast performance of the plasma display device can be enhanced.

Second, since the discharge from the address electrode lines to the Y electrode lines is suppressed in the wall charge distribution step, the positive wall charges formed around the address electrode lines in the wall charge accumulation step disappear in the wall charge distribution step. Can be preserved as much as possible. Accordingly, since the positive wall potential of the address electrode lines is not lowered, the addressing voltage required for the counter discharge between the selected address electrode lines and the Y electrode lines does not increase at the addressing time following the reset time.

Claims (8)

A front substrate and a rear substrate spaced apart from each other, wherein the first and second display electrode lines are formed parallel to each other, and the address electrode lines are formed to intersect with the first and second electrode lines. In the method of resetting a plasma display panel, A wall charge accumulation step of continuously increasing a voltage applied to the second display electrode lines to a first voltage; And The voltage applied to the second display electrode lines is continuously maintained to a third voltage lower than the second voltage while the voltage applied to the first display electrode lines is maintained at a second voltage lower than the first voltage. And a wall charge distribution step of applying a fourth voltage lower than the third voltage to the address electrode lines while lowering the plasma display panel. According to claim 1, In the wall charge distribution step, And a time when the fourth voltage is applied to the address electrode lines is a part of the execution time of the wall charge distribution step. The method of claim 1, And a voltage applied to the first display electrode lines is continuously increased to the second voltage immediately before the wall charge accumulation step is performed. A front substrate and a rear substrate spaced apart from each other, wherein the first and second display electrode lines are formed parallel to each other, and the address electrode lines are formed to intersect with the first and second electrode lines. A method of driving a plasma display panel in which a unit frame is divided into a plurality of sub-fields for time division gray scale display, and reset, addressing, and discharge-holding steps are performed in each of the sub-fields. To The resetting of at least one sub-field of the plurality of sub-fields, A wall charge accumulation step of continuously increasing a voltage applied to the second display electrode lines to a first voltage; And The voltage applied to the second display electrode lines is continuously maintained to a third voltage lower than the second voltage while the voltage applied to the first display electrode lines is maintained at a second voltage lower than the first voltage. And a wall charge distribution step of applying a fourth voltage lower than the third voltage to the address electrode lines. The method of claim 4, wherein in the wall charge distribution step, And a time when the fourth voltage is applied to the address electrode lines is a part of the execution time of the wall charge distribution step. The method of claim 4, wherein And a voltage applied to the first display electrode lines immediately before the wall charge accumulation step is continuously increased to the second voltage. The method of claim 4, wherein And the fourth voltage is applied to the sub-fields of the sub-fields of which the execution time of the discharge-holding step in the previous sub-field is long. The method of claim 4, wherein And the application time of the fourth voltage in the wall charge distribution step of each of the sub-fields is proportional to the execution time of the discharge-maintaining step of the previous sub-field.

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