KR20050106550A - Method for driving plasma display panel wherein effective resetting is performed - Google Patents

Abstract

The present invention has a front substrate and a rear substrate spaced apart from each other, the first and second display electrode lines are formed parallel to each other between the substrates, the address electrode lines with respect to the first and second electrode lines As a method of driving a discharge display panel in which a unit frame is divided into a plurality of subfields for time division gray scale display, and reset, addressing, and discharge-maintaining are performed in each of the subfields with respect to the plasma display panel formed to intersect. , Steps (a) to (d). In step (a), the potential applied to the second display electrode lines is continuously raised to the first potential at the first rate of rise. In step (b), the potential applied to the second display electrode lines is rapidly raised from the first potential to the second potential at a second rate of increase higher than the first rate of increase. In step (c), the potential applied to the second display electrode lines is continuously lowered to a third potential lower than the second potential as the first drop rate. In step (d), the potential applied to the second display electrode lines is drastically lowered from the third potential to the fourth potential with a second falling rate higher than the first falling rate.

Description

Method for driving plasma display panel where effective resetting is performed}

The present invention relates to a method of driving a discharge display panel, and more particularly, to a plasma display panel having a three-electrode surface discharge structure, a unit frame is divided into a plurality of subfields for time division gray scale display. A method of driving a discharge display panel in which resetting, addressing, and discharge-holding are performed in each of the subfields.

FIG. 1 shows the structure of a three-electrode surface discharge plasma display panel as a conventional discharge display panel. FIG. 2 shows an example of one display cell of the panel of FIG. 1. 1 and 2, between the front and rear glass substrates 10 and 13 of a conventional surface discharge plasma display panel 1, address electrode lines A _R1 ,..., A _Bm , a dielectric layer. (11, 15), Y electrode lines (Y ₁ , ..., Y _n ), X electrode lines (X ₁ , ..., X _n ), phosphor 16, partition 17 and protective layer As a magnesium monoxide (MgO) layer 12 is provided.

The address electrode lines A _R1 ,..., A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied to the entire surface in front of the address electrode lines A _R1 ,..., A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 ,..., And A _Bm . These partitions 17 function to partition the discharge area of each display cell and prevent optical cross talk between each display cell. The fluorescent layer 16 is applied between the partition walls 17.

The X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) intersect the address electrode lines (A _R1 , ..., A _Bm ). It is formed in a constant pattern on the back of the front glass substrate 10. Each intersection sets a corresponding display cell. Each X electrode line (X ₁ , ..., Xn) and each Y electrode line (Y ₁ , ..., Y _n ) is a transparent electrode line of a transparent conductive material such as indium tin oxide (ITO) or the like (see FIG. 2). X _na , Y _na ) and a metal electrode line (X _nb , Y _nb of FIG. 2) for increasing conductivity are formed. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ,..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The plasma forming gas is sealed in the discharge space 14.

In the driving method basically applied to such a discharge display panel, the resetting, addressing, and display-sustain steps are sequentially performed in the unit subfield. In the resetting phase, the charge states of all display cells are uniform. In the addressing step, a predetermined wall voltage is generated in the selected display cells. In the discharge-hold step, a predetermined alternating voltage is applied to all the XY electrode line pairs so that display cells in which the wall voltage is formed in the addressing step cause discharge-maintain discharge. In this discharge-maintaining step, plasma is formed in the discharge space 14, i.e., the gas layer, of the selected display cells causing the discharge-maintaining discharge, and the fluorescent layer 16 is excited by the ultraviolet radiation to generate light.

FIG. 3 shows a typical driving device of the plasma display panel 1 of FIG. 1. Referring to FIG. 3, a typical driving device of the plasma display panel 1 includes an image processor 66, a logic controller 62, an address driver 63, an X driver 64, and a Y driver 65. . The image processing unit 66 converts an external analog image signal into a digital signal to convert an internal image signal, for example, 8 bits of red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The controller 62 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 66. The address driver 63 processes the address signal S _A among the drive control signals S _A , S _Y , and S _X from the logic controller 62 to generate a display data signal, and generates the display data signal. Is applied to the address electrode lines. The X driving unit 64 processes the X driving control signal S _X among the driving control signals S _A , S _Y , and S _X from the control unit 62, and applies the X driving control signal S _X to the X electrode lines. The Y driver 65 processes the Y driving control signal S _Y among the driving control signals S _A , S _Y , and S _X from the logic controller 62, and applies the Y driving control signal S _Y to the Y electrode lines.

FIG. 4 illustrates a conventional address-display separation driving scheme for the Y electrode lines of the plasma display panel of FIG. 1. Referring to FIG. 4, each of all unit frames is divided into _eight subfields SF ₁ , SF 8 to realize time division gray scale display. In addition, each subfield SF ₁ , ..., SF ₈ has a reset time R ₁ , ..., R ₈ , an addressing time A ₁ , ..., A ₈ , and a discharge-hold It is divided by time S ₁ , ..., S ₈ .

The discharge conditions of all the display cells become uniform at each reset time R ₁ ,..., R ₈ , while being adapted to the addressing to be performed in the next step.

At each addressing time (A ₁ , ..., A ₈ ), a display data signal is applied to the address electrode lines (A _R1 , ..., A _{Bm in} FIG. 1) and at the same time, each Y electrode line (Y ₁ , ..., Y _n ), the scanning pulses are sequentially applied. Accordingly, when a high level display data signal is applied while the scan pulse is applied, wall charges are formed by addressing discharge in the corresponding discharge cell, and wall charges are not formed in the discharge cell that is not.

At each discharge-hold time (S ₁ , ..., S ₈ ), all Y electrode lines (Y ₁ , ..., Y _n ) and all X electrode lines (X ₁ , ..., X _n) The discharge-maintenance pulses are alternately applied to generate the display discharge in the discharge cells in which the wall charges are formed at the corresponding addressing times A ₁ , ..., A ₈ . Therefore, the luminance of the plasma display panel is proportional to the length of the discharge-hold time S ₁ , ..., S ₈ occupied in the unit frame. The length of the discharge-hold time S ₁ , ..., S ₈ occupied in the unit frame is 255T (T is the unit time). Therefore, it can be displayed in 256 gray scales, even if it is not displayed once in a unit frame.

Here, the first sub-field (SF ₁₎ discharge-maintaining time (S _1), the time (1T) corresponding to ^20, the second discharge of the sub-field (SF ₂₎ - a holding time (S _2), the two the time (2T) equivalent to ^1, the third sub-field (SF ₃₎ discharge of-discharge of the sustain time period (4T) corresponding to the in ² 2 (S ₃₎ is the fourth sub-field (SF ₄₎ - In the holding time S ₄ , a time 8T corresponding to 2 ³ , and in the discharge-holding time S ₅ of the fifth subfield SF ₅ , a time 16T corresponding to 2 ⁴ , a sixth sub in time corresponding to ²⁶ the retention time (S ₇₎ - a holding time (S _6), this time (32T) corresponding to ^25, a seventh discharge of the subfield (SF ₇₎ - a field (SF ₆₎ discharge of 64T and a time 128T corresponding to 2 ⁷ are set in the discharge-hold time S ₈ of the eighth subfield SF ₈ , respectively.

Accordingly, if a subfield to be displayed among the eight subfields is appropriately selected, 256 gray levels may be displayed including all zero (zero) grays not displayed in any subfields.

FIG. 5 shows driving signals applied to electrode lines of the plasma display panel 1 of FIG. 1 in each unit subfield of FIG. 4 according to a conventional resetting method. The conventional resetting method included in the driving method of Fig. 5 is taught in Japanese Laid-Open Patent Publications 214,823 and 242,224. In FIG. 5, reference numeral S _{AR1 ..ABm} denotes a driving signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 .. Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to.

Referring to FIG. 5, in the first time t ₁ to t ₂ of the resetting time R of the unit subfield SF, the first application is applied to the X electrode lines X ₁ ,..., X _n . The potential to be increased is continuously raised from the ground potential V _G to the potential of the second potential V _S. Here, the ground potential V _G is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, between the X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), and the X electrode lines (X ₁ , ..., X) A weak discharge occurs between _n ) and the address electrode lines A ₁ , ..., A _m , and negative wall charges are formed around the X electrode lines X ₁ , ..., X _n . .

In the second time t ₂ to t ₃ as the wall charge accumulation time, the potential applied to the Y electrode lines Y ₁ ,..., Y _n is from the second potential V _S to the second potential V. _It is continuously raised to the potential of the first potential V _{_ PR that} is higher by the fifth potential V _SET than _S ). Here, the ground potential V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ..., A _Bm . Accordingly, a weak discharge occurs between the Y electrode lines (Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n ), while the Y electrode lines (Y ₁ , A weaker discharge occurs between ..., Y _n ) and the address electrode lines A _R1 , ..., A _Bm . Here, Y electrode lines _{(Y 1, ..., Y n} ) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _The reason why the discharge between _n ) and the X electrode lines (X ₁ , ..., X _n ) becomes stronger is that the negative wall charges around the X electrode lines (X ₁ , ..., X _n ) Because they were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm .

In the third time t ₃ to t ₄ as the wall charge distribution time, in a state where the potential applied to the X electrode lines X ₁ ,..., X _n is maintained at the second potential V _S , The potential applied to the Y electrode lines Y ₁ ,..., Y _n is continuously lowered from the second potential V _S to the ground potential V _G as the third potential. Here, the ground potential V _G is applied to the address electrode lines A _R1 ,..., A _Bm . Accordingly, due to the weak discharge between the X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), the Y electrode lines (Y ₁ ,. Some of the negative wall charges around .., Y _n ) move around the X electrode lines X ₁ ,..., X _n . Accordingly, the wall electric-potential of the X electrode lines X ₁ , ..., X _n is lower than the wall potential of the address electrode lines A _R1 , ..., A _Bm and the Y electrode Higher than the wall potential of the lines Y ₁ , ..., Y _n . As a result, the addressing voltage V _A -V _G required for the counter discharge between the selected address electrode lines and the Y electrode line may be lowered at the subsequent addressing time A. FIG. Meanwhile, since the ground potential V _G is applied to all the address electrode lines A _R1 ,..., And A _Bm , the address electrode lines A _R1 ,..., A _Bm are X electrode lines ( Discharge is performed on X ₁ , ..., X _n ) and Y electrode lines (Y ₁ , ..., Y _n ), and due to the discharge, the address electrode lines (A _R1 , ..., A) _Bm ) the positive wall charges around it disappear.

In the subsequent addressing time A, the display data signal is applied to the address electrode lines, and the Y electrode lines Y ₁ ,... _{Biased to} the sixth potential V _SCAN lower than the second potential V _S. , Y _n ), as the scan signals of the ground potential V _G are sequentially applied, smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , ..., A _Bm is applied with the positive addressing potential V _A when the display cell is selected and the ground potential V _G when the display cell is not selected. do. Accordingly, when the display data signal of the positive addressing potential V _A is applied while the scan pulse of the ground potential V _G is applied, wall charges are formed by the addressing discharge in the corresponding display cell. Wall charges do not form. Here, for a more accurate and efficient addressing discharge, the second potential V _S is maintained at the X electrode lines X ₁ , ... X _n .

Discharging the second electrical potential (V _S) for a holding time in the (S), all the Y electrode lines (Y _1, ... Y _n) and the X electrode lines _{(X 1, ... X n)} - leading to the discharge -The sustain pulses are applied alternately, producing a discharge for discharge-maintaining in the display cells in which wall charges are formed at the corresponding addressing time (A).

According to the conventional driving method as described above, the wall charge accumulation time (t ₂ ~ t ₃ ) and the wall charge distribution time (t ₃ ~ t ₄ ) of the limited reset time (R) of the unit subfield (SF), respectively Use a single rate of climb and a single rate of descent. Accordingly, since the single rising rate of the limited wall charge accumulation time t ₂ to t ₃ and the single falling rate of the limited wall charge distribution time t ₃ to t ₄ must each be set high, stable and efficient resetting is performed. Can't. In this case, the addressing following the reset becomes unstable, and thus the sustain-discharge becomes unstable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method capable of enhancing the display performance of a discharge display device in a method of driving a discharge display panel, by performing stable and efficient reset in a limited time.

A method of the present invention for achieving the above object has a front substrate and a back substrate spaced apart from each other, the first and second display electrode lines are formed parallel to each other between the substrates, the address electrode lines are the first substrate And a unit frame is divided into a plurality of subfields for time division gradation display for a plasma display panel formed to intersect with the second electrode lines, and reset, addressing, and discharge-maintaining are performed in each of the subfields. A method of driving a discharge display panel performed, comprising steps (a) to (d). In the step (a), the potential applied to the second display electrode lines is continuously raised to the first potential at the first rising rate. In the step (b), the potential applied to the second display electrode lines is rapidly raised from the first potential to the second potential at a second rising rate higher than the first rising rate. In the step (c), the potential applied to the second display electrode lines is continuously lowered to a third potential lower than the second potential as a first falling rate. In the step (d), the potential applied to the second display electrode lines is rapidly lowered from the third potential to the fourth potential with a second falling rate higher than the first falling rate.

According to the driving method of the discharge display panel of the present invention, the wall charges can be stably accumulated at a relatively low rise rate in the step (a), and rapidly at a limited time as the high rise rate is applied in the step (b). Can increase the potential. Likewise, the wall charges can be stably distributed with a relatively low rate of descent in step (c), and the potential can be lowered quickly in a limited time as a high rate of descent is applied in step (d). Accordingly, the display performance of the discharge display device can be enhanced by performing stable and efficient reset in a limited time.

Hereinafter, preferred embodiments according to the present invention will be described in detail. Here, the technique described in FIGS. 1 to 4 is equally applied to the present embodiment.

6 illustrates driving signals applied to electrode lines of the plasma display panel 1 of FIG. 1 in the unit subfield SF of FIG. 4 by the driving method of an exemplary embodiment of the present invention. In FIG. 6, reference numeral S _{AR1 ..ABm} denotes a driving signal applied to each address electrode line (A _R1 , A _G1 ,..., A _Gm , A _{Bm in} FIG. 1), and S _{X1 ..Xn} denotes an X electrode. The driving signal applied to the lines (X ₁ , ... X _{n in} FIG. 1), and S _Y1 , ..., S _Yn are the respective Y electrode lines (Y ₁ , ... Y _{n in} FIG. 1). Indicates a drive signal applied to. FIG. 7 illustrates a wall charge distribution of one display cell at time t ₄ of FIG. 6. FIG. 8 illustrates a wall charge distribution of one display cell at time t ₇ of FIG. 6.

6 to 8, driving signals applied to the electrode lines of the plasma display panel 1 of FIG. 1 in the unit subfield SF of FIG. 4 will be described as follows.

In the initial time t ₁ to t ₂ of the resetting time R _A of the unit subfield SF _A , the potential applied to the X electrode lines X ₁ ,..., X _n is _first grounded. The voltage is continuously raised from V _G to the fifth potential V _S. Here, the ground potential V _G is applied to the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ,..., A _Bm . Accordingly, between the X electrode lines (X ₁ , ..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ), and the X electrode lines (X ₁ , ..., X) A weak discharge occurs between _n ) and the address electrode lines A ₁ , ..., A _m , and negative wall charges are formed around the X electrode lines X ₁ , ..., X _n . .

The first wall charge storage time (t ₂ ~ t ₃₎ In, Y electrode lines from the fifth voltage potential is a fifth potential (V _S) applied to the _{(Y 1, ..., Y n} ) (V S) It is further raised continuously with the first rate of rise up to the first potential. Further, in the second wall charge accumulation time t ₃ to t ₄ , the potential applied to the Y electrode lines Y ₁ ,..., Y _n is from the first potential at a second rising rate higher than the first rising rate. the rapidly increased to the second potential (V_ _PR). Here, the ground potential V _G is applied to the X electrode lines X ₁ ,..., X _n and the address electrode lines A _R1 ..., A _Bm .

Between the wall charge storage time (t ₂ ~ t ₄₎ as described above, the Y-electrode lines (Y _1, ..., Y _n) and the X electrode lines (X _1, ..., X _n) weak While a discharge occurs, a weaker discharge occurs between the Y electrode lines Y ₁ ,..., Y _n and the address electrode lines A _R1 ..., A _Bm . Here, Y electrode lines (Y _1, ..., Y _n) and the address electrode lines _{(A R1, ..., A Bm} ) than the discharge electrode line Y between the (Y _1, ..., Y _n) and the X-electrode lines (X _1, ..., X _n) because the discharge is stronger between is, the X electrode lines (X _1, ..., X _n) of negative polarity wall around Because the charges were formed. Accordingly, many negative wall charges are formed around the Y electrode lines (Y ₁ , ..., Y _n ), and positive wall charges are formed around the X electrode lines (X ₁ , ..., X _n ). Are formed, and less positive wall charges are formed around the address electrode lines A _R1 , ..., A _Bm (see FIG. 7).

At the first wall charge distribution time t ₅ to t ₆ , the Y electrode in a state where the potential applied to the X electrode lines X ₁ ,..., X _n is maintained at the fifth potential V _S. The first drop rate from the fifth potential V _S to the third potential lower than the ground potential V _G , that is, the scan potential V _{SC_L} , is applied to the lines Y ₁ ,..., And Y _n . As it descends continuously. In the second wall charge distribution time t ₆ to t ₇ , the Y electrode in a state where the potential applied to the X electrode lines X ₁ ,..., X _n is maintained at the fifth potential V _S. The potential applied to the lines Y ₁ ,..., And Y _n is drastically lowered from the third potential V _{_ PF} to the fourth potential V _{_ PF with a} lowering rate higher than the first falling rate. Here, the ground potential V _G is applied to the address electrode lines A _R1 ,..., A _Bm .

In the wall charge distribution time (t ₅ ~ t ₇₎ as described above, X electrode lines _{(X 1, ..., X n} ) and Y electrode lines between weak _{(Y 1, ..., Y n} ) Due to the discharge, some of the negative wall charges around the Y electrode lines (Y ₁ , ..., Y _n ) move around the X electrode lines (X ₁ , ..., X _n ) (FIG. 8). Accordingly, the wall electric-potential of the X electrode lines X ₁ , ..., X _n is lower than the wall potential of the address electrode lines A _R1 , ..., A _Bm and the Y electrode Higher than the wall potential of the lines Y ₁ , ..., Y _n . As a result, the addressing voltage V _A -V _G required for the counter discharge between the selected address electrode lines and the Y electrode line may be lowered at the subsequent addressing time A. FIG. Meanwhile, since the ground potential V _G is applied to all the address electrode lines A _R1 ,..., And A _Bm , the address electrode lines A _R1 ,..., A _Bm are X electrode lines ( Discharge is performed on X ₁ , ..., X _n ) and Y electrode lines (Y ₁ , ..., Y _n ), and due to the discharge, the address electrode lines (A _R1 , ..., A) _Bm ) the positive wall charges around it disappear (see FIG. 8).

On the other hand, in the wall charge accumulation time (t ₂ ~ t ₄ ), the wall charges can be stably accumulated at a relatively low rate of increase in the first wall charge accumulation time (t ₂ ~ t ₃ ), the second wall charge As a high ascent rate is applied at the accumulation times t ₃ to t ₄ , the potential can be quickly increased in a limited time. In addition, in the wall charge distribution time (t ₅ ~ t ₇ ), the wall charges can be stably distributed at a relatively low falling rate in the first wall charge distribution time (t ₅ ~ t ₆ ), the second wall As a high rate of descent is applied at the charge distribution times t ₆ to t ₇ , the potential can be lowered quickly in a limited time. Accordingly, the display performance of the discharge display device can be enhanced by performing stable and efficient reset in a limited time.

For reference, wherein if as V _OPPR an appropriate difference between the first potential and the second potential (V_ _PR), the relationship V _OPPR on obtained by the repeated experiment the first increase rate are given in Table 1 below .

First ascent rate (V / ) V _OPPR (V) 1.5 70-80 2.0 60 to 65 2.5 50-55 3.0 30 to 35 3.5 25-30

Let X be the first ascent rate and derive a relational expression from Table 1 below.

Further, if an appropriate difference value between the third potential V _{SC_L} and the fourth potential V _{_ PF} is V _OPPF, the relationship of V _OPPF to the first falling rate obtained by the repeated experiment is as follows. Table 2 is as follows.

1st descent rate (V / ) V _OPPF (V) 1.5 55 to 65 2.0 45-50 2.5 35 to 45 3.0 25-30 3.5 15 to 20

Let Y be the second ascension rate and derive a relational expression from Table 1 below.

On the other hand, the appropriate positive pulse width of the second electric potential (V_ _PR) if _OPPR as T, the relationship T _OPPR for the first increase rate obtained by repeated experiments are given in Table 3 below.

First ascent rate (V / ) T _OPPR ( ) 1.5 30 to 40 2.0 25-30 2.5 15 to 20 3.0 10 to 12 3.5  8 to 10

When the appropriate falling pulse width of the fourth potential V _{_ PF} is T _OPPF, the relationship of T _OPPF to the first falling rate obtained by repeated experiments is shown in Table 4 below.

1st descent rate (V / ) T _OPPF ( ) 1.5 45-50 2.0 25 to 35 2.5 15 to 20 3.0 10 to 15 3.5  8 to 13

Next, at the addressing time A, the display data signal is applied to the address electrode lines, and the Y electrode lines Y ₁ , which are biased to the sixth potential V _{SC_H} lower than the fifth potential V _S. As the scan signals of the third potential V _{SC_L} lower than the ground potential V _G are sequentially applied to Y _n ), smooth addressing may be performed. The display data signal applied to each of the address electrode lines A _R1 , ..., A _Bm is applied with the positive addressing potential V _A when the display cells are selected and the ground potential V _G when the display cells are not selected. do. Accordingly, when the display data signal of the positive addressing potential V _A is applied while the scan pulse of the ground potential V _G is applied, wall charges are formed by the addressing discharge in the corresponding display cell. Wall charges do not form. Here, for a more accurate and efficient addressing discharge, the fifth potential V _S is maintained at the X electrode lines X ₁ , ... X _n .

In the subsequent discharge-hold time _S , the discharge of the fifth potential V _S is applied to all of the Y electrode lines Y ₁ , ... Y _n and the X electrode lines X ₁ , ... X _n . -The sustain pulses are applied alternately, producing a discharge for discharge-maintaining in the display cells in which wall charges are formed at the corresponding addressing time (A).

As described above, according to the driving method of the discharge display panel according to the present invention, in the wall charge accumulation time (t ₂ ~ t ₄ ), it is relatively low in the first wall charge accumulation time (t ₂ ~ t ₃ ) As the rate of increase, the wall charges can be stably accumulated, and as the high rate of increase is applied in the second wall charge accumulation times t ₃ to t ₄ , the potential can be quickly increased in a limited time. In addition, in the wall charge distribution time (t ₅ ~ t ₇ ), the wall charges can be stably distributed at a relatively low falling rate in the first wall charge distribution time (t ₅ ~ t ₆ ), the second wall As a high rate of descent is applied at the charge distribution times t ₆ to t ₇ , the potential can be lowered quickly in a limited time. Accordingly, the display performance of the discharge display device can be enhanced by performing stable and efficient reset in a limited time.

The present invention is not limited to the above embodiments, but may be modified and improved by those skilled in the art within the spirit and scope of the invention as defined in the claims.

1 is an internal perspective view showing the structure of a plasma display panel of a three-electrode surface discharge method as a conventional discharge display panel.

FIG. 2 is a cross-sectional view illustrating an example of one display cell of the panel of FIG. 1.

3 is a block diagram illustrating a conventional driving device of the plasma display panel of FIG. 1.

FIG. 4 is a timing diagram illustrating a conventional address-display separation driving scheme for Y electrode lines of the plasma display panel of FIG. 1.

5 is a waveform diagram of signals applied to electrode lines of a plasma display panel by a conventional driving method.

6 is a waveform diagram of signals applied to electrode lines of a plasma display panel by a driving method of an embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t ₄ of FIG. 6.

FIG. 8 is a cross-sectional view illustrating a wall charge distribution of one display cell at time t ₇ of FIG. 6.

<Explanation of symbols for the main parts of the drawings>

1 ... plasma display panel, 10 ... front glass substrate,

11, 15 dielectric layer, 12 protective layer,

13 ... back glass substrate, 14 ... discharge space,

16 fluorescent layers, 17 bulkheads,

X ₁ , ..., Xn ... X electrode line, Y ₁ , ..., Yn ... Y electrode line,

A _R1 , ..., A _Bm ... address electrode line, X _na , Y _na ... transparent electrode line,

X _nb , Y _nb ... metal electrode line, SF ₁ , ... SF ₈ ... subfield,

S _Y ... Y drive control signal, V _G ... ground potential,

S _X ... X drive control signal,

S _A ... address drive control signal,

62 logic controller, 63 address drive,

64 ... X drive, 65 ... Y drive,

66 ... image processing unit, R ₁ , ..., R ₈ ... reset cycle.

Claims (4)

A front substrate and a rear substrate spaced apart from each other, wherein the first and second display electrode lines are formed parallel to each other, and the address electrode lines are formed to intersect with the first and second electrode lines. A method of driving a discharge display panel in which a unit frame is divided into a plurality of subfields for time division gray scale display, and reset, addressing, and discharge-holding steps are performed in each of the subfields. , The resetting step of each of the subfields, (a) continuously raising a potential applied to the second display electrode lines to a first potential at a first rising rate; (b) rapidly raising a potential applied to the second display electrode lines from the first potential to a second potential at a second rate of increase higher than the first rate of increase; (c) continuously lowering the potential applied to the second display electrode lines to a third potential lower than the second potential as a first falling rate; And and d) rapidly lowering the potential applied to the second display electrode lines from the third potential to the fourth potential at a second rate lower than the first rate of decline. The method of claim 1, wherein in steps (a) to (d), And a potential applied to the address electrode lines is maintained at a ground potential lower than the first potential and higher than the third potential. The method of claim 2, wherein in steps (c) and (d), And a potential applied to the first display electrode lines is maintained at a fifth potential lower than the first potential and higher than the ground potential. The method of claim 3, A method of driving a discharge display panel in which a potential applied to the first display electrode lines is continuously raised to the fifth potential immediately before the potential applied to the second display electrode lines is continuously raised to the first potential. .