KR100647679B1 - Method of driving plasma display panel - Google Patents

Abstract

The present invention relates to a method of driving a plasma display panel in which there are a plurality of sub-fields for time division gray scale display for each frame as a display period, and a reset period, an address period, and a sustain discharge period exist for each sub-field. will be. The method of driving a plasma display panel according to the present invention includes a first reset period to which a voltage of a rising ramp pulse waveform in which a reset period continuously rises from a first level to a second level is applied to the Y electrode lines. In the reset period, a voltage of a rising ramp pulse waveform continuously rising from the reference level to the sixth level is applied to the address electrode lines formed along the red discharge cells, and based on the address electrode lines formed along the green discharge cells. The voltage of the falling ramp pulse waveform is continuously applied from the level to the seventh level. According to the present invention, the wall charges accumulated in the red discharge space, the green discharge space, and the blue discharge space are uniformly formed, thereby enabling uniform address discharge in each discharge space.

Description

Method of driving plasma display panel

1 is an internal perspective view showing the structure of a three-electrode surface discharge plasma display panel.

FIG. 2 is a block diagram illustrating a driving apparatus of the plasma display panel of FIG. 1.

3 is a timing diagram illustrating a method of driving the plasma display panel of FIG. 1.

4 is a timing diagram illustrating driving signals applied to electrode lines of a plasma display panel in a unit sub-field according to an exemplary embodiment of the present invention.

<Explanation of symbols for main parts of the drawings>

14R: red discharge space, 14G: green discharge space,

14B: blue discharge space, 16R: red fluorescent layer,

16G: green fluorescent layer, 16B: blue fluorescent layer,

X ₁ , ..., X _n : X electrode line, Y ₁ , ..., Y _n : Y electrode line,

A ₁ , ..., A _m : address electrode line, SF ₁ , ... SF ₈ : sub-field,

The present invention relates to a method for driving a plasma display panel, and more particularly, there are a plurality of sub-fields for time division gray scale display for each frame as a display period, and a reset period, an address period, and a sustain period for each sub-field. A driving method of a plasma display panel in which discharge cycles exist.

As flat panel display devices, plasma display panels (PDPs), which are easy to manufacture large panels, have attracted attention. A plasma display panel is a display device that displays an image by using a discharge phenomenon. In general, a plasma display panel can be classified into a direct current type and an alternating current type according to the type of driving voltage. Due to the disadvantages, the development of the AC plasma display panel has been made a lot.

An AC plasma display panel includes a three-electrode AC surface discharge type plasma display panel having three electrodes and driven by an AC voltage. A typical three-electrode surface discharge type plasma display panel is composed of a multi-layered plate, which is spatially advantageous because it can provide a thinner, lighter, and wider screen than a conventional cathode ray tube (CRT).

In order to display an image on the plasma display panel, VUV (Vacuum UltraViolet Vacuum Ultraviolet Light) is emitted from the discharge gas by a plasma formed by a voltage applied through respective electrode lines from the outside, and the fluorescent layer absorbs VUV to display visible light. Emits. In this case, a color required in a conventional plasma display panel is expressed by a combination of red, green, and blue.

To this end, the fluorescent layer is composed of a red fluorescent layer, a green fluorescent layer, and a blue fluorescent layer, and forms a red discharge space, a green discharge space, and a blue discharge space including respective fluorescent layers therein, and from each fluorescent layer The image is displayed by the combination of red, green, and blue light emitted.

However, the discharge characteristics of the panel vary depending on the type of fluorescent layer. In other words, the intensity of discharge and the timing of discharge vary depending on the type of the red fluorescent layer, the green fluorescent layer, and the blue fluorescent layer, so that the wall charges accumulated on the inner wall surface of the discharge space are not uniform. And low discharge may occur in the green discharge space.

The plasma display panel typically includes a reset period, an address period, and a sustain period. In particular, during the reset period, the discharge timing is different due to the difference in the phosphor characteristics of the red fluorescent layer, the green fluorescent layer, and the blue fluorescent layer, resulting in uneven wall charges in the red discharge space, the green discharge space, and the blue discharge space. .

Therefore, wall charges begin to accumulate quickly in the red discharge space and overdischarge occurs in subsequent address cycles. Wall charges begin to accumulate late in the green discharge space and low discharge occurs in subsequent address cycles. . In addition, there is also a problem that the sustain discharge that is next is uneven due to the nonuniformity of the address discharge.

The present invention is to solve the above problems, by adjusting the voltage bias applied to the respective address electrode lines corresponding to the red discharge space, green discharge space, blue discharge space, red discharge space, green discharge space, blue It is an object of the present invention to provide a plasma display panel driving method capable of uniformly forming wall charges accumulated in a discharge space and enabling uniform address discharge in each discharge space.

In the plasma display panel driving method according to the present invention for achieving the above object, the address electrode in the area where the address electrode lines intersect with respect to the pair of sustain electrode line in which the X electrode lines and the Y electrode lines are alternately arranged. For a plasma display panel in which red, green, and blue discharge cells are formed by red, green, and blue fluorescent layers formed along lines, there are a plurality of sub-fields for time division gray scale display per frame as a display period. A driving method of a plasma display panel in which there is a reset period, an address period, and a sustain discharge period in each sub-field, wherein the reset period is continuously raised from the first level to the second level on the Y electrode lines. Contains a first reset period to which the voltage of the ramp pulse waveform is applied. In addition, a voltage of a rising ramp pulse waveform continuously rising from a reference level to a sixth level is applied to address electrode lines formed along the red discharge cells in a first reset period, and address electrodes formed along the green discharge cells. Lines are applied with a voltage of a falling ramp pulse waveform that continuously falls from the reference level to the seventh level.

According to another aspect of the present invention, a method of driving a plasma display panel is provided along address electrode lines in an area where address electrode lines cross with respect to sustain electrode line pairs in which X electrode lines and Y electrode lines are alternately arranged. For a plasma display panel in which red, green, and blue discharge cells are formed by red, green, and blue fluorescent layers, respectively, a plurality of sub-fields for time division gray scale display exist for each frame as a display period, and each sub-field A method of driving a plasma display panel in which reset cycles, address cycles, and sustain discharge cycles are provided each time, the reset cycle being a first reset to which a voltage of a second waveform pulse waveform is applied to Y electrode lines with respect to a first level; And formed along the red discharge cells in a first reset period. The voltage of the sixth level pulse waveform is applied to the address electrode lines with respect to the reference level.

According to another aspect of the present invention, a method of driving a plasma display panel is provided along address electrode lines in an area where address electrode lines cross with respect to sustain electrode line pairs in which X electrode lines and Y electrode lines are alternately arranged. For a plasma display panel in which red, green, and blue discharge cells are formed by red, green, and blue fluorescent layers, respectively, a plurality of sub-fields for time division gray scale display exist for each frame as a display period, and each sub- A method of driving a plasma display panel in which a reset period, an address period, and a sustain discharge period are present for each field, the method comprising: applying a voltage of a pulse waveform of a second level to a first level with respect to the Y electrode lines; And a green reset cell in a first reset period. The pulse waveform of the seventh-level voltage with respect to the reference level to the address electrode lines to be formed is applied.

According to the present invention, the wall charges accumulated in the red discharge space, the green discharge space, and the blue discharge space are uniformly formed, thereby enabling uniform address discharge in each discharge space.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an internal perspective view showing the structure of a three-electrode surface discharge plasma display panel.

Referring to the drawings, between the front and rear glass substrates 10 and 13 of the surface discharge plasma display panel 1, the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm , Dielectric layers 11 and 15, Y electrode lines Y ₁ , ..., Y _n , X electrode lines X ₁ , ..., X _n , fluorescent layer 16, barrier rib 17, and The magnesium monoxide (MgO) layer 12 as a protective layer is provided.

The address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm are formed in a predetermined pattern on the front side of the rear glass substrate 13. The lower dielectric layer 15 is applied entirely in front of the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . In front of the lower dielectric layer 15, barrier ribs 17 are formed in a direction parallel to the address electrode lines A _R1 , A _G1 ,..., A _Gm , A _Bm . These partitions 17 function to partition the discharge area of each discharge cell and to prevent optical cross talk between each discharge cell. The fluorescent layer 16 is formed between the partition walls 17.

The X electrode lines (X ₁ ,..., X _n ) and the Y electrode lines (Y ₁ , ..., Y _n ) are the address electrode lines (A _R1 , A _G1 , ..., A _Gm , A _Bm ) is formed in a predetermined pattern on the back of the front glass substrate 10 to be orthogonal to each other. Each intersection sets a corresponding discharge cell. Each X electrode line (X ₁ , ..., X _n ) and each Y electrode line (Y ₁ , ..., Y _n ) have a conductivity and a transparent electrode line made of a transparent conductive material such as indium tin oxide (ITO). Metal electrode lines for heightening are formed in combination. The front dielectric layer 11 is formed by applying the entire surface to the rear of the X electrode lines X ₁ ,..., X _n and the Y electrode lines Y ₁ ,..., Y _n . A protective layer 12 for protecting the panel 1 from a strong electric field, for example, a magnesium monoxide (MgO) layer, is formed by applying the entire surface to the back of the front dielectric layer 11. The discharge gas for plasma formation is sealed in the discharge space 14.

In addition, the fluorescent layer 16 is composed of a red fluorescent layer 16R, a green fluorescent layer 16G, and a blue fluorescent layer 16B, and includes a red discharge including the respective fluorescent layers 16R, 16G, and 16B therein. The space 14R, the green discharge space 14G, and the blue discharge space 14B are formed, and an image is displayed by the combination of red, green, and blue emitted from each of the fluorescent layers 16R, 16G, and 16B.

FIG. 2 is a block diagram illustrating a driving device of the plasma display panel of FIG. 1.

Referring to the drawing, the driving device 2 of the plasma display panel 1 includes an image processor 26, a logic controller 22, an address driver 23, an X driver 24, and a Y driver 25. . The image processing unit 26 converts an external analog image signal into a digital signal, for example, an internal image signal, for example, 8-bit red (R), green (G), and blue (B) image data, a clock signal, vertical and horizontal, respectively. Generate sync signals. The logic controller 22 generates driving control signals S _A , S _Y , and S _X according to an internal image signal from the image processor 26.

In this case, the driving unit such as the address driver 23, the X driver 24, and the Y driver 25 receives input from the driving control signals S _A , S _Y , and S _X , and generates respective driving signals. The applied driving signal to each of the electrode lines.

That is, the address driver 23 processes the address signal S _A among the drive control signals S _A , S _Y , and S _X from the logic controller 22 to generate a display data signal, and generates the displayed display. The data signal is applied to the address electrode lines. The X driver 24 processes the X driving control signal S _X from the driving control signals S _A , S _Y , and S _X from the logic controller 22 and applies the X driving control signal S _X to the X electrode lines. The Y driver 25 processes the Y driving control signal S _Y among the driving control signals S _A , S _Y , and S _X from the logic controller 22 and applies the Y driving control signal S _Y to the Y electrode lines.

3 is a timing diagram illustrating a method of driving the plasma display panel of FIG. 1.

Referring to the drawing, the unit frame is divided into eight subfields SF1, ..., SF8 to realize time division gray scale display. Each of the subfields SF1, ..., SF8 includes reset periods R1, ..., R8, address periods A1, ..., A8, and sustain discharge periods S1, ..., SF8. , S8).

The luminance of the plasma display panel is proportional to the length of the sustain discharge periods S1, ..., S8 occupied in the unit frame. The lengths of sustain discharge cycles S1, ..., S8 occupy a unit frame are 255T (T is unit time). At this time, a time corresponding to 2 ⁿ is set in the sustain discharge period Sn of the nth subfield SFn. Accordingly, when appropriately selecting a subfield to be displayed among the eight subfields, it can be seen that display of 256 gray levels can be performed including all zero (zero) gray levels that are not displayed in any of the subfields.

4 is a timing diagram illustrating driving signals applied to electrode lines of a plasma display panel in a unit sub-field according to an exemplary embodiment of the present invention.

Referring to the drawings, reference numeral S _{AR1 ..ABm} denotes a drive signal applied to each address electrode line (A _R1 ,..., A _{Bm in} FIG. 1), and S _{X1 .. Xn} denotes X electrode lines (FIG. A driving signal applied to X ₁ , ..., X _{n of 1} , and S _Y1..Yn represents a driving signal applied to each Y electrode line (Y ₁ , ..., Y _n of FIG. 1). Point.

The plasma display panel driving method according to the present invention, the X electrode lines (Fig. 1 of X _1, ..., X _n) and Y electrode lines (Fig. 1 of Y _1, ..., Y _n) are alternately Red, green, and blue fluorescent layers formed along the address electrode lines in a region where the address electrode lines (A _R1 ,..., A _{Bm in} FIG. 1) intersect with the pair of sustain electrode lines arranged in FIG. For a plasma display panel in which red, green, and blue discharge cells (14R, 14G, 14B in FIG. 1) are formed by 16R, 16G, and 16B of 1, time-division gray scale display is performed for each frame FR as a display period. There are a plurality of sub-fields (SF1, ..., SF8 of FIG. 3), and there is a reset period PR, an address period PA, and a sustain discharge period PS for each sub-field. .

The reset period PR may include an erase period PR1, a first reset period PR2, and a second reset period PR3. In the erasing period PR1, a voltage applied to the X electrode lines X ₁ ,..., X _n of FIG. 1 is _first applied to a fifth level voltage V from a reference level, for example, the ground voltage V _{G. S} ) For example, it continuously rises up to 155 volts (V). Here, the ground voltage (V) is applied to the Y electrode lines (Y ₁ ,..., Y _n in FIG. 1) and the address electrode lines (A _R1 , A _G1 , ..., A _Gm , A _{Bm in} FIG. 1). _G ) is applied.

Accordingly, between the X electrode lines (X ₁ , ..., X _{n in} FIG. 1) and the Y electrode lines (Y ₁ , ..., Y _{n in} FIG. 2), and the X electrode lines (FIG. 1). A weak discharge occurs between X ₁ ,..., X _n ) and the address electrode lines (A ₁ ,..., A _{m in} FIG. 1) while the Y electrode lines (Y ₁ ,. , Y _n ) and positive wall charges are formed around the address electrode lines (A ₁ , ..., A _{m in} FIG. 1), and the X electrode lines (X ₁ , ..., X in FIG. 1). _n ) negative wall charges are formed around. Optimal for address discharge in the first reset period PR2 and the second reset period PR3 by erasing the wall charges accumulated in the sustain discharge period PS of the previous sub-field, and continuing the wall charge state in the discharge space. To form a state.

In the first level (V _S), for example a predetermined voltage from 155V than the first level (V _S) 1, the reset period (PR2) of the Y electrode lines (Fig. 1 of Y _1, ..., Y _n) in ( V _SET) as the higher the voltage of the rising ramp pulse waveform to continue to rise up to the level 2 (V _SET + V _S) for example, 355V is applied. At this time, the X electrode lines (X ₁ ,..., X _n of FIG. 1) maintain the ground voltage V _G. Accordingly, with the help of the wall charges formed in the erasing period PR1, the Y electrode lines (Y ₁ ,..., Y _n in FIG. 1) and the X electrode lines (X ₁ ,. Weak discharge occurs between X _n ).

Meanwhile, in the first reset period PR2, between the Y electrode lines Y ₁ ,..., Y _n in FIG. 1 and the address electrode lines A _R1 ..., A _{Rm in} FIG. Weak discharge occurs. Here, the Y electrode lines (FIG. 1) rather than the discharge between the Y electrode lines (Y ₁ ,..., Y _n in FIG. 1) and the address electrode lines (A _{R1 ,.} The reason why the discharge between Y ₁ ,..., Y _n ) and the X electrode lines (X ₁ ,..., X _n of FIG. 1) becomes stronger is because of the X electrode lines (X ₁ , This is because negative wall charges are formed around X _n ).

In particular, the discharges between the Y electrode lines (Y ₁ ,..., Y _n in FIG. 1) and the address electrode lines (A _R1 ,..., A _{Rm in} FIG. It is affected by the phosphor characteristics of the red, green, and blue fluorescent layers 16R, 16G, and 16B formed in the discharge cells 14R, 14G, and 14B. Typically, (Y, Gd) BO ₃ : Eu as a red phosphor, BaAl ₁₂ O ₁₉ : Mn, or Zn ₂ SiO ₄ : Mn as a green phosphor, and BaMgAl ₁₄ O ₂₃ : Eu as a blue phosphor may be used. In the red phosphor, wall charges may start to accumulate quickly and overdischarge may occur in the address period PA. In the green phosphor, wall charges may start to accumulate slowly and low discharge may occur in the address period PA.

Accordingly, as shown in FIG. 4, the Y electrode lines (Y ₁ ,..., FIG. 1) are formed in the address electrode lines (A _R1 ,..., A _Rm in FIG. 1) formed along the red discharge cells. It is preferable to apply a voltage that changes according to the voltage applied to Y _n ). That is, in the present embodiment, the voltage of the rising ramp pulse waveform continuously rising from the reference level V _G to the sixth level V _AR may be applied. Accordingly, the voltage applied to the Y electrode lines (Y ₁ ,..., Y _{n in} FIG. 1) and the address electrode lines (A _R1 ,..., A _{Rm in} FIG. 1) formed along the red discharge cells. ), The difference in voltage applied to the late reaches the starting voltage required for the discharge, and the amount of wall charges formed by the discharge may be less as the discharge starts later, and accordingly, the red phosphor characteristics in the subsequent address discharge Over discharge can be alleviated.

In particular, Y electrode lines (Fig. 1 of Y _1, ..., Y _n) is the ramp voltage and the address electrode lines are formed along the red discharge cell of a pulse waveform (in Fig. 1 in A _R1, ... , A _Rm ) may be such that the voltage of the rising ramp pulse waveform is started at the same time and has the same slope. In this case, it is preferable that the difference between the sixth level V _AR and the reference level V _G is smaller than the difference VSET between the second level and the first level.

That is, the voltage applied to the address electrode lines A _R1 ,..., A _Rm of FIG. 1 formed along the red discharge cell may adjust the size of the sixth level V _AR to adjust the Y electrode lines ( The difference between the voltage applied to Y ₁ ,..., Y _n of FIG. 1 and the voltage applied to the address electrode lines A _R1 ,..., A _{Rm of} FIG. It is possible to reach the starting voltage required for discharge. In this embodiment, the discharge start time points are formed along the green discharge cells along the address electrode lines (A _G1 ,..., A _Gm in FIG. 1) and the Y electrode lines (Y ₁ ,. , Y _n ), and the address electrode lines (A _B1 ,..., A _Bm in FIG. 1) and the Y electrode lines (Y _{1 ,.} It is preferable to adjust the size of the sixth level V _AR to be synchronized with the discharge start time of Y _n ).

At this time, the address electrode lines (A _B1 ,..., A _{Bm in} FIG. 1) formed along the blue discharge cells and the address electrode lines (A _G1,. The voltage applied to A _Gm ) may maintain the ground level.

However, as shown in FIG. 4, the Y electrode lines (Y ₁ ,..., FIG. 1) are formed in the address electrode lines (A _G1 ,..., A _Gm in FIG. 1) formed along the green discharge cells. Y _n ) may be applied to a voltage that changes in the negative polarity according to the voltage applied to Y _n ). That is, in the present embodiment, the voltage of the falling ramp pulse waveform continuously falling from the reference level V _G to the seventh level V _AG may be applied. Accordingly, the voltage applied to the Y electrode lines (Y ₁ ,..., Y _{n in} FIG. 1) and the address electrode lines (A _G1 ,..., A _{Gm in} FIG. 1) formed along the green discharge cells. The difference in the voltage applied to) reaches the starting voltage required for discharge as soon as possible, and the amount of wall charges formed by the discharge can be increased as soon as the discharge is started, and according to the green phosphor characteristics in the subsequent address discharges. The low discharge phenomenon can be alleviated.

In particular, Y electrode lines (Fig. 1 of Y _1, ..., Y _n) is the rising ramp voltage to the address electrode lines formed along the green discharge cell in the pulse waveform (FIG. 1 of A _G1, which is a. , A _Gm ) may be such that the voltage of the rising ramp pulse waveform is started at the same time and has the same magnitude and negative slope. In this case, it is preferable that the difference between the seventh level V _AG from the reference level V _G is smaller than the difference V _SET between the first level and the second level.

That is, the voltages applied to the address electrode lines (A _G1 ,..., A _{Gm in} FIG. 1) formed along the green discharge cells adjust the size of the seventh level V _AG to adjust the Y electrode lines ( The difference between the voltage applied to Y ₁ ,..., And Y _n of FIG. 1 and the voltage applied to the address electrode lines A _G1 ,..., A _{Gm of} FIG. It is possible to reach the starting voltage required for discharge. In this embodiment, the discharge start time is defined along the address electrode lines (A _R1 ,..., A _Rm in FIG. 1) and the Y electrode lines (Y ₁ ,. Y _n ) at the start of discharge and along the blue discharge cell, the address electrode lines (A _B1 ,..., A _Bm in FIG. 1) and the Y electrode lines (Y ₁ , ..., Y in FIG. 1) are formed. It is preferable to adjust the size of the seventh level V _AG to be synchronized with the discharge start time of _n ).

At this time, the address electrode lines (A _B1 ,..., A _{Bm in} FIG. 1) formed along the blue discharge cells and the address electrode lines (A _R1 , ..., FIG. 1) formed along the red discharge cells are formed. The voltage applied to A _Rm ) may maintain the ground level.

However, as shown in FIG. 4, according to the exemplary embodiment, the address electrode lines formed along the red discharge cells (A _R1 ,..., A _{Rm in} FIG. 1) and the address electrode lines formed along the green discharge cells. (Fig. 1 a _G1, a ..., a _Gm) so that the voltage applied to each of both can be changed according to the voltage applied to the Y electrode lines (Fig. 1 of Y _1, ..., Y _n) You can do it. In such a case, the address electrode lines (A _R1 ,..., A _{Rm in} FIG. 1) formed along the red discharge cells and the address electrode lines (A _G1,. , A _Gm ), and address electrode lines (A _B1 , ..., A _Bm in FIG. 1) and Y electrode lines (Y ₁ , ..., Y _{n in} FIG. 1) formed along the blue discharge cell. It will be easier to adjust the discharge start time point in between.

Here, according to the embodiment of the present invention, as in the method of adjusting the voltage applied to the address electrode lines formed along the red or green discharge cells, the address electrode lines formed along the blue discharge cells (A of FIG. 1). _B1, ..., a _Bm) to adjust the voltage applied to discharge the blue address electrode lines formed along the cell (Fig. 1 a _B1, a ..., a _Bm) and Y electrode lines is on (Fig. 1 It will of course also be possible to adjust the discharge start time between Y ₁ ,..., Y _n ).

That is, the address electrode lines (A _R1 ,..., A _Rm in FIG. 1) and the Y electrode lines (Y ₁ , FIG. 1) are formed along the red discharge cells by adjusting the sixth level V _AR . ..., Y _n ) to delay the start of discharge and adjust the seventh level (V _AG ) to address electrode lines formed along the green discharge cells (A _G1 , ..., A _{Gm in} FIG. 1). And the discharge start point between the Y electrode lines (Y ₁ ,..., Y _{n in} FIG. 1) is accelerated to adjust the discharge start points in the red, green, and blue discharge spaces 14R, 14G, and 14B. A uniform wall charge state can be obtained.

In addition, in the present embodiment, the case in which the voltage applied to the Y electrode lines (Y ₁ ,..., Y _{n in} FIG. 1) is a ramp pulse waveform has been described as an example, but various types of waveforms including square wave pulses may be applied. have.

By the first reset period PR1 as described above, many negative wall charges are formed around the Y electrode lines Y ₁ ,..., Y _n in FIG. 1, and the X electrode lines (FIG. 1). Positive wall charges are formed around X ₁ ,..., X _n ), and less positive wall charges are formed around address electrode lines (A _R1 ,..., A _{Bm in} FIG. 1).

In the second reset period PR3, the address electrode lines A _R1 ,..., A _Bm in FIG. 1 maintain the reference level V _G , and the X electrode lines (X ₁ ,. , X _n ) is biased to the voltage of the fifth level (V _S ), and the fourth level from the third level (V _S ) to the Y electrode lines (Y ₁ , ..., Y _{n in} FIG. 1). The voltage of the falling ramp pulse waveform continuously falling down to (V _G ) may be applied. At this time, it is preferable that the first level and the third level is the same level (V _S).

Accordingly, due to the weak discharge between the X electrode lines (X ₁ , ..., X _n in FIG. 1) and the Y electrode lines (Y ₁ , ..., Y _{n in} FIG. 1), the Y electrode line Some of the negative wall charges around the field (Y ₁ , ..., Y _{n in} FIG. 1) move around the X electrode lines (X ₁ , ..., X _{n in} FIG. ₁ ). Further, the address electrode lines (A _R1, ..., A _Bm) is so applied with a ground voltage (V _G), the address electrode lines are positive wall charges around the (A _R1, ..., A _Bm) Slightly increased.

Accordingly, in a subsequent addressing period PA, the display data signal is applied to the address electrode lines, and the Y electrode lines Y ₁ , which are biased to the voltage V _SCAN lower than the third level voltage V _S , are applied. As the scan signals of the ground voltage V _G are sequentially applied to the ... Y _n ), smooth addressing may be performed. The display data signal applied to each address electrode line A _R1 , ..., A _Bm is applied with the positive address voltage V _A when the discharge cell is selected and the ground voltage V _G when the discharge cell is not selected. do. Accordingly, when the display data signal of the positive address voltage V _A is applied while the scan pulse of the ground voltage V _G is applied, wall charges are formed by the address discharge in the corresponding discharge cell. Wall charges do not form. Here, for a more accurate and efficient address discharge, the fifth level voltage V _S is applied to the X electrode lines (X ₁ ,... X _n of FIG. 1).

In the sustain discharge period PS that follows, the first level is applied to all the Y electrode lines Y ₁ ,... Y _n in FIG. 1 and the X electrode lines X ₁ ,... X _{n in} FIG. a display sustain pulse of the voltage (V _s) it is alternately applied to and cause the discharge to maintain the display in discharge cells on which wall charges are formed in the corresponding address period (PA) for.

The plasma display panel, its driving apparatus, and the driving method shown in FIGS. 1 to 3 are just one embodiment to which the driving method of the plasma display panel according to the present invention can be applied, and various other plasma display panels and its driving method. Applicable to the device and the driving method.

According to the plasma display panel driving method according to the present invention, the red discharge space, the green discharge space, the blue discharge by adjusting the voltage bias applied to the respective address electrode lines corresponding to the red discharge space, the green discharge space, and the blue discharge space. By uniformly forming wall charges stored in the space, uniform address discharge in each discharge space is possible.

In addition, uniform sustain discharge is possible by uniform address discharge in each discharge space.

Although the present invention has been described with reference to one embodiment shown in the accompanying drawings, this is merely exemplary, and various modifications and equivalent other embodiments may be made by those skilled in the art. You will understand. Accordingly, the true scope of protection of the invention should be defined only by the appended claims.

Claims (15)

Red and green, respectively, by red, green, and blue fluorescent layers formed along the address electrode lines in a region where the address electrode lines intersect with respect to the pair of sustain electrode lines in which the X electrode lines and the Y electrode lines are alternately arranged. For a plasma display panel in which blue discharge cells are formed, there are a plurality of sub-fields for time division gray scale display for each frame as a display period, and a reset period, an address period, and a sustain discharge period are provided for each sub-field. In the present method of driving a plasma display panel, The reset period includes a first reset period to which a voltage of a rising ramp pulse waveform is continuously applied to the Y electrode lines from a first level to a second level, In the first reset period, a voltage of a rising ramp pulse waveform continuously rising from a reference level to a sixth level is applied to the address electrode lines formed along the red discharge cells, and the addresses formed along the green discharge cells. And a voltage of a falling ramp pulse waveform continuously falling from the reference level to the seventh level is applied to the electrode lines. The method of claim 1, In the first reset period, The voltage of the rising ramp pulse waveform applied to the Y electrode lines and the voltage of the rising ramp pulse waveform applied to the address electrode lines formed along the red discharge cell start at the same time point, and have the same slope, The voltage of the rising ramp pulse waveform applied to the Y electrode lines and the voltage of the falling ramp pulse waveform applied to the address electrode lines formed along the green discharge cells start at the same time, and have the same magnitude and negative slope. A method of driving a plasma display panel. The method of claim 1, Driving of the plasma display panel in which the difference between the sixth level and the reference level is smaller than the difference between the first level and the first level, and the difference between the seventh level and the reference level is smaller than the difference between the first level and the first level; Way. The method of claim 1, And a reference level voltage is applied to the X electrode lines in the first reset period. The method of claim 1, The reset period causes the address electrode lines to maintain a reference level, the X electrode lines are biased to a voltage of a fifth level, and the Y electrode lines are continuously lowered from the third level to a fourth level. And a second reset cycle to which the voltage of the falling ramp pulse waveform is applied. The method of claim 5, And the first level and the third level are the same level. The method of claim 1, And a voltage of the reference level is a ground level. Red and green, respectively, by red, green, and blue fluorescent layers formed along the address electrode lines in a region where the address electrode lines intersect with respect to the pair of sustain electrode lines in which the X electrode lines and the Y electrode lines are alternately arranged. For a plasma display panel in which blue discharge cells are formed, there are a plurality of sub-fields for time division gray scale display for each frame as a display period, and a reset period, an address period, and a sustain discharge period are provided for each sub-field. In the present method of driving a plasma display panel, The reset period includes a first reset period to which a voltage of a rising ramp pulse waveform is continuously applied to the Y electrode lines from a first level to a second level, In the first reset period, a voltage of a rising ramp pulse waveform continuously rising from a reference level to a sixth level is applied to address electrode lines formed along the red discharge cells, In the first reset period, the voltage of the rising ramp pulse waveform applied to the Y electrode lines and the rising ramp pulse waveform applied to the address electrode lines formed along the red discharge cell start at the same time point. A method of driving a plasma display panel having the same slope. delete delete The method of claim 8, And a difference of the reference level from the sixth level is smaller than the difference of the first level from the second level. Red and green, respectively, by red, green, and blue fluorescent layers formed along the address electrode lines in a region where the address electrode lines intersect with respect to the pair of sustain electrode lines in which the X electrode lines and the Y electrode lines are alternately arranged. For a plasma display panel in which blue discharge cells are formed, there are a plurality of sub-fields for time division gray scale display for each frame as a display period, and a reset period, an address period, and a sustain discharge period are provided for each sub-field. In the present method of driving a plasma display panel, The reset period includes a first reset period to which a voltage of a rising ramp pulse waveform is continuously applied to the Y electrode lines from a first level to a second level, And a voltage of a falling ramp pulse waveform continuously falling from a reference level to a seventh level is applied to the address electrode lines formed along the green discharge cells during the first reset period. delete The method of claim 12, In the first reset period, The voltage of the rising ramp pulse waveform applied to the Y electrode lines and the voltage of the falling ramp pulse waveform applied to the address electrode lines formed along the green discharge cells start at the same time, and have the same magnitude and negative slope. A method of driving a plasma display panel. The method of claim 12, And the difference of the seventh level from the reference level is smaller than the difference of the first level from the second level.

Images