JP3612404B2 - Driving method of plasma display panel - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a driving method for a matrix display alternating current (AC) plasma display panel (PDP).
[0002]
[Prior art]
In recent years, with the increase in size of display devices, thin display devices are required, and various thin display devices are provided. One of them is ACPDP.
The ACDP includes a column electrode and a row electrode that is orthogonal to the column electrode and constitutes one row (one scan line) as a pair. Each of the column electrode and the row electrode pair is a dielectric layer with respect to the discharge space. A discharge cell (pixel) is formed at each intersection of the column electrode and the row electrode pair. The row electrode is composed of a transparent electrode and a bus electrode laminated thereon.
[0003]
FIG. 7 is a diagram showing application timings of various conventional drive pulses of the ACDP.
In FIG. 7, first, a negative reset pulse RP _x is applied to all the row electrodes X _{1 to} X _n , and simultaneously, a positive reset pulse RP _y is applied to each of all the row electrodes Y _{1 to} Y _n. . By applying such a reset pulse, discharge occurs in all the discharge cells, charged particles are generated, and wall charges are accumulated and formed in each discharge cell after completion of the discharge (simultaneous reset period).
[0004]
Next, pixel data pulses DP _{1 to} DP _n corresponding to the pixel data for each row are sequentially applied to the column electrodes D _{1 to} D _m . A scan pulse (selective erase pulse) SP is sequentially applied to the row electrodes Y ₁ to Y _n in synchronization with the application timings of the pixel data pulses DP _{1 to} DP _n .
[0005]
At this time, the wall charges formed during the simultaneous reset period are generated only in discharge cells (light-out pixels, light-off cells) in which the pixel data pulse DP and the scan pulse SP are simultaneously applied to the column electrode and the row electrode, respectively. Is erased. On the other hand, in the discharge cells (lighted pixels, lighted cells) to which the scan pulse SP is applied but the pixel data pulse DP is not applied, the discharge as described above does not occur, so that the wall charges formed in the simultaneous reset period remain as they are. . Thus, the wall charge of each discharge cell is selectively erased according to the pixel data, and the lit pixel and the unlit pixel are selected (address period).
[0006]
Next, the positive polarity sustaining pulse IP _x is applied to each of the row electrodes X _{1 to} X _{n and} the positive polarity sustaining pulse IP _y is applied to the row electrodes at a timing different from the application timing of the sustaining pulse IP _x. It is applied to each of the Y ₁ to Y _n. In this way, discharge sustain pulses IP _x and IP _y are alternately applied to the pair of row electrodes, and discharge cells in which wall charges remain (lighted pixels, lighted cells) repeat discharge light emission, while discharge cells in which wall charges have disappeared (Light-off pixels, light-off cells) do not emit light during discharge (sustain discharge period).
[0007]
Next, the erasing pulse EP is applied to all the row electrodes Y _{1 to} Y _n simultaneously to erase the wall charges of all the discharge cells (lighted cells) (wall charge erasing period).
As described above, image display is performed by repeating the simultaneous reset period, address period, sustain discharge period, and wall charge erasing period as one display cycle.
As one method of displaying such PDPs in grayscale, N subframes (subfields) that emit light for a time corresponding to the weighting of each bit digit of display data of N bits in one frame (one field) display period. There is a method (so-called subframe method) in which the image is divided and displayed.
[0008]
[Problems to be solved by the invention]
By the way, in the above PDP driving method, after the sustain discharge period, one erase pulse (a narrow erase pulse or a wide erase pulse) is applied simultaneously to the row electrode pair to erase the wall charge of the lit cell. Was.
[0009]
However, as shown in FIG. 8A, since the wall charges to be erased are distributed over the entire row electrode, even if one erase pulse is applied simultaneously to the row electrode pairs, FIG. As shown in FIG. 3, it is difficult to reliably erase the wall charges of the lighting cell.
[0010]
That is, when the row electrode length (depth) L is long, the wall charges on the side opposite to the discharge gap (the bus electrode side) cannot be erased, resulting in residual wall charges. It is desirable to erase the wall charge on the column electrode. However, when a wide erase pulse is used, a negative charge is formed on the column electrode by the erase discharge, and if the column electrode has a long electrode length, As in the case of the electrodes, residual wall charges are generated on the opposite side (outside) of the discharge gap of the column electrodes.
[0011]
These residual wall charges cause unnecessary discharge (erroneous discharge) in the address period in the next display period (subframe), and cause a decrease in address margin. Further, this unnecessary discharge becomes an obstacle to lowering the contrast or miniaturizing the cell.
[0012]
Furthermore, it has been difficult to erase wall charges uniformly in the panel due to variations in characteristics among discharge cells and voltage drop in the panel. Therefore, the discharge in the next display period (subframe) varies from cell to cell and deteriorates the address margin.
[0013]
The present invention has been made to solve the above-described problems, and an object thereof is to reliably and uniformly erase wall charges in the wall charge erasing period to prevent erroneous discharge and to improve display characteristics. .
[0014]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a plasma display panel driving method comprising: a plurality of row electrode pairs coated with a dielectric layer; and a plurality of row electrode pairs that are arranged to intersect the row electrode pairs and that form pixels at each intersection. An address period in which a scanning pulse is applied to one row electrode of a pair of row electrodes and a pixel data pulse is applied to the column electrode to select a lit pixel and a non-lit pixel according to pixel data; A sustain discharge period in which the discharge sustain pulse is alternately applied to the row electrodes constituting the row electrode pair to maintain the lit pixel and the unlit pixel, and a wall charge in which the wall charge erase pulse is applied to the row electrode pair to erase the wall charge a driving method of a plasma display panel which performs display by using the erase period, wall charges erase pulse, the wall charge erasing pulse having a voltage value lower than the sustaining pulse having the same polarity as the smallest and discharge sustain voltage When, characterized in that it comprises a single wall charge erase pulse having a minimum discharge sustain voltage or voltage value that follows the wall charge erasing pulse train.
[0015]
According to a third aspect of the present invention, there is provided a plasma display panel driving method comprising: a plurality of row electrode pairs covered with a dielectric layer; and a plurality of row electrode pairs that are arranged to intersect the row electrode pairs to form pixels at each intersection. An address period in which a scanning pulse is applied to one row electrode of a pair of row electrodes and a pixel data pulse is applied to the column electrode to select a lit pixel and a non-lit pixel according to pixel data; A sustain discharge period in which the discharge sustain pulse is alternately applied to the row electrodes constituting the row electrode pair to maintain the lit pixel and the unlit pixel, and a wall charge in which the wall charge erase pulse is applied to the row electrode pair to erase the wall charge A plasma display panel driving method for performing display using an erasing period, wherein the wall charge erasing pulse has the same polarity as the discharge sustaining pulse and the voltage value gradually decreases to a voltage value less than the minimum sustaining voltage. Na A wall charge erasing pulse train, characterized in that it comprises a single wall charge erase pulse having a minimum discharge sustain voltage or voltage value that follows the wall charge erasing pulse train.
[0022]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a diagram showing a structure of a reflective ACPDP having a three-electrode structure driven by a plasma display panel driving method according to an embodiment of the present invention.
[0023]
As shown in FIG. 1, a pair of row electrodes (sustain electrodes) arranged adjacent to each other in parallel to the inner surface of the glass substrate 1 on the display surface side of the pair of glass substrates 1 and 2 that are arranged to face each other via the discharge space 7. A wall charge forming dielectric layer 5 covering X and Y, row electrodes X and Y, and a protective layer 6 made of MgO covering the dielectric layer 5 are provided.
[0024]
The row electrodes X and Y are respectively a transparent electrode 4 made of a wide strip-like transparent conductive film and a bus electrode (metal electrode) 3 made of a narrow strip-like metal film laminated to supplement the conductivity. It consists of and.
[0025]
On the other hand, on the inner surface of the glass substrate 2 on the back side, the row electrodes X and Y are provided on the glass substrate 2 between the barriers 10 and the barriers 10 that are provided in the direction intersecting the row electrodes X and Y and partition the discharge space 7. A column electrode (address electrode) D arranged in the intersecting direction, and a phosphor layer 8 of a predetermined emission color that covers each column electrode and the side surface of the barrier 10 are provided. The discharge space 7 is filled with a discharge gas in which a small amount of xenon is mixed with neon. A discharge cell (pixel) is formed at each intersection of the column electrode and the row electrode pair.
[0026]
Next, a method of driving the plasma display panel according to the present invention performed using the PDP of FIG. 1 will be described.
FIG. 2 is a diagram showing application timings of various driving pulses applied to the PDP 11 when performing panel driving in the first embodiment of the driving method of the present invention.
[0027]
In FIG. 2, first, a reset voltage RP _x having a long rise time (long time constant) pulse positive voltage is applied to all the row electrodes X _{1 to} X _n from a row electrode drive pulse generation circuit (not shown), and simultaneously, a positive voltage Similarly to the case of, a negative voltage reset pulse RP _y is applied to each of the row electrodes Y _{1 to} Y _n . When the potential difference generated between the positive potential and the negative potential applied between each row electrode pair exceeds the discharge start voltage, the discharge is excited between all the row electrode pairs of the PDP 11, and within the discharge space of all the pixel cells. Charged particles are generated. After the discharge is terminated by applying the reset pulses RP _x and RP _y , a predetermined amount of wall charges are uniformly formed in the dielectric layers of all the pixel cells (simultaneous reset period).
[0028]
Next, pixel data pulses DP _{1 to} DP _n having positive voltages corresponding to the pixel data for each row are sequentially applied to the column electrodes D _{1 to} D _m from a pixel data pulse generation circuit (not shown).
At this time, a scan pulse SP having a small pulse width is sequentially applied to the row electrodes Y ₁ to Y _n in synchronization with the application timings of the pixel data pulses DP _{1 to} DP _n . Here, immediately before the scanning pulse SP is applied to each of the row electrodes Y _{1 to} Y _n, a positive voltage priming pulse PP as shown in FIG. 2 is applied to each of the row electrodes Y _{1 to} Y _n . By applying the priming pulse PP, priming particles obtained by the simultaneous reset and reduced with the passage of time are re-formed in the discharge space. Therefore, pixel data writing by applying the scan pulse SP is tried while a desired amount of priming particles are present in the discharge space.
[0029]
For example, when the content of the pixel data is logic “0”, since the pixel data pulse DP is simultaneously applied together with the scanning pulse SP, the wall charges formed inside the pixel cell disappear.
On the other hand, when the content of the pixel data is theoretical “1”, only the scanning pulse SP is applied, so that no discharge occurs and the wall charges formed inside the pixel cell are held as they are. That is, the scan pulse SP can be said to be a selective erasing pulse that serves as a trigger for selectively erasing wall charges formed in the pixel cell in accordance with pixel data (pixel data writing period).
[0030]
Next, a positive voltage sustaining pulse IP _x is applied to each of the row electrodes X _{1 to} X _n . Next, the discharge sustain pulse IP _y having a positive voltage is applied to each of the row electrodes Y _{1 to} Y _n at a timing shifted from the application timing of the discharge sustain pulse IP _x . Only the pixel cells in which the wall charges remain are maintained during the period in which such discharge sustaining pulses are alternately applied to the row electrodes X and Y alternately (sustain discharge period). .
In this sustain discharge process, the pulse width is set longer than the discharge sustain pulses IP _y , IP _x ... Applied first to the row electrodes, that is, first.
The reason for this will be described below.
[0031]
When discharge occurs, priming particles are generated in the discharge space, but decrease with time. As the number of priming particles decreases, the time from the application of a pulse until the first discharge occurs (discharge formation delay time) and the variation in the discharge start time of each pixel cell (discharge statistical delay time) increase. Then, the discharge is not generated by the discharge sustain pulse applied at the beginning of the sustain discharge period, and there is a high possibility that no discharge is generated by the discharge sustain pulse applied thereafter. Therefore, by making the pulse width of the discharge sustain pulse applied first longer than the discharge sustain pulse applied thereafter, that is, longer than the sum of the discharge formation delay time, the discharge statistical delay time and the time required for the discharge itself. Thus, it is possible to reliably generate a discharge with the discharge sustain pulse applied first.
[0032]
Next, a plurality of wall charge erasing pulses (wall charge erasing pulse trains) having a voltage value lower than the voltage value of the sustaining pulse, that is, a voltage value lower than the minimum sustaining voltage Vsm, are applied to the row electrodes X _{1 to} X _n. , Y _{1 to} Y _n , the wall charges formed on the row electrodes X _{1 to} X _n and Y _{1 to} Y _n are extinguished, and the state of the wall charges in the lit and extinguished pixel cells is eliminated. Make substantially uniform (wall charge erasing period).
[0033]
As described above, in such a plasma display panel driving method, a reset pulse having a slowly rising waveform is applied simultaneously to all the row electrodes to execute a simultaneous reset, and the first step is performed in the sustain discharge process. By setting the pulse width of the sustaining pulse applied to the electrodes to be long, the panel is made to emit light.
[0034]
As described above, in the present invention, in the wall charge erasing period, a plurality of wall charge erasing pulses (wall charge erasing pulse train) having a voltage value lower than the voltage value of the discharge sustaining pulse, that is, a voltage value lower than the minimum discharge sustaining voltage Vsm, are obtained. It is characterized by being applied alternately to the row electrode pairs X and Y.
[0035]
Here, the minimum discharge sustain voltage Vsm is a minimum voltage for maintaining the discharge. When the pulse has a voltage value less than this value, the discharge continues for a while even if the pulse is continuously applied, but gradually weakens. Eventually, the discharge stops.
[0036]
As described above, in the wall charge erasing period, a plurality of wall charge erasing pulses (wall charge erasing pulse train) having a voltage value lower than the voltage value of the discharge sustaining pulse as the wall charge erasing pulse, that is, a voltage value lower than the minimum discharge sustaining voltage Vsm. Is used, the wall charges distributed over the entire row electrode decrease in density each time it is discharged, and the distribution is also biased to the vicinity of the discharge gap.
[0037]
The wall charges on the column electrode side are also reduced in density in the same manner as on the row electrode side, and the distribution is also biased toward the region facing the discharge gap between the row electrodes. As a result, as shown in FIG. 3, when the discharge stops in the middle of applying the wall charge erasing pulse train, the wall charges on the row and column electrodes are only slightly left in the vicinity of the discharge gap. . Therefore, since there is no extra wall charge when moving to the next subframe, no erroneous discharge occurs, and the address margin and contrast do not deteriorate.
[0038]
In the wall charge erasing period, a plurality of wall charge erasing pulses (wall charge erasing pulse train) having a voltage value lower than the voltage value of the discharge sustaining pulse, that is, a voltage value lower than the minimum discharge sustaining voltage Vsm, is used as the wall charge erasing pulse. As a result, wall charges are erased (decreased) automatically (spontaneously) according to the discharge characteristics of individual discharge cells, enabling stable erase operations even if the discharge characteristics vary from discharge cell to discharge cell. become.
[0039]
Further, since the wall charges are automatically reduced until the discharge cannot be maintained, the residual wall charges can be reduced very much. Furthermore, in the address period, unnecessary discharge (interference of discharge cells) between adjacent row electrode pairs (between bus electrodes), that is, between scan lines can be prevented, and high definition can be achieved by reducing the size of the cells and the scan line pitch. Is possible.
[0040]
FIG. 4 is a diagram showing application timings of various drive pulses applied to the PDP when panel driving is performed in the second embodiment of the driving method of the present invention.
[0041]
A difference from the driving method of FIG. 2 is that a plurality of wall charge erasing pulses having a voltage value lower than the voltage value of the discharge sustaining pulse as the wall charge erasing pulse, that is, a voltage value lower than the minimum discharge sustaining voltage Vsm, in the wall charge erasing period. When (wall charge erasing pulse train) is used, the voltage value of the wall charge erasing pulse train is gradually decreased to a voltage value lower than the minimum discharge sustaining voltage.
Also in this case, the same operation and effect as the first embodiment are obtained.
[0042]
FIG. 5 is a diagram showing application timings of various drive pulses applied to the PDP when panel driving is performed in the third embodiment of the driving method of the present invention.
[0043]
A difference from the driving method of FIG. 2 is that the wall charge erasing period has a voltage value lower than the voltage value of the discharge sustaining pulse as the wall charge erasing pulse, that is, a voltage value lower than the minimum discharge sustaining voltage Vsm. After the application of a plurality of wall charge erasing pulses having the same polarity (wall charge erasing pulse train), one wall charge erasing pulse having a voltage value equal to or higher than the minimum discharge sustaining voltage is applied to the row electrode pair. Is a point.
Also in this case, the same operation and effect as the first embodiment are obtained.
[0044]
FIG. 6 is a diagram showing application timings of various drive pulses applied to the PDP when panel driving is performed in the fourth embodiment of the driving method of the present invention.
[0045]
The driving method of FIG. 4 is different from the driving method of FIG. 4 in the wall charge erasing period in that the voltage value is gradually decreased to maintain the minimum discharge in the row electrode pair after the application of the wall charge erasing pulse train having a voltage value lower than the minimum discharge sustaining voltage. One wall charge erase pulse having a voltage value equal to or higher than the voltage is applied to the row electrode pair.
Also in this case, the same operation and effect as the first embodiment are obtained. In the third and fourth embodiments, after the end of the wall charge erasing pulse train, one narrow wall charge erasing pulse having the opposite polarity to the discharge sustaining pulse is applied to one of the row electrode pairs (Y electrode) all at once. However, the present invention is not limited to this, and one wall charge erasing pulse having the same polarity as the discharge sustaining pulse may be applied simultaneously to the other (X electrode) of the pair of row electrodes. The one wall charge erasing pulse has a voltage value equal to or higher than the minimum discharge sustaining voltage.
[Brief description of the drawings]
FIG. 1 is a diagram showing a structure of a reflective ACPDP having a three-electrode structure driven by a driving device for a plasma display panel according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating application timings of various driving pulses applied to a PDP when performing panel driving in an embodiment of a driving method according to the present invention.
FIG. 3 is a diagram illustrating an erased state of wall charges in a PDP according to the present invention.
FIG. 4 is a diagram showing application timings of various drive pulses applied to a PDP in a second embodiment of a drive method according to the present invention.
FIG. 5 is a diagram showing application timings of various drive pulses applied to a PDP in a third embodiment of a drive method according to the present invention.
FIG. 6 is a diagram showing application timings of various drive pulses applied to a PDP in a fourth embodiment of a drive method according to the present invention.
FIG. 7 is a diagram illustrating application timings of various drive pulses of a conventional PDP.
FIG. 8 is a diagram showing an erased state of wall charges in a conventional PDP.
[Explanation of symbols]
1, 2 ... Glass substrate 3 ... Bus electrode (metal electrode)
4 ... Transparent electrode 5 ... Dielectric layer 6 ... Protective layer 7 ... Discharge space 8 ... Phosphor layer 10 ... Barrier 11・ ・ ・ ・ ・ PDP
X, Y ...... Row electrode (sustain electrode)
D ... Column electrode (address electrode)

Claims (4)

A plurality of row electrode pairs covered with a dielectric layer, and a plurality of column electrodes arranged to intersect the row electrode pairs and form pixels at each intersection , and one row of the row electrode pairs an address period for selecting a lighting pixel and off pixels in accordance with pixel data pulses to apply to the pixel data to the column electrodes applied with a scan pulse to the electrodes, the discharge sustaining alternately to the row electrodes constituting the row electrode pair A plasma display that performs display using a sustain discharge period in which a pulse is applied to maintain the lit pixel and the unlit pixel, and a wall charge erase period in which a wall charge erase pulse is applied to the row electrode pair to erase a wall charge A panel driving method,
The wall charge erasure pulse has a wall charge erasure pulse train having the same polarity as the discharge sustain pulse and less than a minimum discharge sustain voltage, and a voltage value equal to or higher than the minimum discharge sustain voltage following the wall charge erasure pulse train. A method for driving a plasma display panel, comprising: one wall charge erasing pulse . Said row electrode pair is composed of a transparent electrode disposed on the inner surface of the substrate on the display surface side, a metal electrode laminated on the transparent electrode, before Symbol column electrodes, a discharge space and a substrate of the display surface side 2. The method of driving a plasma display panel according to claim 1, wherein the plasma display panel is disposed on an inner surface of a substrate on the back side opposed to each other through a substrate and covered with a phosphor layer. A plurality of row electrode pairs covered with a dielectric layer; and a plurality of column electrodes arranged crossing the row electrode pairs and forming pixels at each intersection, and one row of the row electrode pairs An address period in which a scanning pulse is applied to the electrode and a pixel data pulse is applied to the column electrode to select a lit pixel and a non-lit pixel according to the pixel data, and a discharge is alternately maintained in the row electrode constituting the row electrode pair A plasma display that performs display using a sustain discharge period in which a pulse is applied to maintain the lit pixel and the unlit pixel, and a wall charge erase period in which a wall charge erase pulse is applied to the row electrode pair to erase the wall charge A panel driving method,
  The wall charge erasure pulse has the same polarity as the discharge sustain pulse and the voltage value gradually decreases to a voltage value lower than the minimum discharge sustain voltage, and the minimum discharge following the wall charge erase pulse train And a wall charge erasing pulse having a voltage value equal to or higher than the sustain voltage. The row electrode pair includes a transparent electrode disposed on the inner surface of the substrate on the display surface side and a metal electrode laminated on the transparent electrode, and the column electrode has a discharge space between the substrate on the display surface side and the discharge space. 4. The method of driving a plasma display panel according to claim 3, wherein the plasma display panel is disposed on the inner surface of the substrate on the back side opposed to each other and covered with a phosphor layer.

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