JP4496703B2 - Driving method of plasma display panel - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a plasma display panel (hereinafter referred to as PDP) known as a thin, lightweight image display device with a large screen.
[0002]
[Prior art]
The PDP is a display that displays an image by exciting and emitting phosphors with ultraviolet rays generated by gas discharge. The discharge can be classified into an alternating current (AC) type and a direct current (DC) type.
[0003]
The characteristics of the AC type are superior to the DC type in terms of luminance, luminous efficiency, and lifetime, and the reflective surface discharge type is particularly prominent in terms of luminance and luminous efficiency. It is becoming.
[0004]
FIG. These are top views which show schematic structure of the conventional PDP. Also, FIG. FIG. 5 is a cross-sectional perspective view showing a schematic structure of a part of an image display area of a conventional PDP.
[0005]
The front substrate 2 of the PDP 1 is a display electrode 6 composed of N scanning electrodes 4 and N sustain electrodes 5 formed on one main surface of the front glass substrate 3 (when the Nth electrode is shown, the number is attached). And a dielectric layer 7 that covers the display electrode 6 and a protective layer 8 made of, for example, MgO that covers the dielectric layer 7. Scan electrode 4 and sustain electrode 5 have a structure in which bus electrodes 4b and 5b made of a metal material are laminated on transparent electrodes 4a and 5a for the purpose of reducing electrical resistance.
[0006]
The back substrate 9 includes M data electrodes 11 formed on one main surface of the back glass substrate 10 (the numbers are given when the M-th is shown), a dielectric layer 12 covering the data electrodes 11, a dielectric In this structure, the barrier ribs 13 are located between the data electrodes 11 on the body layer 12, and the phosphor layers 14 R, 14 G, and 14 B between the barrier ribs 13.
[0007]
The front substrate 2 and the rear substrate 9 are opposed to each other so that the display electrode 6 and the data electrode 11 are orthogonal to each other with the partition wall 13 interposed therebetween, and the periphery outside the image display region 15 is sealed by the sealing member 16. The discharge space 17 formed between the front substrate 2 and the back substrate 9 is filled with, for example, a Ne-Xe 5% discharge gas at a pressure of 66.5 kPa (500 Torr).
[0008]
The intersection between the display electrode 6 and the data electrode 11 in the discharge space 17 operates as a discharge cell 18 (unit light emitting region).
[0009]
FIG. The block diagram of schematic structure of the plasma image display apparatus using the above-mentioned PDP1 is shown. The plasma image display device 30 has a configuration in which a PDP driving device 31 is connected to the PDP 1.
[0010]
The PDP driving device 31 includes a controller 32, a sustain driver circuit 33, a scan driver circuit 34, and a data driver circuit 35. When the plasma image display device 30 is driven, the PDP 1 includes a sustain driver circuit 33, a scan driver circuit 34, and a data driver circuit. 35 is connected and the discharge cell 18 ( FIG. ), An address discharge is performed by applying a voltage between the scan electrode 4 and the data electrode 11, and then a sustain discharge is performed by applying a voltage between the scan electrode 4 and the sustain electrode 5. Due to this sustain discharge, ultraviolet rays are generated in the discharge cells 18, and the phosphor layers 14 R, 14 G, and 14 B excited by the ultraviolet rays are lit to emit light, and depending on the combination of lighting and non-lighting of the discharge cells 18 of each color. An image is displayed.
[0011]
FIG. Shows the waveform of the drive voltage when driving the PDP 1.
[0012]
In the PDP 1, a plurality of (one field period includes an initialization period, a writing period, a sustain period, and a wall charge adjustment period ( FIG. The number of sustain pulses for determining the number of sustain discharges is different for each subfield, and gradation expression is performed by combining the subfields.
[0013]
An example of this driving operation will be described. First, an initialization pulse of Va (V) is applied to the scan electrodes 4 SCN (1) to SCN (N) in the initialization period, so that the inside of the discharge cells of the panel. Initialize wall charge. In the subsequent writing period, in order to perform display in the first row, a scan pulse voltage of Vb (V) is applied to the scan electrode SCN (1) in the first row, and D (the data electrode 11 corresponding to the discharge cell 18). 1) to D (M) by applying a write pulse voltage of Vdat (V), write discharge (address discharge) between D (1) to D (M) and SCN (1) in the first row Is generated, wall charges are accumulated, and the write operation (address operation) in the first row is performed.
[0014]
The above operations are sequentially performed, and a latent image for one screen is written when the writing operation for the Nth row is completed.
[0015]
Next, in the sustain period, D (1) to D (M) are grounded. First, a sustain pulse voltage of Vs (V) is applied to all of SUS (1) to SUS (N) which are sustain electrodes 5, and then By applying a sustain pulse voltage of Vs (V) to all SCN (1) to SCN (N) and continuing this operation alternately, the sustain discharge is performed in the discharge cell 18 in which the write operation is performed in the write period. Is continuously emitted and the screen is displayed. Thereafter, Vs1 (V), which is a voltage for adjusting wall charges, is first applied to all of SCN (1) to SCN (N) in the wall charge adjustment period, and then, in a time shorter than the pulse width of the sustain pulse voltage. Switch to Vd (V). By switching the applied voltage during this wall charge adjustment period, FIG. A narrow wall charge adjustment pulse as indicated by Z in the middle is formed, and a weak discharge is generated compared to the sustain discharge. The wall charge is adjusted to an appropriate amount by this weak discharge.
[0016]
In this manner, image display is performed by a series of driving methods including an initialization period, a writing period, a sustain period, and a wall charge adjustment period (see, for example, Non-Patent Document 1).
[0017]
[Non-Patent Document 1]
Heki Uchiike and Shigeo Miko “All about Plasma Displays”, Industrial Research Council, Inc., May 1, 1997, for example, p122-p123, p126-p127
[0018]
[Problems to be solved by the invention]
In the conventional PDP described above, if the wall charge adjustment pulse in the wall charge adjustment period is too small and the discharge is too weak, the wall charge cannot be adjusted to an appropriate amount, and a write failure occurs in the subsequent write period. It was the cause of non-lighting. Further, if the wall charge adjustment pulse is too large and the discharge is too strong, the discharge spreads to the adjacent discharge cells 18, which causes a false discharge between the discharge cells 18 called crosstalk. In addition, a method of controlling the scale of the discharge by an externally applied voltage is also conceivable.To that end, it is necessary to align the shape variation of the discharge cells 18 and suppress the variation of the discharge start voltage within a predetermined range. This is very difficult considering the actual manufacturing process.
[0019]
The present invention has been made in view of the above problems, and an object of the present invention is to realize a PDP driving method capable of suppressing erroneous discharge and non-lighting, which may be caused by poor wall charge adjustment.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, a method for driving a plasma display panel of the present invention includes: After the sustain period, a wall charge adjustment period for applying a wall charge adjustment pulse to the scan electrode is provided, and the wall charge adjustment period has a narrow wall charge at the same voltage as the sustain pulse voltage at the scan electrode. After applying the adjustment pulse voltage, the scan electrode is put into a high impedance state, and then a voltage lower than the wall charge adjustment pulse voltage is applied to the scan electrode, and then a voltage that gradually decreases is applied. Characterized by It is.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
That is, according to the first aspect of the present invention, a front substrate on which a display electrode composed of a scan electrode and a sustain electrode is formed, and a rear substrate on which a data electrode is formed so as to be orthogonal to the display electrode, A plasma display panel having a plurality of discharge cells arranged to face each other so as to form a discharge space, and when driving the plasma display panel, one field is constituted by a plurality of subfields, and the subfield In addition, in the write period in which the scan pulse voltage is applied to the scan electrode and the write pulse voltage is applied to the data electrode to generate the write discharge, and in the discharge cell in which the write operation is performed in the write period, the scan electrode And a sustain period for generating a sustain discharge by alternately applying a sustain pulse voltage to the sustain electrodes. A method of driving a plasma display panel, After the sustain period, a wall charge adjustment period for applying a wall charge adjustment pulse to the scan electrode is provided, and the wall charge adjustment period has a narrow wall charge at the same voltage as the sustain pulse voltage at the scan electrode. After applying the adjustment pulse voltage, the scan electrode is put into a high impedance state, and then a voltage lower than the wall charge adjustment pulse voltage is applied to the scan electrode, and then a voltage that gradually decreases is applied. Characterized by .
[0022]
Hereinafter, a PDP driving method according to an embodiment of the present invention will be described with reference to FIGS. FIG. Will be described. Used in the description of the conventional PDP 10 to 13 The same number is attached | subjected to the same thing as what is shown in.
[0023]
(Embodiment 1)
FIG. 1 is a plan view showing a schematic structure of a PDP that is driven by a PDP driving method according to an embodiment of the present invention. FIG. 2 is also a cross-sectional perspective view showing a schematic structure of a part of an image display area of the PDP that is driven by the PDP driving method according to the embodiment of the present invention.
[0024]
The front substrate 2 of the PDP 1 is a display electrode 6 composed of N scanning electrodes 4 and N sustain electrodes 5 formed on one main surface of the front glass substrate 3 (when the Nth electrode is shown, the number is attached). And a dielectric layer 7 that covers the display electrode 6 and a protective layer 8 made of, for example, MgO that covers the dielectric layer 7. Scan electrode 4 and sustain electrode 5 have a structure in which bus electrodes 4b and 5b made of a metal material are laminated on transparent electrodes 4a and 5a for the purpose of reducing electrical resistance.
[0025]
The back substrate 9 includes M data electrodes 11 formed on one main surface of the back glass substrate 10 (the numbers are given when the M-th is shown), a dielectric layer 12 covering the data electrodes 11, a dielectric In this structure, the barrier ribs 13 are located between the data electrodes 11 on the body layer 12, and the phosphor layers 14 R, 14 G, and 14 B between the barrier ribs 13.
[0026]
The front substrate 2 and the rear substrate 9 are opposed to each other so that the display electrode 6 and the data electrode 11 are orthogonal to each other with the partition wall 13 interposed therebetween, and the periphery outside the image display region 15 (FIG. 1) is a sealing member. 16 (FIG. 1). In the discharge space 17 formed between the front substrate 2 and the rear substrate 9, for example, a discharge gas of 5% Ne—Xe has a pressure of 66.5 kPa (500 Torr). It is enclosed with.
[0027]
The intersection between the display electrode 6 and the data electrode 11 in the discharge space 17 operates as a discharge cell 18 (unit light emitting region).
[0028]
FIG. 3 shows a block diagram of a schematic configuration of a plasma image display device using the above-described PDP 1. The plasma image display device 30 has a configuration in which a PDP driving device 31 is connected to the PDP 1.
[0029]
The PDP driving device 31 includes a controller 32, a sustain driver circuit 33, a scan driver circuit 34, and a data driver circuit 35. When the plasma image display device 30 is driven, the PDP 1 includes a sustain driver circuit 33, a scan driver circuit 34, and a data driver circuit. 35, and after performing address discharge by applying a voltage between the scan electrode 4 and the data electrode 11 in the discharge cell 18 (FIG. 2) to be lit according to the control of the controller 32, the scan electrode 4 The sustain discharge is performed by applying a voltage between the sustain electrode 5 and the sustain electrode 5. Due to the sustain discharge, ultraviolet rays are generated in the discharge cells 18, and the discharge cells 18 are turned on by the light emission of the phosphor layers 14 R, 14 G, and 14 B excited by the ultraviolet rays, and the discharge cells 18 of the respective colors are turned on and off. An image is displayed by the combination.
[0030]
Here, sustain driver circuit 33 includes a switching circuit 33a for switching the voltage output to sustain electrode 5, and a sustain control circuit 33b for controlling the operation of switching circuit 33a. Similarly, the scan driver circuit 34 includes a switching circuit 34a for switching the voltage output to the scan electrode 4, and a scan control circuit 34b for controlling the operation of the switching circuit 34a.
[0031]
FIG. 4 shows the waveform of the drive voltage when driving the PDP 1.
[0032]
The PDP 1 is composed of an initializing period, a plurality of (8 in FIG. 4) subfields having an initializing period, a writing period, a sustaining period, and a wall charge adjusting period, and sustain discharge is performed for each subfield. The number of sustain pulses for determining the number of times is made different, and gradation expression is performed by combining the subfields.
[0033]
An example of this driving operation will be described. First, an initialization pulse of Va (V) is applied to the scanning electrodes 4 SCN (1) to SCN (N) in the initialization period, and the wall inside the discharge cell 18 is Initialize the charge. In the subsequent writing period, in order to display the first row, a scan pulse voltage of Vb (V) is applied to the SCN (1) of the first row, and D (1) which is the data electrode 11 corresponding to the discharge cell 18. A write pulse voltage of Vdat (V) is applied to ˜D (M), and a write discharge (address discharge) is generated between D (1) to D (M) and SCN (1) in the first row, The wall charges are accumulated and the writing operation (address operation) in the first row is performed.
[0034]
The above operations are sequentially performed, and a latent image for one screen is written when the writing operation for the Nth row is completed.
[0035]
Next, in the sustain period, D (1) to D (M) are grounded. First, a sustain pulse voltage of Vs (V) is applied to all of SUS (1) to SUS (N) which are sustain electrodes 5, and then All Scan electrode 4 By applying a sustain pulse voltage of Vs (V) to SCN (1) to SCN (N) and continuing this operation alternately, emission of sustain discharge occurs in the discharge cell 18 in which the write operation is performed in the write period. The screen will be displayed. After that, in the wall charge adjustment period, all the SCN (1) to SCN (N) have the same voltage as the sustain pulse voltage Vs (V) and a narrow wall charge adjustment pulse voltage Vs1 ( v) is applied, and a weak discharge is generated as compared with the sustain discharge. Then, the wall charge of the discharge cell 18 is adjusted to an appropriate amount by this weak discharge.
[0036]
Here, the feature of the present embodiment compared to the prior art is the method of forming the wall charge adjustment pulse. That is, in the wall charge adjustment period in the present embodiment, the wall charge adjustment pulse voltage Vs1 (v), which is a voltage for adjusting the wall charge, is applied to all the SCN (1) to SCN (N) that are the scan electrodes 4. After the application, the scan electrode 4 and the sustain electrode 5 are switched to a high impedance state, and then the scan electrode 4 is switched to a voltage Vd (V) lower than the wall charge adjustment pulse voltage Vs1 and applied. Then, it is configured to apply a voltage that gradually decreases. That's it. Hereinafter, this characteristic point will be described.
[0037]
FIG. 5 is a block diagram showing a schematic configuration of the sustain driver circuit 33 and the scan driver circuit 34.
[0038]
The switching circuit 33a of the sustain electrode 5 includes a switch SW2H including a first field effect transistor 331 having a drain connected to the sustain electrode 5 in common and a source connected to a high potential Vs (V), a low potential, For example, the switch SW2L includes a second field-effect transistor 332 connected to GND. Further, it has a bidirectional switch SW4H composed of field effect transistors 333 and 334 having a source connected to Ve (V) which is a potential in the wall charge adjustment period. The switches SW2H, SW2L, and SW4H are controlled by the sustain control circuit 33b, thereby switching the voltage output to the sustain electrode 5.
[0039]
That is, the sustain control circuit 33b controls the switching of each field effect transistor constituting the switches SW2H, SW2L, and SW4H, so that the sustain electrode 5 has a high impedance state (SW2H is off, SW2L is off, and SW4H is off). For example, a low potential state such as GND (SW2H is off, SW2L is on, SW4H is off), and a high potential state is Vs (V) (SW2H is on, SW2L is off, SW4H is off), It is possible to output one of four states of Ve (V) (SW2H is off, SW2L is off, and SW4H is on), which is another state of the high potential state.
[0040]
The switching circuit 34a of the scan electrode 4 includes a switch SW1H including a third field effect transistor 341 having a drain connected to the scan electrode 4 in common and a source connected to a high potential Vs (V). And a switch SW1L including a fourth field effect transistor 342 connected to a potential, for example, GND. Furthermore, it has a bidirectional switch SW3H composed of field effect transistors 343 and 344 having their sources connected to Vd (V) which is the potential in the wall charge adjustment period. And these switches SW1H and SW 1 By controlling L and SW3H by the scanning control circuit 34b, the voltage output to the scanning electrode 4 is switched.
[0041]
That is, the scanning control circuit 34b controls the switching of each field effect transistor constituting the switches SW1H, SW1L, and SW3H, so that the scanning electrode 4 has a high impedance state (SW1H is off, SW1L is off, and SW3H is off). For example, a low potential state such as GND (SW1H is off, SW1L is on, SW3H is off), and a high potential state is Vs (V) (SW1H is on, SW1L is off, SW3H is off), It is possible to output one of four states of Vd (V) (SW1H is off, SW1L is off, and SW3H is on), which is another state of a high potential state.
[0042]
FIG. 6 shows the sustain period and the wall charge adjustment period in the drive voltage waveform in this embodiment, and the states of the switches SW1H, SW1L, SW2H, SW2L, SW3H, and SW4H at that time. For comparison, FIG. 7 shows the sustain voltage and wall charge adjustment period portions of the drive voltage waveform of the conventional PDP, and the states of the switches SW1H, SW1L, SW2H, SW2L, SW3H, and SW4H at that time. .
[0043]
In the conventional PDP, as shown in FIG. 7, the voltage for adjusting the wall charges to the scan electrodes 4 SCN (1) to SCN (N) by turning SW1H on (A in FIG. 7). Vs1 (= Vs) (V) is applied, and thereafter, it is turned off (B in FIG. 7) in a time shorter than the pulse width of the sustain pulse voltage, and at the same time, SW3H is turned on (C in FIG. 7). Thus, a wall charge adjustment pulse for generating a weak discharge for adjusting the wall charge as shown by Z in FIG. 7 is formed and applied to the scan electrode 4. As shown in FIG. 6, by setting SW1H to the on state (A in FIG. 6), Vs1 (Vs1) is a voltage for adjusting wall charges to the scan electrodes 4 SCN (1) to SCN (N). ) And then SW1H is turned off (B in FIG. 6). Remains in time t hold state, then, SW3H as the ON state (C in FIG. 6), applying a Vd (V). By such an operation, as shown in FIG. 6, after the voltage Vs1 (V), which is the voltage for adjusting the wall charge during the wall charge adjustment period, is applied, the sustain electrode 5 and the scan electrode are scanned for about time t. 4 is a high impedance state. Here, the term “during about time t” means that the switching signal is delayed when passing through the field-effect transistor, and depending on the degree of the delay, the switching timing is delayed by time t. This is because the period of the high-impedance state may not be exactly the time t even if it exists (similarly, as shown in FIG. 6, the output waveform has a delay when the switching signal passes through the field effect transistor). Therefore, it is delayed as compared with the switching signal, so it is actually necessary to determine the timing of the signal in anticipation of this delay.) In the above, discharge is generated by Vs1 (V), which is a voltage for adjusting the wall voltage applied to scan electrode 4, but sustain electrode 5 and scan electrode 4 are in a high impedance state. When the discharge starts to grow, the potential on the electrode is weakened due to the influence of the electric field generated by the generated electric charge, and the discharge stops by itself. Thereafter, Vd (V) is applied by turning on SW3H. As a result, the discharge generated by Vs1 (V) is a weak discharge suitable for adjusting the wall charge, and the voltage state at that time has a waveform as indicated by Z in FIG.
[0044]
As described above, according to the present embodiment, even when the voltage Vs1 (V) for adjusting the wall charge is large, the scale of the discharge can be controlled by the electric field of the discharge itself. , When Vs1 (V) is large, the discharge spreads to adjacent discharge cells 18, the problem of false discharge called crosstalk, and the size of Vs1 (V) is reduced more than necessary. It is possible to suppress the problem that the charge cannot be adjusted to an appropriate amount and a write failure occurs in the subsequent write period, resulting in erroneous discharge or non-lighting.
[0045]
Note that the switching control as described above is not limited to the case where the drive voltage applied to the scan electrode 4 includes a wall charge adjustment pulse from the beginning as shown in FIGS. 4 and 6. As shown in FIG. 9, the drive voltage waveform applied to the scan electrode 4 does not include the wall charge adjustment pulse, and the wall voltage varies depending on the rise timing of the drive voltage applied between the scan electrode 4 and the sustain electrode 5. The same effect can be obtained even when a voltage state equivalent to that of the charge adjustment pulse is formed.
[0046]
In addition, the voltage state at the time of high impedance of the scan electrode 4 and the sustain electrode 5 shown in FIG. 6, FIG. 8, and FIG. 9 is merely an example, and in reality, the voltage state is floating at the time of high impedance. Therefore, the illustrated state may be slightly different due to the influence between the electrodes.
[0047]
In the following, the results of studies conducted to confirm the effect of the PDP driving method of the present embodiment will be described.
[0048]
For the conventional wall charge adjustment pulse PDP (hereinafter referred to as panel A) and the wall charge adjustment pulse PDP according to the present embodiment (hereinafter referred to as panel B), a voltage margin capable of obtaining a stable display was measured. . The voltage margin is the difference between the Vs voltage at which all cells are lit when an analog signal is input and the Vs voltage at which erroneous discharge such as crosstalk occurs. The voltages other than the Vs voltage are set to the same set value.
[0049]
In a 42-inch class XGA display panel (number of pixels: 1024 × 768), for example, the pitch between the partition walls 13 is 225 μm, the thickness of the dielectric layer 7 is 35 μm, and the thickness of the MgO protective film 8 is 0.8 μm. In a panel in which the gap between the scan electrode 4 and the sustain electrode 5 is 80 μm and the height of the partition wall 13 is 120 μm, the setting values in the waveform of the drive voltage in FIG. Vd = 140V, Ve = 150V, Vs = 160V, Vs1 = 160V, and Vdat = 67V.
[0050]
The experimental results confirm that panel A has a voltage margin of 20V, while panel B has an effect of preventing the occurrence of erroneous discharge at 35V. Similarly, in the case of the drive waveforms shown in FIGS. 8 and 9, the same effects as those with the margins of 33V and 35V were obtained, respectively. Further, the control with only the externally applied voltage (scan electrode: Vd (V), sustain electrode: Ve (V)) did not change from the conventional voltage margin.
[0051]
Similar effects were also obtained in panels such as VGA.
[0052]
From the above, it is considered that the wall charges are appropriately adjusted according to the present embodiment, thereby suppressing erroneous discharge, non-lighting, and the like.
[0053]
【The invention's effect】
As described above, according to the present invention, it is possible to realize a PDP driving method capable of suppressing erroneous discharge and non-lighting caused by poor wall charge adjustment.
[Brief description of the drawings]
FIG. 1 is a plan view showing a schematic configuration of a plasma display panel according to an embodiment of the present invention.
FIG. 2 is a cross-sectional perspective view showing a schematic configuration of an image display region of a plasma display panel in an embodiment of the present invention.
FIG. 3 is a block diagram showing a schematic configuration of a plasma image display device using a plasma display panel according to an embodiment of the present invention.
FIG. 4 is a diagram showing a waveform of a driving voltage in a method for driving a plasma display panel according to an embodiment of the present invention.
FIG. 5 is a block diagram showing a schematic configuration of a sustain driver circuit and a scan driver circuit of a plasma display panel according to an embodiment of the present invention.
FIG. 6 is a diagram showing a part of a driving voltage waveform and a state of a switching circuit in the driving method of the plasma display panel according to the embodiment of the present invention.
FIG. 7 is a diagram showing a part of a driving voltage waveform and a state of a switching circuit in a conventional plasma display panel driving method;
FIG. 8 is a diagram showing a part of a driving voltage waveform and a state of a switching circuit in a driving method of a plasma display panel according to another embodiment of the present invention.
FIG. 9 is a diagram showing a part of a driving voltage waveform and a state of a switching circuit in a plasma display panel driving method according to another embodiment of the present invention;
FIG. 10 The top view which shows schematic structure of the conventional plasma display panel
FIG. 11 Sectional perspective view showing a schematic configuration of an image display region of a conventional plasma display panel
FIG. Block diagram showing a schematic configuration of a plasma image display device using a conventional plasma display panel
FIG. 13 The figure which shows the waveform of the drive voltage in the drive method of the conventional plasma display panel
[Explanation of symbols]
1 Plasma display panel
4 Scanning electrodes
5 Maintenance electrode
33a, 34a switching circuit

Claims (1)

A plurality of discharges are formed by disposing a front substrate on which display electrodes including scan electrodes and sustain electrodes are formed and a rear substrate on which data electrodes are formed so as to be orthogonal to the display electrodes so as to form a discharge space therebetween. A plasma display panel having cells formed therein, and when driving the plasma display panel, one field is constituted by a plurality of subfields, and a scan pulse voltage is applied to the scan electrodes in the subfields, and In a write period in which a write pulse voltage is applied to the data electrode to generate a write discharge, and in a discharge cell in which a write operation is performed in the write period, a sustain pulse voltage is alternately applied to the scan electrode and the sustain electrode and maintained. A plasma display panel driving method having a sustain period for generating discharge There are, after the maintenance period, the wall charge adjusting period for applying a wall charge adjusting pulse to the scanning electrode is provided, and the wall charge adjustment period, to the scan electrodes, narrow at the same voltage as the sustain pulse voltage After applying the wall charge adjustment pulse voltage, the scan electrode is set to a high impedance state, and after that, a voltage lower than the wall charge adjustment pulse voltage is applied to the scan electrode, and then a voltage gradually decreasing is applied. A method for driving a plasma display panel, characterized by comprising:

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