JP4956911B2 - Driving method of plasma display panel - Google Patents

Description

  The present invention relates to a method for driving a plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of pairs of display electrodes made up of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other, and a dielectric layer and a protective layer are formed so as to cover the display electrodes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of partition walls formed in parallel to the data electrodes on each of the dielectric layers. A phosphor layer is formed on the side surface of the partition wall. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed at a portion where the display electrode and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of RGB colors are excited and emitted by the ultraviolet light to perform color display.

  As a method for driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields. In addition, among the subfield methods, Patent Document 1 discloses a novel driving method in which light emission not related to gradation display is reduced as much as possible to suppress an increase in black luminance and an contrast ratio is improved.

  The driving method will be briefly described below. Each subfield has an initialization period, a writing period, and a sustain period. The initializing period is an all-cell initializing period in which an initializing discharge is performed on all discharge cells that perform image display, or a discharge cell that has undergone a sustain discharge in the immediately preceding subfield. A selective initializing period for performing a selective initializing operation for selectively performing initializing discharge.

  First, during the all-cell initialization period, all discharge cells perform initialization discharge all at once, erasing the wall charge history for each previous discharge cell, and forming the wall charge required for the subsequent write operation To do. In addition, it has a function of generating priming (priming for discharge = excited particles) for reducing the discharge delay and stably generating the write discharge. In the subsequent writing period, a scanning pulse is sequentially applied to the scanning electrodes, and a writing pulse corresponding to an image signal to be displayed is applied to the data electrodes to selectively cause a writing discharge between the scanning electrodes and the data electrodes. , Selective wall charge formation. In the sustain period, a predetermined number of sustain pulses corresponding to the luminance weight are applied between the scan electrodes and the sustain electrodes, and the discharge cells in which the wall charges are formed by the write discharge are selectively discharged to emit light.

  As described above, in order to display an image correctly, it is important to surely perform selective writing discharge in the writing period. To that end, it is necessary to surely perform an initialization operation to prepare for the writing operation. Is important.

  On the other hand, in the all-cell initialization operation, it is necessary to generate an initialization discharge with the scan electrode as the anode and the sustain electrode and the data electrode as the cathode, but a phosphor having a small electron emission coefficient is applied to the data electrode side. For this reason, the discharge delay of the initialization discharge using the data electrode as a cathode increases, and the initialization discharge may become unstable. This narrows the drive voltage margin for the write operation, such as the possibility of a write failure during the write period.

For this reason, in the all-cell initializing period, an abnormal charge erasing unit is provided that generates a self-erasing discharge for the discharge cells that apply a rectangular waveform voltage to the scan electrodes and accumulate excessive wall voltage. Had improved.
JP 2000-242224 A

  By the way, when the cell is lit for a long time, impurities contained in the gas generated during lighting may adhere to the scan electrode and sustain electrode of the adjacent unlit cell, and the discharge start voltage may decrease. .

  As a result, in the abnormal charge erasing unit arranged immediately after the all-cell initialization period, a strong discharge occurs and a self-erasing discharge is performed, which makes it impossible to perform the subsequent writing operation, and causes the image quality to deteriorate significantly. became.

  In recent years, studies have been made to increase the luminous efficiency of the panel by increasing the xenon partial pressure of the discharge gas sealed in the panel. However, increasing the xenon partial pressure may reduce discharge, particularly the discharge start voltage. There is a problem that a write failure occurs in the subsequent write period, and the drive voltage margin of the write operation becomes narrow.

  The present invention has been made in view of these problems, and an object of the present invention is to provide a method of driving a plasma display panel that can display an image with high quality by stabilizing the initialization discharge.

  A driving method of a plasma display panel according to the present invention is a driving method of a plasma display panel in which discharge cells are formed at intersections of scan electrodes, sustain electrodes, and data electrodes, with respect to all discharge cells in one field. A subfield having an all-cell initializing period for generating an initializing discharge, and a subfield having a selective initializing period for selectively generating an initializing discharge for a discharge cell having generated a sustain discharge, The all-cell initializing period includes a first initializing period section that applies a first ramp waveform voltage to the scan electrodes and performs a first initializing discharge using the scan electrode as an anode and a sustain electrode and a data electrode as a cathode; And a second initializing period portion for applying a second ramp waveform voltage to the electrode and performing a second initializing discharge using the scan electrode as a cathode and the sustain electrode and the data electrode as an anode. And a sub-field with a selective initializing period immediately after the sub-field having a all-cell initializing period, characterized by disposing the abnormal charge erasing unit for applying a rectangular wave voltage to the scan electrodes.

  Further, when a subfield having a plurality of all-cell initializing periods exists in one field, the abnormal charge erasing unit is included in the subfield having a selective initializing period immediately after the subfield having at least one all-cell initializing period. It is characterized by arranging.

  In addition, in the plurality of subfields having the all-cell initializing period in one field, the abnormal charge erasing unit is arranged in the subfield having the selective initializing period immediately after the subfield having the smallest number of sustain pulses. The abnormal charge erasing part is arranged in a subfield having an all-cell initializing period other than the above.

  In addition, the abnormal charge erasing unit is arranged in the subfield having the selective initialization period immediately after the subfield having the first all-cell initializing period in one field, and thereafter, the subcell having the all-cell initializing period is arranged. It is arranged in the field.

  As a result, it is possible to provide a method for driving a plasma display panel that can stabilize the initializing discharge and display an image with good quality even when the discharge start voltage decreases.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the drive method of the plasma display panel which can display an image with favorable quality by stabilizing initialization discharge.

  Hereinafter, a method for driving a plasma display panel according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
FIG. 1 is a perspective view showing a main part of a panel used in an embodiment of the present invention. The panel 1 is configured such that a glass front substrate 2 and a back substrate 3 are disposed to face each other and a discharge space is formed therebetween. On the front substrate 2, a plurality of scanning electrodes 4 and sustaining electrodes 5 constituting display electrodes are formed in parallel with each other. A dielectric layer 6 is formed so as to cover the scan electrode 4 and the sustain electrode 5, and a protective layer 7 is formed on the dielectric layer 6. The protective layer 7 is preferably made of a material having a large secondary electron emission coefficient and high sputtering resistance in order to generate a stable discharge. In the embodiment, an MgO thin film is used.

  A plurality of data electrodes 9 covered with an insulating layer 8 are provided on the back substrate 3, and a partition wall 10 is provided in parallel with the data electrodes 9 on the insulating layer 8 between the data electrodes 9. In addition, phosphors 11 are provided on the surface of the insulator layer 8 and the side surfaces of the partition walls 10. The front substrate 2 and the rear substrate 3 are arranged to face each other in the direction in which the scan electrode 4 and the sustain electrode 5 and the data electrode 9 intersect, and in the discharge space formed between them, for example, neon is used as a discharge gas. A mixed gas of xenon is enclosed. In the present embodiment, in order to improve the light emission efficiency of the panel, the xenon partial pressure of the discharge gas sealed in the panel is increased to 10%.

  FIG. 2 is an electrode array diagram of the panel according to the embodiment of the present invention. N scan electrodes SCN1 to SCNn (scan electrode 4 in FIG. 1) and n sustain electrodes SUS1 to SUSn (sustain electrode 5 in FIG. 1) are alternately arranged in the row direction, and m data electrodes in the column direction. D1 to Dm (data electrodes 9 in FIG. 1) are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCNi and sustain electrode SUSi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed.

  FIG. 3 is a configuration diagram of a plasma display apparatus using the panel driving method according to the embodiment of the present invention. The plasma display device includes a panel 1, a data electrode drive circuit 12, a scan electrode drive circuit 13, a sustain electrode drive circuit 14, a timing generation circuit 15, an AD (analog / digital) converter 18, a scan number conversion unit 19, and a subfield. A conversion unit 20, an APL (Average Picture Level) detection unit 21, and a power supply circuit (not shown) are provided.

  In FIG. 3, the image signal sig is input to the AD converter 18. The horizontal synchronization signal H and the vertical synchronization signal V are input to the timing generation circuit 15, the AD converter 18, the scanning number conversion unit 19, and the subfield conversion unit 20. The AD converter 18 converts the image signal sig into digital signal image data, and outputs the image data to the scanning number conversion unit 19 and the APL detection unit 21. The APL detection unit 30 detects the average luminance level of the image data. The scanning number conversion unit 19 converts the image data into image data corresponding to the number of pixels of the panel 1 and outputs the image data to the subfield conversion unit 20. The subfield conversion unit 20 divides the image data of each pixel into a plurality of bits corresponding to a plurality of subfields, and outputs the image data for each subfield to the data electrode driving circuit 12. The data electrode drive circuit 12 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes.

  The timing generation circuit 15 generates a timing signal based on the horizontal synchronization signal H and the vertical synchronization signal V, and outputs the timing signal to the scan electrode drive circuit 13 and the sustain electrode drive circuit 14, respectively. Scan electrode drive circuit 13 supplies a drive waveform to scan electrodes SCN1 to SCNn based on the timing signal, and sustain electrode drive circuit 14 supplies a drive waveform to sustain electrodes SUS1 to SUSn based on the timing signal. Here, the timing circuit controls the drive waveform based on the APL output from the APL detection unit 21. Specifically, based on APL, the initialization operation of each subfield constituting one field is determined as either all-cell initialization or selective initialization, and the subfield in which the abnormal charge erasing unit is arranged To decide. The subfield in which the abnormal charge erasing part is arranged will be described later.

  Next, a driving waveform for driving the panel and its operation will be described. In the embodiment, one field is divided into 10 subfields (first SF, second SF,..., 10th SF), and each subfield is (1, 2, 3, 6, 11, 18, 30). , 44, 60, 80). In this way, the luminance weight is configured to increase in the rear subfield.

  FIG. 4 is a drive waveform diagram applied to each electrode of the plasma display panel in accordance with the exemplary embodiment of the present invention, and shows a subfield having an initialization period for performing the all-cell initialization operation (hereinafter, “all-cell initialization subfield”). And a drive waveform diagram for a subfield having an initialization period for performing a selective initialization operation (hereinafter abbreviated as “selective initialization subfield”). FIG. 4 shows the first SF as an all-cell initialization subfield and the second subfield as a selective initialization subfield for explanation.

  First, the drive waveform and operation of the all-cell initialization subfield will be described. The all-cell initialization period will be described by dividing it into two periods of the first half and the second half as follows.

  In the first half of the initialization period, which is the first initialization period, sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm are held at 0 (V), and are equal to or lower than the discharge start voltage with respect to scan electrodes SCN1 to SCNn. A ramp voltage that gradually rises from a voltage Vp (V) to a voltage Vr (V) exceeding the discharge start voltage is applied. Then, a weak initializing discharge is generated with scan electrodes SCN1 to SCNn as anodes and sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm as cathodes. Thus, the first weak initializing discharge is generated in all the discharge cells, the negative wall voltage is stored on the scan electrodes SCN1 to SCNn, and the positive wall on the sustain electrodes SUS1 to SUSn and the data electrodes D1 to Dm. Stores voltage. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer or the phosphor layer covering the electrode.

  In the second half of the initialization period, which is the second initialization period, sustain electrodes SUS1 to SUSn are kept at positive voltage Vh (V), and voltage Vg (V) to voltage Va (V) is applied to scan electrodes SCN1 to SCNn. A ramp voltage that gradually falls toward is applied. Then, in all the discharge cells, a second weak initializing discharge is generated using scan electrodes SCN1 to SCNn as cathodes and sustain electrodes SUS1 to SUSn and data electrodes D1 to Dm as anodes. Then, the wall voltage on scan electrodes SCN1 to SCNn and the wall voltage on sustain electrodes SUS1 to SUSn are weakened, and the wall voltage on data electrodes D1 to Dm is also adjusted to a value suitable for the write operation. As described above, the initialization operation in the all-cell initialization subfield is an all-cell initialization operation in which initialization discharge is performed in all discharge cells.

  Next, the drive waveform and the operation of the selective initialization subfield will be described.

  In the initialization period, sustain electrodes SUS1 to SUSn are held at Vh (V), data electrodes D1 to Dm are held at 0 (V), and scan electrodes SCN1 to SCNn are moved from Vq (V) to Va (V). Apply a ramp voltage that falls slowly. Then, in the discharge cell in which the sustain discharge is performed in the sustain period of the previous subfield, a weak initializing discharge is generated, the wall voltage on scan electrode SCN1 and sustain electrode SUSi is weakened, and the wall voltage on data electrode Dk is reduced. Is also adjusted to a value suitable for the write operation. On the other hand, the discharge cells that did not perform the write discharge and the sustain discharge in the previous subfield are not discharged, and the wall charge state at the end of the initialization period of the previous subfield is maintained as it is. As described above, the initializing operation in the selective initializing subfield is a selective initializing operation in which initializing discharge is performed in the discharge cells that have undergone sustain discharge in the previous subfield.

  Next, in the abnormal charge erasing unit, the sustain electrodes SUS1 to SUSn are returned to 0 (V) again. Then, a positive voltage Vm (V) less than the discharge start voltage is applied to scan electrodes SCN1 to SCNn for 5 to 20 μs, and then a negative voltage Va (V) for a short time of 3 μs or less is set to be rectangular. Apply wave voltage. During this time, discharge does not occur in the discharge cells that have performed stable initialization discharge, and the wall voltage also maintains the state of the latter half of the initialization period. However, for discharge cells in which positive abnormal wall charges are accumulated on scan electrode SCNi, a strong discharge occurs because the discharge start voltage is exceeded when voltage Vm (V) is applied to scan electrodes SCN1 to SCNn. The wall voltage on the electrode SCNi is inverted. Then, when a narrow negative pulse voltage Va (V) is applied to scan electrodes SCN1 to SCNn, self-erasing discharge is generated and the wall voltage inside the discharge cell is erased.

  Next, in the writing period, scan electrodes SCN1 to SCNn are temporarily held at Vs (V). Next, a positive write pulse voltage Vw (V) is applied to the data electrode Dk of the discharge cell to be displayed in the first row among the data electrodes D1 to Dm, and the scan pulse voltage is applied to the scan electrode SCN1 in the first row. Vb (V) is applied. At this time, the voltage at the intersection between the data electrode Dk and the scan electrode SCN1 is obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SCN1 to the externally applied voltage (Vw−Vb). And the discharge start voltage is exceeded. Then, a write discharge occurs between data electrode Dk and scan electrode SCN1 and between sustain electrode SUS1 and scan electrode SCN1, and a positive wall voltage is accumulated on scan electrode SCN1 of this discharge cell, and on sustain electrode SUS1. And a negative wall voltage is also accumulated on the data electrode Dk. In this way, an address operation is performed in which an address discharge is caused in the discharge cells to be displayed in the first row and a wall voltage is accumulated on each electrode.

  On the other hand, since the voltage at the intersection of the data electrode to which the positive write pulse voltage Vw (V) is not applied and the scan electrode SCN1 does not exceed the discharge start voltage, no write discharge occurs. Further, since the discharge cell that has caused a discharge in the abnormal charge erasing portion during the initialization period has also erased the wall voltage on the data electrode, no write discharge occurs. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  Next, in the sustain period, first, sustain electrodes SUS1 to SUSn are returned to 0 (V), and positive sustain pulse voltage Vm (V) is applied to scan electrodes SCN1 to SCNn. At this time, in the discharge cell in which the write discharge has occurred, the voltage between scan electrode SCNi and sustain electrode SUSi is equal to sustain pulse voltage Vm (V) as the wall voltage on scan electrode SCNi and sustain electrode SUSi. The magnitude is added and exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCNi and sustain electrode SUSi, a negative wall voltage is accumulated on scan electrode SCNi, and a positive wall voltage is accumulated on sustain electrode SUSi. At this time, a positive wall voltage is also accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage state at the end of the initialization period is maintained.

  Subsequently, scan electrodes SCN1 to SCNn are returned to 0 (V), and positive sustain pulse voltage Vm (V) is applied to sustain electrodes SUS1 to SUSn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage between the sustain electrode SUSi and the scan electrode SCNi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUSi and the scan electrode SCNi, A positive wall voltage is accumulated on sustain electrode SUSi, and a positive wall voltage is accumulated on scan electrode SCNi.

  Thereafter, similarly, by applying sustain pulses alternately to scan electrodes SCN <b> 1 to SCNn and sustain electrodes SUS <b> 1 to SUSn, the sustain discharge is continuously performed in the discharge cells in which the address discharge is generated in the address period. At the end of the sustain period, a so-called narrow pulse is applied between scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn to leave positive wall charges on data electrode Dk, and leave scan electrodes SCN1 to SCN1. The wall voltages on SCNn and sustain electrodes SUS1 to SUSn are erased. Thus, the maintenance operation in the maintenance period is completed.

  By the way, as shown in FIG. 5, if the abnormal charge erasing part is arranged immediately after the all-cell initializing period, the discharge start voltage is exceeded, and wall charges are released by self-erasing discharge, and writing is performed in the subsequent writing period. It will not be possible to perform the operation.

  This is because when an adjacent cell is lit, impurities contained in the gas leaked from the adjacent cell adhere to the protective layer 7 and the discharge start voltage decreases.

  Therefore, by arranging the abnormal charge erasing portion arranged in the subfield of the all-cell initializing period in the selective initializing subfield immediately after that, writing failure can be prevented. As a result, in the sustain period of the all-cell initialization subfield, the sustain discharge is erroneously generated by applying the sustain pulse voltage Vm (V). Thereafter, the sustain discharge is initialized by the initialization operation of the selective initialization subfield. The What is important here is that, due to the sustain discharge, impurities adhering to the protective layer 7 are diffused and removed again as a gas, and the reduced discharge start voltage increases. As a result, a stable initialization operation is performed, and a normal write operation can be performed in the subsequent write period without causing a self-erase discharge even if an abnormal charge erasing portion is disposed later. On the other hand, since the self-erase discharge occurs and the wall voltage inside the discharge cell is erased with respect to the discharge cell in which positive abnormal wall charges remain accumulated on the scan electrode SCNi, The effect remains sustained.

  Further, in order for impurities to adhere to the protective layer 7 and the discharge start voltage to decrease to cause a problem, it is necessary to turn on the adjacent cells for a long time. For this reason, the abnormal charge erasing portion is arranged in the selective initialization subfield, and the frequency of removing the attached impurities can be reduced.

  In other words, there is a mixture of an abnormal charge erasing unit arranged in a subfield having an all-cell initializing period and an abnormal charge erasing unit arranged in a selective initializing subfield immediately after a subfield having an all-cell initializing period. Therefore, a subfield that is erroneously subjected to sustain discharge can be assigned to a subfield having a small number of sustain pulses. As a result, light emission at this time can be suppressed, and once the lamp is erroneously turned on, a stable discharge can be obtained for a long time thereafter, so that the image quality is not deteriorated.

  FIG. 6 is a diagram showing an arrangement example of subfields in which the all-cell initializing period and the abnormal charge erasing unit are arranged. In FIG. 6, one field is composed of 12 subfields (1SF to 12SF), and in the pattern A, all cell initialization periods are provided in 1SF, 4SF, and 7SF, and the abnormal charge erasing unit has an all cell initialization period. It is arranged in 2SF next to the provided 1SF, and 4SF and 7SF provided with the all-cell initialization period next. In the pattern B, all-cell initializing periods are provided in 1SF and 5SF, and the abnormal charge erasing unit is arranged in 2SF next to 1SF and 5SF having an all-cell initializing period next. In the pattern C, the all-cell initializing period is provided only for 1SF, and the abnormal charge erasing section is arranged in 2SF next to 1SF.

  The driving method of the plasma display panel according to the present invention enables stable high-speed writing and driving of the plasma display panel with suppressed increase in black luminance, and is useful as an image display device using the plasma display panel. is there.

The perspective view which shows the principal part of the panel used for the drive method of the plasma display panel by one embodiment of this invention Electrode arrangement of the panel The block diagram of the plasma display apparatus which implement | achieves the drive method in one embodiment of this invention Drive waveform diagram applied to each electrode of the panel in one embodiment of the present invention Drive waveform diagram applied to each electrode of the panel in the comparative example of the present invention Explanatory drawing which shows the example of arrangement | positioning of all the cell initialization periods and an abnormal charge erasing part in the drive method of this invention

Explanation of symbols

SUS1-SUSn Sustain electrode D1-Dm Data electrode SCN1-SCNn Scan electrode

Claims (1)

Combination of subfields that emit light by dividing one field into a plurality of subfields having an initializing period, a writing period, and a sustaining period in a plasma display panel in which discharge cells are formed at intersections of scan electrodes, sustain electrodes, and data electrodes A method of driving a plasma display panel that performs gradation display by:
A first initializing period portion for applying a first ramp waveform voltage to the scan electrode during one field and performing a first initializing discharge using the scan electrode as an anode and the sustain electrode and the data electrode as a cathode; A second initializing period portion for applying a second ramp waveform voltage to the scan electrode and performing a second initializing discharge using the scan electrode as a cathode and the sustain electrode and the data electrode as an anode. A subfield having an all-cell initializing period for generating an initializing discharge for all discharge cells;
Applying a downward ramp waveform voltage that gradually falls from a positive voltage to a negative voltage to the scan electrode, and selectively initializing discharge cells that have generated a sustain discharge in the sustain period of the immediately preceding subfield A subfield having a selective initialization period for generating a discharge,
In the subfield having the selective initializing period immediately after the subfield having the all-cell initializing period, the scan electrode is set to the scan electrode while maintaining the sustain electrode at a ground potential between the selective initializing period and the writing period. An abnormal charge erasing unit that generates a discharge in the discharge cell in which abnormal wall charges are accumulated by applying a positive voltage and subsequently applying a rectangular wave voltage having a negative voltage that is narrower than the positive voltage. A method for driving a plasma display panel, comprising: disposing the plasma display panel.

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