JP5119613B2 - Driving method of plasma display panel - Google Patents

Description

  The present invention relates to a method for driving a plasma display panel used in a wall-mounted television or a large monitor.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other. In the front plate, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes are formed in parallel with each other on the front glass substrate, and a dielectric layer and a protective layer are formed so as to cover the display electrode pairs. Yes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of barrier ribs in parallel with the data electrodes formed on the back glass substrate. A phosphor layer is formed on the side walls of the barrier ribs. Then, the front plate and the back plate are arranged opposite to each other so that the display electrode pair and the data electrode are three-dimensionally crossed and sealed, and a discharge gas containing, for example, 5% xenon is enclosed in the internal discharge space. Has been. Here, a discharge cell is formed in a portion where the display electrode pair and the data electrode face each other. In the panel having such a configuration, ultraviolet light is generated by gas discharge in each discharge cell, and phosphors of red, green, and blue colors are excited and emitted by the ultraviolet light to perform color display.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields. Each subfield has an initialization period, an address period, and a sustain period. In the initialization period, an initialization discharge is generated, and wall charges necessary for the subsequent address operation are formed on each electrode. In the address period, address discharge is selectively generated in the discharge cells to be displayed to form wall charges. In the sustain period, a sustain pulse is alternately applied to the display electrode pair composed of the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell in which the address discharge is generated, and the phosphor layer of the corresponding discharge cell is caused to emit light. The image is displayed.

  In addition, among the subfield methods, initializing discharge is performed using a slowly changing voltage waveform, and further, initializing discharge is selectively performed on discharge cells that have undergone sustain discharge. A novel driving method is disclosed in which the light emission that is not generated is reduced as much as possible to improve the contrast ratio.

  Specifically, among the plurality of subfields, an initialization operation (hereinafter abbreviated as “all cell initialization operation”) for discharging all discharge cells in the initialization period of one subfield is performed. In the initializing period of the subfield, an initializing operation (hereinafter abbreviated as “selective initializing operation”) for initializing only the discharge cells that have undergone sustain discharge is performed. As a result, light emission unrelated to display is only light emission accompanying discharge in the all-cell initialization operation, and high-contrast image display is possible (for example, see Patent Document 1).

By driving in this way, the luminance of the black display area (black luminance) that changes depending on the light emission not related to the image display is only weak light emission in the all-cell initialization operation, and an image display with high contrast is possible. It becomes.
JP 2000-242224 A

  However, in recent years, panels have become larger and have a larger screen, so that the address discharge becomes unstable, and the address discharge does not occur in the discharge cells to be displayed. There have been problems such as an increase in voltage necessary for stably generating address discharge.

  The present invention has been made in view of these problems, and generates a stable address discharge without increasing the voltage necessary for generating the address discharge even in a large screen / high brightness panel, It is an object to provide a method for driving a panel with good display quality.

The present invention relates to a panel driving method in which a discharge cell is formed at the intersection of a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode, and an initialization for applying a slowly decreasing ramp waveform voltage to the scan electrode. One field period includes a subfield having a period, an address period in which an address discharge is selectively generated in the discharge cells, and a sustain period in which the number of sustain discharges corresponding to the luminance weight is generated in the discharge cells in which the address discharge is generated The voltage value applied to the sustain electrode in the address period of the predetermined subfield among the plurality of subfields is lower than the voltage value applied to the sustain electrode in the address period of the subfield other than the predetermined subfield. The lowest voltage value of the ramp waveform voltage that gradually falls during the initialization period of a given subfield is The voltage between the scan electrode and the sustain electrode at the time when the slowly decreasing ramp waveform voltage is lower than the lowest voltage value of the slowly decreasing ramp waveform voltage in the initialization period of the subfield other than the fixed subfield The difference is set so that the subfields other than the predetermined subfields are smaller than the predetermined subfields, and the entire cell initialization operation is performed in the predetermined subfields. In the subfield, a selective initialization operation is performed . This method can generate stable address discharge and display an image with good display quality without increasing the voltage necessary for generating address discharge even in a large screen / high brightness panel. . In addition, the effect of canceling out the address discharge due to the influence of priming and the effect of the residual wall voltage in the sustain period becomes more significant, and stable address can be achieved without increasing the voltage required to generate the address discharge. It is possible to generate an electric discharge and display an image with good display quality.

  In the panel driving method of the present invention, the predetermined subfield may be a subfield subsequent to the subfield in which the sustain discharge is generated once in the sustain period. According to this method, the influence of the residual wall voltage in the sustain period can be offset.

  ADVANTAGE OF THE INVENTION According to this invention, even if it is a large screen and a high-intensity panel, it is possible to generate a stable address discharge without increasing the voltage necessary for generating the address discharge, and to drive the panel with good image display quality. Can be provided.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of panel 10 according to Embodiment 1 of the present invention. On the glass front plate 21, a plurality of display electrode pairs 28 made up of the scan electrodes 22 and the sustain electrodes 23 are formed. A dielectric layer 24 is formed so as to cover the scan electrode 22 and the sustain electrode 23, and a protective layer 25 is formed on the dielectric layer 24. A plurality of data electrodes 32 are formed on the back plate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 21 and the back plate 31 are arranged to face each other so that the display electrode pair 28 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. In the present embodiment, a discharge gas with a xenon partial pressure of 10% is used to improve luminance. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 28 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel is not limited to the above-described structure, and for example, a structure having a stripe-shaped partition may be used.

  FIG. 2 is an electrode array diagram of panel 10 in accordance with the first exemplary embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi (i = 1 to n) intersects with one data electrode Dj (j = 1 to m). , M × n discharge cells are formed in the discharge space.

  FIG. 3 is a circuit block diagram of plasma display device 1 in accordance with the first exemplary embodiment of the present invention. The plasma display apparatus 1 includes a panel 10, an image signal processing circuit 51, a data electrode drive circuit 52, a scan electrode drive circuit 53, a sustain electrode drive circuit 54, a timing generation circuit 55, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 51 converts the input image signal sig into image data indicating light emission / non-light emission for each subfield. The data electrode driving circuit 52 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm.

  The timing generation circuit 55 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to each circuit block. Scan electrode driving circuit 53 drives each of scan electrodes SC1 to SCn based on the timing signal. Sustain electrode drive circuit 54 drives sustain electrodes SU1 to SUn based on the timing signal.

  Next, a driving method for driving the panel 10 will be described. The plasma display device 1 performs gradation display by subfield method, that is, dividing one field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, an address period, and a sustain period. In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent address discharge are formed on each electrode. The initializing operation at this time includes an all-cell initializing operation in which initializing discharge is generated in all discharge cells, and a selective initializing operation in which initializing discharge is generated in the discharge cells that have undergone sustain discharge. In the address period, address discharge is selectively generated in the discharge cells to emit light to form wall charges. In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the display electrode pair 28 to generate a sustain discharge in the discharge cells that have generated the address discharge, thereby causing light emission. The proportional constant at this time is called luminance magnification.

  FIG. 4 is a diagram showing a subfield configuration according to Embodiment 1 of the present invention. FIG. 4 schematically shows a drive voltage waveform between one field in the subfield method, and detailed drive voltage waveforms in an initialization period, an address period, and a sustain period of each subfield will be described later.

  In the present embodiment, one field is divided into 10 subfields (first SF, second SF,..., 10th SF), and each subfield is, for example, (1, 2, 3, 6, 11, It is assumed that the luminance weight is 18, 30, 44, 60, 81) and the luminance magnification is 2. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by the luminance magnification is applied to the display electrode pair 28. In the present embodiment, the all-cell initialization operation is performed in the initialization period of the first SF, and the selective initialization operation is performed in the initialization period of the second SF to the tenth SF.

  In the present embodiment, the predetermined subfield is the first SF. That is, the lowest voltage value of the falling ramp waveform voltage applied to the scan electrode 22 in the initializing period of the first SF is the lowest voltage value of the falling ramp waveform voltage applied to the scan electrode 22 in the initializing period of the subfield other than the first SF. The voltage value is set to be lower than the low voltage value, and the voltage value applied to the sustain electrode 23 in the address period of the first SF is lower than the voltage value applied to the sustain electrode 23 in the address period of the subfield other than the first SF. Is set.

  Below, the detail of the drive voltage waveform for driving the panel 10 and its operation | movement are demonstrated. FIG. 5 is a waveform diagram of drive voltage applied to each electrode of panel 10 in the first exemplary embodiment of the present invention. FIG. 5 shows details of the driving voltage waveforms of the first SF to the third SF. In addition, the initialization period of 1st SF which performs all-cell initialization operation | movement is divided into the front half part and the latter half part for convenience, and is demonstrated.

  In the first half of the initializing period of the first SF, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and the discharge start voltage with respect to the sustain electrodes SU1 to SUn is applied to the scan electrodes SC1 to SCn. From the following voltage Vi1, an upward ramp waveform voltage that gently rises toward a voltage Vi2 that exceeds the discharge start voltage is applied. While this ramp waveform voltage rises, a weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, and scan electrodes SC1 to SCn receive a discharge start voltage from voltage Vi3 that is equal to or lower than the discharge start voltage with respect to sustain electrodes SU1 to SUn. A downward ramp waveform voltage that gently falls toward the exceeding voltage Vi4L is applied.

  During this time, weak initializing discharges occur between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, respectively. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The The wall voltage above the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  Here, the initializing discharge generated by applying the downward ramp waveform voltage to the scan electrodes SC1 to SCn has a function of weakening the wall voltage above the data electrodes D1 to Dm. Accordingly, the wall voltage above the data electrodes D1 to Dm changes in accordance with the voltage value of the initialization voltage Vi4L having the lowest downward ramp waveform voltage, and increasing the voltage value of the voltage Vi4L weakens the function of weakening the wall voltage. The wall voltage at the upper part of D1 to Dm is increased, and when the voltage value of the voltage Vi4L is lowered, the wall voltage is weakened and the wall voltage at the upper part of the data electrodes D1 to Dm is lowered. In the present embodiment, lowest initialization voltage Vi4L applied to scan electrodes SC1 to SCn is set to be lower than voltage Vi4H applied in the initialization period of the subfield other than the first SF. Therefore, the wall voltage above the data electrodes D1 to Dm is adjusted low.

  Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  In the address period of the first SF, voltage Ve2L is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn. Here, voltage Ve2L applied to sustain electrodes SU1 to SUn is set to be lower than voltage Ve2H applied in the address period of the subfield other than the first SF. In the present embodiment, voltage Ve2L is voltage It is set equal to Ve1.

  Next, the negative scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the data electrode Dk (k = 1 to m) of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. A positive address pulse voltage Vd is applied. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the voltage applied to the electrode (Vd−Va) and the difference between the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1. Exceeds the discharge start voltage. Then, a discharge occurs between data electrode Dk and scan electrode SC1, progresses to a discharge between sustain electrode SU1 and scan electrode SC1, an address discharge occurs, and a positive wall voltage accumulates on scan electrode SC1. Thus, a negative wall voltage is accumulated on the sustain electrode SU1, and a negative wall voltage is also accumulated on the data electrode Dk.

  In the present embodiment, since the wall voltage above the data electrodes D1 to Dm is adjusted to be lower than that of the other subfields during the initialization period of the first SF, the data electrode Dk and the scan electrode SC1 The voltage difference at the intersection is lower than that in the other subfields. Thus, the initialization operation of the first SF of the present embodiment works to weaken the discharge between the data electrode Dk and the scan electrode SC1. In addition, the voltage Ve2L applied to the sustain electrodes SU1 to SUn is also set to be lower than the voltage Ve2H applied in the address period of the subfield other than the first SF, and between the sustain electrode SU1 and the scan electrode SC1. Works to weaken the discharge. Thus, in the present embodiment, the driving method is to reduce the strength of the address discharge in the first SF.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse voltage Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur. The above address operation is performed until the discharge cell in the nth row of scan electrode SCn, and the address period ends.

  In the sustain period of the first SF, first, sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn, and 0 (V) is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, 0 (V) is applied to scan electrodes SC1 to SCn, and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. A negative wall voltage is accumulated on SUi, and a positive wall voltage is accumulated on scan electrode SCi.

  Then, at the end of the sustain period, a so-called narrow pulse voltage difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and the positive wall voltage on data electrode Dk is left while scanning. The wall voltage on electrode SCi and sustain electrode SUi is erased.

  In the subsequent initialization period of the second SF, 0 (V) is applied to the data electrodes D1 to Dm, the positive voltage Ve1 is applied to the sustain electrodes SU1 to SUn, and the sustain electrodes SU1 to SUn are applied to the scan electrodes SC1 to SCn. In contrast, a downward ramp waveform voltage that gently falls from a voltage Vi3 that is equal to or lower than the discharge start voltage to a voltage Vi4H that exceeds the discharge start voltage is applied. Then, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has occurred in the sustain period of the immediately preceding subfield, and the wall voltage on each electrode is adjusted to a wall voltage suitable for the subsequent address operation.

  Here, voltage Vi4H is set to be higher than the lowest voltage value Vi4L of the downward ramp waveform voltage applied to scan electrodes SC1 to SCn in a predetermined subfield, in the present embodiment, the initialization period of the first SF. ing. Therefore, the wall voltage above the data electrodes D1 to Dm is adjusted to be higher than that of the first SF.

  On the other hand, the discharge cells that did not cause the sustain discharge in the immediately preceding subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained. As described above, the initializing operation of the second SF is a selective initializing operation, and the initializing discharge is selectively performed on the discharge cells that have undergone the sustain operation in the sustain period of the immediately preceding subfield.

  In the address period of the second SF, voltage Ve2H is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn. Here, voltage Ve2H applied to sustain electrodes SU1 to SUn is set to be higher than voltage Ve2L applied in the writing period of the first SF.

  Next, the scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the positive address pulse voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row, thereby causing the address discharge and causing each discharge. An address operation for accumulating wall voltage on the electrodes is performed.

  In the present embodiment, since the wall voltage above the data electrodes D1 to Dm is adjusted to be higher than the first SF during the initialization period of the second SF, the initialization operation of the second SF is performed by scanning with the data electrode Dk. It works to strengthen the discharge between the electrode SC1. In addition, the voltage Ve2H applied to the sustain electrodes SU1 to SUn is also set to be higher than the voltage Ve2L applied in the address period of the first SF, thereby strengthening the discharge between the sustain electrode SU1 and the scan electrode SC1. To work. Thus, in the present embodiment, the driving method is to increase the strength of the address discharge in the second SF.

  In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, no address discharge occurs in the discharge cells to which the address pulse voltage Vd is not applied. The above address operation is performed until the discharge cell in the nth row of scan electrode SCn, and the address period ends.

  The operation during the sustain period of the second SF is the same as the operation of the first SF except for the number of sustain pulses applied to the display electrode pair 28. That is, by applying a number of sustain pulses obtained by multiplying the luminance weight to the luminance magnification alternately to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and applying a potential difference between the electrodes of the display electrode pair 28, in the writing period The sustain discharge is continuously performed in the discharge cell in which the address discharge has occurred. At the end of the sustain period, a narrow pulse-shaped voltage difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, leaving the positive wall voltage on data electrode Dk, and the scan electrode. The wall voltage on SCi and sustain electrode SUi is erased.

  Since the operations of the third SF to the tenth SF are the same as the operations of the second SF except for the number of sustain pulses applied to the display electrode pair 28, the description is omitted.

  In the present embodiment, for example, voltage Vi1 = voltage Vi3 = voltage Vs = 180 (V), voltage Vi2 = 420 (V), voltage Vi4H = −85 (V), voltage Vi4L = −90 (V) Voltage Ve1 = Voltage Ve2L = 160 (V), Voltage Ve2H = 165 (V). However, these voltage values are merely an example, and it is desirable to set them appropriately to optimum values according to the panel characteristics, the specifications of the plasma display device, and the like.

  Next, the reason why the driving method in the present embodiment can generate a stable address discharge without increasing the voltage necessary for generating the address discharge even in a large screen / high brightness panel. explain.

  Immediately after the initializing discharge is completed in the initializing period of each subfield, the voltage obtained by adding the wall voltage to the voltage applied to the data electrode Dk and the scan electrode SCi is substantially equal to the discharge start voltage. This is also clear from the fact that a weak initializing discharge was generated between the data electrode Dk and the scan electrode SCi in the initializing period.

  In order to generate the address discharge, the address pulse voltage Vd may be applied to the data electrode Dk and the scan pulse voltage Va may be applied to the scan electrode SCi so as to exceed the discharge start voltage. However, this is not sufficient to generate the address discharge reliably and stably, and a voltage higher than the discharge start voltage (hereinafter referred to as “stable discharge voltage”) between the data electrode Dk and the scan electrode SCi. Must be given).

  On the other hand, in the discharge cell to which only the address pulse voltage Vd or only the scan pulse voltage Va is applied, the voltage between the data electrode Dk and the scan electrode SCi does not exceed the discharge start voltage so that unnecessary discharge does not occur. Don't be. However, even if the voltage is lower than the discharge start voltage, the wall charge may decrease due to the influence of priming and the like, an apparent dark current may flow, and the wall voltage may decrease. In particular, when the ratio (lighting rate) of the discharge cells that cause light emission to all the discharge cells is high, the time during which the address pulse voltage Vd is applied to the data electrode Dk becomes long, so the time during which the dark current flows also becomes long. In order to suppress this decrease in wall charge, it is necessary to reduce the dark current itself. For this purpose, the voltage between the data electrode Dk and the scan electrode SCi when only the address pulse voltage Vd or only the scan pulse voltage Va is applied is lower than the discharge start voltage (hereinafter referred to as “ Stable undischarged voltage ”).

  From such a viewpoint, the value of the address pulse voltage Vd applied to the data electrode Dk and the value of the scan pulse voltage Va applied to the scan electrode SCi are set. However, the present inventors have found that the above-described stable discharge voltage and stable undischarged voltage are not constant but differ from subfield to subfield. When there are multiple subfields and the discharge probability is different in each subfield, the stable discharge voltage and the stable undischarged voltage are lower in the subfield where address discharge is likely to occur than in the subfield where address discharge is unlikely to occur. .

  In the present embodiment, since the priming associated with the all-cell initialization discharge remains in the address period of the first SF in which the all-cell initialization operation is performed, the second SF to the tenth SF in which the selective initialization operation is performed, The stable discharge voltage and the stable undischarge voltage tend to be low. In such a case, it is possible to absorb the difference between the stable discharge voltage and the stable undischarge voltage for each subfield by setting the scan pulse voltage Va and the address pulse voltage Vd high.

  However, in the present embodiment, in the first SF initialization period in which the address discharge is likely to occur, the voltage Vi4L having the lowest ramp waveform voltage applied to the scan electrode SCi is initialized to the second SF to the tenth SF in which the address discharge is less likely to occur. The voltage Ve2L applied to the sustain electrode SUi in the address period of the first SF in which the address discharge is likely to occur is set to be lower than the lowest voltage Vi4H of the falling ramp waveform voltage applied to the scan electrode SCi in the period. The voltage is set to be lower than the voltage Ve2H applied to the sustain electrode SUi in the writing period of the second SF to the tenth SF, which is unlikely to occur. By driving in this way, the strength of the address discharge in the first SF is weakened. Therefore, the likelihood of the address discharge due to the effect of priming can be offset, and the stable discharge voltage and stability in the first SF to the tenth SF can be compensated. Undischarged voltages can be substantially equalized, and stable address discharge can be generated without increasing the scan pulse voltage Va and address pulse voltage Vd.

  In the present embodiment, both the voltage Vi4L having the lowest ramp waveform voltage applied to the scan electrode SCi in the initializing period of the predetermined subfield and the voltage Ve2L applied to the sustain electrode SUi in the address period are set to a predetermined level. Although the present invention is described as being set lower than subfields other than the subfield, the present invention is not limited to this. For example, the voltage Ve2L applied to the sustain electrode SUi in the address period is lower than that of the other subfields. It may be set.

  In the present embodiment, the predetermined subfield has been described as the first SF that performs the all-cell initialization operation. However, the present invention is not limited to this, and a subfield that is susceptible to address discharge is used. It can be a predetermined subfield. Furthermore, the predetermined subfield is not limited to one, and a plurality of subfields may be used as the predetermined subfield.

  Further, the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the values appropriately according to the characteristics of the panel, the specifications of the plasma display device, and the like.

  In the present invention, the number of subfields and the luminance weight of each subfield are not limited to the above values. Furthermore, the structure which switches a subfield structure based on an image signal etc. may be sufficient.

(Embodiment 2)
The difference between the second embodiment and the first embodiment is the subfield configuration, and the drive voltage waveform corresponding to the subfield configuration. FIG. 6 is a diagram showing a subfield configuration in Embodiment 2 of the present invention.

  In the present embodiment, one field is divided into eleven subfields (first SF, second SF,..., Eleventh SF), and each subfield is, for example, (0.5, 1, 2, 3, 6, 11, 18, 30, 44, 60, 81), and the luminance magnification is 2. In the sustain period of each subfield, the number of sustain pulses obtained by multiplying the luminance weight of each subfield by the luminance magnification is applied to the display electrode pair 28. In the present embodiment, the all-cell initialization operation is performed in the initialization period of the second SF, and the selective initialization operation is performed in the initialization periods of the first SF and the third SF to the eleventh SF.

  In the present embodiment, the predetermined subfield is the second SF. That is, the lowest voltage value of the falling ramp waveform voltage applied to the scan electrode SCi in the initialization period of the second SF is the lowest voltage value of the falling ramp waveform voltage applied to the scan electrode SCi in the initialization period of the subfield other than the second SF. The voltage value is set to be lower than the low voltage value, and the voltage value applied to the sustain electrode SUi in the address period of the second SF is lower than the voltage value applied to the sustain electrode SUi in the address period of the subfield other than the second SF. Is set.

  Below, the detail of the drive voltage waveform for driving the panel 10 and its operation | movement are demonstrated. FIG. 7 is a waveform diagram of drive voltage applied to each electrode of panel 10 in the second exemplary embodiment of the present invention. FIG. 7 shows details of the driving voltage waveforms of the first SF to the third SF.

  First, the first SF having a luminance weight of 0.5 will be described.

  In the initializing period of the first SF, the same operation as the selective initializing operation of the second SF in the first embodiment is performed. That is, 0 (V) is applied to data electrodes D1 to Dm, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, and scan electrodes SC1 to SCn have a discharge start voltage lower than sustain electrodes SU1 to SUn. A downward ramp waveform voltage that gradually falls from the voltage Vi3 to the voltage Vi4H exceeding the discharge start voltage is applied.

  Then, a weak initializing discharge is generated in the discharge cell in which the sustain discharge has occurred in the sustain period of the immediately preceding subfield, and the wall voltage on each electrode is adjusted to a wall voltage suitable for the subsequent address operation. On the other hand, the discharge cells that did not cause the sustain discharge in the immediately preceding subfield are not discharged, and the wall charges at the end of the initialization period of the previous subfield are maintained.

  During the writing period of the first SF, the same operation as the writing operation of the second SF in the first embodiment is performed. That is, voltage Ve2H is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn. Next, the scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the address pulse voltage Vd is applied to the data electrode Dk of the discharge cell that should emit light in the first row among the data electrodes D1 to Dm. Wake up. The above address operation is performed until the discharge cell in the nth row of scan electrode SCn.

  In the sustain period of the first SF, positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn and 0 (V) is applied to sustain electrodes SU1 to SUn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. Exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. In the discharge cells in which no address discharge has occurred during the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained. Thus, the first SF is a subfield in which the sustain pulse for generating the sustain discharge is applied once to the display electrode pair 28 in the sustain period because the brightness weight is 0.5 and the brightness magnification is 2.

  In the present embodiment, a so-called narrow pulse voltage difference for erasing the wall voltage on scan electrode SCi and sustain electrode SUi while leaving the positive wall voltage on data electrode Dk remains is scan electrode SC1. ~ SCn and no sustain electrodes SU1 to SUn. Therefore, a negative wall voltage remains on scan electrode SCi, and a positive wall voltage remains on sustain electrode SUi. These wall voltages work to strengthen the address discharge in the address period of the next subfield.

  In the initialization period of the second SF, the same operation as the all-cell initialization operation of the first SF in the first embodiment is performed. That is, in the first half of the initialization period, 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SUn, respectively, and the scan electrodes SC1 to SCn have a discharge start voltage lower than the discharge start voltage with respect to the sustain electrodes SU1 to SUn. An upward ramp waveform voltage that gently rises from the voltage Vi1 toward the voltage Vi2 that exceeds the discharge start voltage is applied. While this ramp waveform voltage rises, a weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn.

  In the latter half of the initialization period, positive voltage Ve1 is applied to sustain electrodes SU1 to SUn, and scan electrodes SC1 to SCn receive a discharge start voltage from voltage Vi3 that is equal to or lower than the discharge start voltage with respect to sustain electrodes SU1 to SUn. A downward ramp waveform voltage that gently falls toward the exceeding voltage Vi4L is applied. Here, voltage Vi4L applied to scan electrodes SC1 to SCn is set to be lower than voltage Vi4H applied in the initialization period of the subfield other than the second SF.

  During this time, weak initializing discharges occur between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, respectively. Then, the negative wall voltage above scan electrodes SC1 to SCn and the positive wall voltage above sustain electrodes SU1 to SUn are weakened, and the positive wall voltage above data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The Thus, the all-cell initializing operation for performing the initializing discharge on all the discharge cells is completed.

  In the address period of the second SF, voltage Ve2L is applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn. Here, voltage Ve2L applied to sustain electrodes SU1 to SUn is set to be lower than voltage Ve2H applied in the address period of the subfield other than the second SF. In the present embodiment, voltage Ve2L is voltage It is set equal to Ve1.

  Then, the scan pulse voltage Va is applied to the scan electrode SC1 in the first row, and the positive address pulse voltage Vd is applied to the data electrode Dk of the discharge cell to be lit in the first row, thereby causing an address discharge. The above address operation is performed until the discharge cell in the nth row of scan electrode SCn.

  In the second SF maintenance period, the same operation as that of the first SF maintenance period in the first embodiment is performed. That is, first, sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn and 0 (V) is applied to sustain electrodes SU1 to SUn to generate a sustain discharge in the discharge cells in which the address discharge has occurred. Subsequently, 0 (V) is applied to scan electrodes SC1 to SCn and sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn, respectively, and a sustain discharge is generated again in the discharge cells that have caused the sustain discharge. Then, at the end of the sustain period, a so-called narrow pulse voltage difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and the positive wall voltage on data electrode Dk is left while scanning. The wall voltage on electrode SCi and sustain electrode SUi is erased.

  The subsequent operations from the third SF to the eleventh SF are the same as the operations from the second SF to the tenth SF in the first embodiment, and thus description thereof is omitted.

  In the present embodiment, the predetermined subfield is driven as the second SF. Since the second SF performs the all-cell initialization operation, address discharge is likely to occur. In addition, since the negative wall voltage remains on scan electrode SCi and the positive wall voltage remains on sustain electrode SUi in the sustain period of the first SF, the address discharge is further enhanced by this wall voltage.

  Therefore, in the present embodiment, voltage Vi4L having the lowest ramp waveform voltage applied to scan electrode SCi is set lower than voltage Vi4H in the other subfields in the initialization period of the second SF that is a predetermined subfield. At the same time, the voltage Ve2L applied to the sustain electrode SUi in the address period of the second SF is set lower than the voltage Ve2H of the other subfields. By driving in this way, the effect of offsetting the susceptibility of address discharge due to the effect of priming and the residual wall voltage in the sustain period of the first SF becomes greater, and the stable discharge voltage in the first SF to the eleventh SF, Stable undischarged voltages can be substantially aligned, and stable address discharge can be generated without increasing the scan pulse voltage Va and address pulse voltage Vd.

  The panel driving method of the present invention generates a stable address discharge without increasing the voltage necessary for generating the address discharge, even for a large screen / high brightness panel, and produces an image with good display quality. Since it can be displayed, it is useful as a driving method for a panel used in a wall-mounted television or a large monitor.

The disassembled perspective view which shows the structure of the panel in Embodiment 1 of this invention. Electrode arrangement of the panel Circuit block diagram of plasma display device according to Embodiment 1 of the present invention The figure which shows the subfield structure in Embodiment 1 of this invention. Drive voltage waveform diagram applied to each electrode of panel in embodiment 1 of the present invention The figure which shows the subfield structure in Embodiment 2 of this invention. Drive voltage waveform diagram applied to each electrode of the panel in the second embodiment of the present invention

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Plasma display apparatus 10 Panel 21 Front plate 22 Scan electrode 23 Sustain electrode 24,33 Dielectric layer 25 Protective layer 28 Display electrode pair 31 Back plate 32 Data electrode 34 Partition 35 Phosphor layer 51 Image signal processing circuit 52 Data electrode drive circuit 53 Scan Electrode Drive Circuit 54 Sustain Electrode Drive Circuit 55 Timing Generation Circuit

Claims (2)

A method of driving a plasma display panel in which a discharge cell is formed at an intersection between a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode,
An initialization period in which a slowly decreasing ramp waveform voltage is applied to the scan electrode, an address period in which an address discharge is selectively generated in the discharge cells, and a luminance weight in accordance with the luminance weight in the discharge cells in which the address discharge is generated A plurality of subfields having a sustain period for generating a number of sustain discharges in one field period;
Among the plurality of subfields, the voltage value applied to the sustain electrode in the write period of a predetermined subfield is lower than the voltage value applied to the sustain electrode in the write period of a subfield other than the predetermined subfield. Set as
The lowest voltage value of the gradually decreasing ramp waveform voltage in the initialization period of the predetermined subfield is the lowest voltage value of the gently decreasing ramp waveform voltage in the initialization period of the subfield other than the predetermined subfield. The voltage difference between the scan electrode and the sustain electrode at the time when the slowly decreasing ramp waveform voltage is the lowest is a subfield other than the predetermined subfield than the predetermined subfield. The plasma display is configured to be driven to be smaller, to perform an all-cell initialization operation in the predetermined subfield, and to perform a selective initialization operation in subfields other than the predetermined subfield. Panel drive method. The method of claim 1, wherein the predetermined subfield is a subfield subsequent to a subfield that generates a sustain discharge once in a sustain period.

Images