JP2011158871A - Method for driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To generate a stable writing discharge while securing a sufficient voltage setting margin to obtain an image of high display quality. <P>SOLUTION: This method for driving a plasma display panel is provided with a plurality of discharge cells each having a scanning electrode, a maintenance electrode and a data electrode. In an initialization period, either a compulsory initializing operation which generates an initialization discharge regardless of an operation of an immediately-previous subfield, or a selection initializing operation which generates the initialization discharge only by the discharge cells which have generated writing discharges in an immediately-previous writing period is executed. First voltages are applied to the maintenance electrodes, ascending slope waveform voltages are applied to the scanning electrodes, and descending slope waveform voltages are then applied to the scanning electrodes. After that, positive rectangular voltages are applied to the scanning electrodes, and the descending slope waveform voltages are then applied to the scanning electrodes, and then second voltages higher than the first voltages are applied to the maintenance electrodes, and the descending slope waveform voltages are applied to the scanning electrodes to conduct the selection initializing operation. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a method for driving a plasma display panel.

  An AC surface discharge type plasma display panel (hereinafter abbreviated as “panel”) includes a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, and is red with ultraviolet rays generated by gas discharge in the discharge cell. Color display is performed by exciting and emitting phosphors of green and blue colors.

  As a method for driving the panel, a subfield method, that is, a method in which a single field is formed using a plurality of subfields having an initialization period, an address period, and a sustain period, and gradation display is performed by combining subfields that emit light. Is common. An initialization operation is performed during the initialization period of each subfield, a write operation is performed during the write period, and a maintenance operation is performed during the sustain period. The initialization operation is an operation that generates initialization discharge and forms wall charges necessary for the subsequent address operation. The initializing operation includes a forced initializing operation that generates an initializing discharge regardless of the operation of the immediately preceding subfield, and a selective initializing that generates an initializing discharge only in the discharge cells that have performed address discharge in the immediately preceding subfield. There is movement. The address operation is an operation in which an address discharge is selectively generated in the discharge cells in accordance with an image to be displayed to form wall charges, and the sustain operation is to generate a sustain discharge by alternately applying a sustain pulse to the display electrode pair, This is an operation of causing the phosphor layer of the corresponding discharge cell to emit light.

  There is a driving method that improves the contrast by lowering the luminance (hereinafter abbreviated as “black luminance”) when displaying black, which is the lowest gradation among the subfield methods, and reducing light emission not related to gradation display as much as possible. It is being considered. For example, Patent Document 1 discloses a driving method in which one subfield for performing a forced initializing operation is set for one field, and the subfields for performing a selective initializing operation are used for the other subfields.

  Patent Document 2 discloses a driving method in which an upward ramp waveform voltage is applied to the scan electrode at the end of the sustain period, and a downward ramp waveform voltage is applied to the scan electrode in the next initialization period to perform a selective initialization operation. It is disclosed.

JP 2000-242224 A JP 2008-256774 A

  As described in Patent Document 2, when a ramp waveform voltage is used as a drive voltage waveform, waveform distortion such as ringing can be suppressed, so that the drive voltage waveform can be accurately applied to each electrode of each discharge cell. For this reason, when the ramp waveform voltage is used as the drive voltage in the initialization period, a stable address discharge can be generated in the next address period. However, the discharge using the ramp waveform voltage is a weak discharge, and the voltage range that can be applied to each electrode to perform the selective initialization operation is limited. There was a problem that it was difficult to generate a discharge sufficient for erasing. For this reason, there is a problem in that the driving conditions of the discharge cells that have performed the address discharge in the immediately preceding subfield and the discharge cells that have not performed the address discharge are different, resulting in a narrow voltage setting margin of the driving voltage waveform.

  The present invention has been made in view of the above problems, and provides a panel driving method capable of generating a stable address discharge while ensuring a sufficient voltage setting margin and displaying an image with high display quality. For the purpose.

  To achieve the above object, according to the present invention, a discharge cell having a scan electrode, a sustain electrode, and a data electrode is formed by using a plurality of subfields having an initialization period, an address period, and a sustain period. A driving method of a plasma display panel for driving a plurality of plasma display panels, wherein the initializing period includes a forced initializing operation for generating an initializing discharge regardless of an immediately preceding subfield operation, and an immediately preceding address period. The selective initializing operation is performed to generate the initializing discharge only in the discharge cell in which the address discharge is generated, and the selective initializing operation applies the first voltage to the sustain electrode and the scan electrode. And then applying a ramp waveform voltage to the scan electrode, and then applying a positive rectangular voltage to the scan electrode And then applying a downward ramp waveform voltage to the scan electrode, then applying a second voltage higher than the first voltage to the sustain electrode and applying a downward ramp waveform voltage to the scan electrode It is performed.

  According to the present invention, an image with high display quality can be displayed by generating a stable address discharge while ensuring a sufficient voltage setting margin in the panel.

The exploded perspective view of the panel used for the plasma display apparatus in an embodiment of the invention Panel arrangement of panels used in the plasma display device Drive voltage waveform diagram applied to each electrode of the panel used in the plasma display device (A) is a diagram showing a voltage setting range which is a pulse peak value of a sustain pulse, and (B) is a diagram showing a voltage setting range which is a pulse peak value of an address pulse. Circuit block diagram of the plasma display device Circuit diagram of scan electrode driving circuit of same plasma display device Circuit diagram of sustain electrode drive circuit of the plasma display device

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

  FIG. 1 is an exploded perspective view of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. The protective layer 26 is formed using magnesium oxide, which is a material having high electron emission performance, in order to easily generate discharge. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the exemplary embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi (i = 1 to n) intersects with one data electrode Dj (j = 1 to m). , M × n discharge cells are formed in the discharge space.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described. The plasma display apparatus displays an image by subfield method, that is, by dividing one field into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield.

  Each subfield has an initialization period, an address period, and a sustain period. In the initialization period, the history of wall charges of the previous discharge cells is erased, and an initialization operation is performed to form wall charges necessary for the subsequent address discharge on each electrode. In the address period, an address discharge is selectively generated in the discharge cells to emit light to perform an address operation for forming wall charges. In the sustain period, sustain pulses of the number corresponding to the luminance weight determined in advance for each subfield are alternately applied to the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell that has generated the address discharge to emit light. Perform maintenance operation. Note that the maintenance period may be omitted in order to keep the emission luminance low.

  As a subfield configuration, for example, one field is divided into 10 subfields (SF1, SF2,..., SF10), and each subfield is (1, 2, 3, 6, 11, 18, 30). , 44, 60, 80). Then, the forced initializing operation is performed in the initializing period of the subfield SF1, and the selective initializing operation is performed in the initializing period of the subfields SF2 to SF10. However, the present invention is not limited to the subfield configuration such as the number of subfields and the luminance weight.

  FIG. 3 is a waveform diagram of driving voltage applied to each electrode of the plasma display device in accordance with the exemplary embodiment of the present invention.

  In the initialization period of subfield SF1, voltage 0 (V) is first applied to data electrodes D1 to Dm, and voltage 0 (V) is also applied to sustain electrodes SU1 to SUn. Then, an upward ramp waveform voltage that gently rises from voltage Vi1 equal to or lower than the discharge start voltage to sustain electrodes SU1 to SUn toward voltage Vi2 exceeding the discharge start voltage is applied to scan electrodes SC1 to SCn. Then, weak initialization discharges occur between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm, respectively, and negative walls are formed on scan electrodes SC1 to SCn. A voltage is accumulated and a positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  Next, voltage Ve is applied to sustain electrodes SU1 to SUn, and a downward ramp waveform voltage that gently decreases from voltage Vi3 to voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, a weak initializing discharge occurs again, and the wall voltages on scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn are weakened. In addition, an excessive portion of the wall voltage of the data electrodes D1 to Dm is discharged and adjusted to a wall voltage suitable for an address operation. In this way, the forced initializing operation in which the initializing discharge is generated in all the discharge cells is completed.

  In the address period of subfield SF1, voltage 0 (V) is continuously applied to data electrodes D1 to Dm, voltage Ve is continuously applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn.

  Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 exceeds the discharge start voltage by adding the positive wall voltage on the data electrode Dk to the difference (Vd−Va) of the externally applied voltage. Then, a discharge is generated between data electrode Dk and scan electrode SC1, and this is extended to a discharge between scan electrode SC1 and sustain electrode SU1 to generate an address discharge. A positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection between the data electrode to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur.

  Next, a scan pulse is applied to scan electrode SC2 in the second row, and an address pulse is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, an address discharge occurs between data electrode Dk and scan electrode SC2 and between sustain electrode SU2 and scan electrode SC2, a positive wall voltage is accumulated on scan electrode SC2, and a negative wall voltage is applied on sustain electrode SU2. And a negative wall voltage is also accumulated on the data electrode Dk. In this manner, an address operation is performed in which an address discharge is caused in the discharge cell to be lit in the second row and wall voltage is accumulated on each electrode. On the other hand, since the voltage at the intersection between the data electrode to which the address pulse is not applied and scan electrode SC2 does not exceed the discharge start voltage, the address discharge does not occur.

  Thereafter, the same address operation is performed until the scan electrode SCn in the n-th row, and wall charges necessary for the subsequent sustain discharge are formed.

  In the sustain period of subfield SF1, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and a sustain pulse of voltage Vs is applied to scan electrodes SC1 to SCn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the voltage Vs plus the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. The discharge start voltage between scan electrode SCi and sustain electrode SUi is exceeded. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. On the other hand, the sustain discharge does not occur in the discharge cells in which the address discharge has not occurred, and the wall voltage at the end of the initialization operation is maintained.

  Subsequently, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and a sustain pulse of voltage Vs is applied to sustain electrodes SU1 to SUn. Then, the sustain discharge occurs again in the discharge cell in which the sustain discharge has occurred, and the phosphor layer 35 emits light. Then, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi.

  Thereafter, similarly, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and sustain discharge is continuously generated in the discharge cells in which the address discharge has occurred.

  In the subsequent initializing period of subfield SF2, voltage 0 (V), which is the first voltage, is applied to sustain electrodes SU1 to SUn and scan electrodes SC1 to SCn are gradually increased from voltage 0 (V) to positive voltage Vr. Ascending ramp waveform voltage is applied. In the present embodiment, the voltage Vr is set to the same voltage as the voltage Vs. Then, in a discharge cell that has undergone a sustain discharge (a discharge cell that has undergone an address discharge when the sustain period is omitted), a first weak erase discharge is generated with scan electrode SCi as an anode and sustain electrode SUi as a cathode. . Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened.

  Next, with the voltage 0 (V) being applied to sustain electrodes SU1 to SUn, a downward ramp waveform voltage that gently decreases from voltage 0 (V) toward negative voltage Vi4 is applied to scan electrodes SC1 to SCn. . Then, a weak discharge is generated again in the discharge cell that has generated a weak erasing discharge. The weak discharge at this time is the first discharge with the scanning electrode as the cathode and the data electrode as the anode. The voltage Vi4 is set to be equal to or slightly higher than the voltage Va of the scanning pulse.

  Thereafter, a rectangular voltage of voltage Vr is applied to scan electrodes SC1 to SCn for time Te. Then, a third discharge is generated in the discharge cell in which the weak erasing discharge is generated. The discharge at this time is a second discharge in which the scan electrode is the anode and the sustain electrode is the cathode, and is a weak discharge.

  Thereafter, with the voltage 0 (V) being applied to sustain electrodes SU1 to SUn, a downward ramp waveform voltage that gently falls from voltage 0 (V) toward voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, a fourth discharge is generated in the discharge cell in which the weak erasing discharge is generated. The discharge at this time is a weak discharge, and this weak discharge is the second discharge using the scan electrode as the cathode and the data electrode as the anode. The voltage Vi4 is set to be equal to or slightly higher than the voltage Va of the scanning pulse.

  After that, voltage Ve, which is a second voltage higher than the first voltage, is applied to sustain electrodes SU1 to SUn, and gradually decreases from voltage 0 (V) to voltage Vi4 to scan electrodes SC1 to SCn. Apply a falling ramp waveform voltage. Then, a fifth discharge is generated in the discharge cell that generated the discharge. The discharge at this time is the third discharge with the scanning electrode as the cathode and the data electrode as the anode. Due to this weak discharge, excessive portions of the wall voltage on scan electrode SCi, sustain electrode SUi, and data electrode Dk are discharged and adjusted to a wall voltage suitable for the address operation. In this way, the initialization operation is completed.

  The subsequent operation in the address period of subfield SF2 is the same as the operation in the address period of subfield SF1, and the operation in the sustain period of subfield SF2 is the same as the operation in the sustain period of subfield SF1 except for the number of sustain pulses. . The operations in subfields SF3 to SF10 are the same as those in subfield SF2 except for the number of sustain pulses.

  In this embodiment, the voltage Vi1 is 200 (V), the voltage Vi2 is 400 (V), the voltage Vi3 is 200 (V), the voltage Vi4 is -180 (V), and the voltage Vc is -55 (V). The voltage Va is -200 (V), the voltage Vs is 200 (V), the voltage Vr is 200 (V), the voltage Ve is 150 (V), and the voltage Vd is 60 (V). The time Te is 50 μs. However, these voltage values are not limited to the values described above, and are desirably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.

  Thus, in the present embodiment, in the initialization period, a first discharge is generated with the sustain electrode SUi as the cathode and the scan electrode SCi as the anode, and then the scan electrode SCi as the cathode and the data electrode Dj as the anode. The first discharge is generated, and then the second discharge is generated with the sustain electrode SUi as the cathode and the scan electrode SCi as the anode, and then the second discharge with the scan electrode SCi as the cathode and the data electrode Dj as the anode. Then, a third discharge is generated with the scan electrode SCi as a cathode and the data electrode Dj as an anode. Further, in order to make these discharges weak and suppress the light emission associated therewith, a first voltage 0 (V) is applied to the sustain electrodes SU1 to SUn and an upward ramp waveform voltage is applied to the scan electrodes SC1 to SCn. Then, a downward ramp waveform voltage is applied to scan electrodes SC1 to SCn, then a positive rectangular voltage is applied to scan electrodes SC1 to SCn, and then a downward ramp waveform voltage is applied to scan electrodes SC1 to SCn. Thereafter, voltage Ve, which is a second voltage higher than the first voltage, is applied to sustain electrodes SU1 to SUn, and a downward ramp waveform voltage is applied to scan electrodes SC1 to SCn.

  In this way, it is possible to accumulate a sufficient wall voltage on each electrode by repeatedly generating a weak discharge a plurality of times without generating a strong discharge, and to stably generate a subsequent address discharge. it can.

  FIG. 4 shows the experimental results of measuring the voltage setting margin according to the conventional driving method described in Patent Document 2 and the voltage setting margin according to the driving method in the present embodiment, and FIG. FIG. 4B shows a setting range of the voltage Vd which is the pulse peak value of the write pulse, and FIG. 4B shows a setting range of the voltage Vd which is the pulse peak value of the writing pulse.

  As shown in FIG. 4A, the setting range of the voltage Vs by the conventional driving method is 170 (V) to 183 (V), and the setting range of the voltage Vs by the driving method in the present embodiment is 170 (V). ) To 210 (V). As described above, according to the driving method of the present embodiment, it can be seen that the voltage setting margin is greatly expanded as compared with the conventional driving method.

  The reason why the driving margin is widened by the driving method in the present embodiment can be considered as follows, for example. After a sustain pulse is applied to the display electrode pair in the sustain period, an upward ramp waveform voltage that rises to the voltage Vr is applied to the scan electrode to generate an erase discharge. At this time, in order to generate the erasure discharge only in the discharge cells in which the sustain discharge has occurred, the voltage Vr cannot be set very high and must be the same level as the voltage Vs. The wall voltage cannot be completely erased by the discharge at that time, and the wall charges accumulated by the sustain discharge remain. According to the conventional driving method, since the remaining wall voltage is added to the sustain pulse, even if the discharge cell does not perform the address operation in the address period following the selective initialization operation, the sustain discharge is performed in the subsequent sustain period. Is likely to occur. Therefore, the voltage Vs cannot be set high.

  However, according to the driving method of the present embodiment, after a sustain pulse is applied to the display electrode pair in the sustain period, the discharge using the sustain electrode as the cathode and the scan electrode as the anode is performed twice, and the scan electrode as the cathode and the data electrode Is generated three times. Therefore, the wall charges accumulated in the sustain discharge are erased without remaining, and there is no possibility that the sustain discharge occurs in the discharge cells that have not performed the address operation in the address period, and the voltage Vs can be set high.

  Further, as shown in FIG. 4B, the lower limit of the setting range of the voltage Vd by the conventional driving method is 58 (V), and the lower limit of the setting range of the voltage Vd by the driving method in this embodiment is the time It is 55 (V) when Te = 40 μs, and 52 (V) when time Te = 55 μs. As described above, according to the driving method in the present embodiment, it can be seen that the voltage setting margin of the voltage Vd is widened as compared with the conventional driving method.

  As described above, according to the panel driving method in the embodiment of the present invention, the voltage setting margin of the voltage Vs and the voltage Vd can be widened as compared with the conventional panel driving method. In addition to the above, the voltage setting margin can be expanded for the pulse peak value of the scanning pulse and the like. Note that the setting range of the voltage Vd and the setting range of the pulse peak value of the scanning pulse are dependent on the time Te for applying the rectangular voltage of the voltage Vr to the scanning electrodes, and the voltage setting margin tends to increase as the time Te is set longer. There is. However, in practice, a sufficient voltage setting margin can be secured by setting the time Te to about 50 μs.

  Next, a drive circuit for driving the panel 10 will be described. FIG. 5 is a circuit block diagram of plasma display device 40 in accordance with the exemplary embodiment of the present invention. The plasma display device 40 includes the panel 10 and its drive circuit. The drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and each of them. A power supply circuit (not shown) for supplying necessary power to the circuit block is provided.

  The image signal processing circuit 41 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode driving circuit 42 converts the image data for each subfield into address pulses corresponding to the data electrodes D1 to Dm, and applies them to the data electrodes D1 to Dm. The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal H and the vertical synchronization signal V, and supplies them to the respective circuit blocks. Scan electrode drive circuit 43 generates the drive voltage waveform described above based on the timing signal and applies it to each of scan electrodes SC1 to SCn. Sustain electrode drive circuit 44 generates the drive voltage waveform described above based on the timing signal and applies it to sustain electrodes SU1 to SUn.

  FIG. 6 is a circuit diagram of scan electrode drive circuit 43 of plasma display device 40 in accordance with the exemplary embodiment of the present invention. Scan electrode drive circuit 43 includes sustain pulse generation circuit 50, ramp waveform voltage generation circuit 60, and scan pulse generation circuit 70.

  Sustain pulse generation circuit 50 includes power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59, and generates sustain pulses to be applied to scan electrodes SC1 to SCn. The power recovery circuit 51 recovers and reuses power when driving the scan electrodes SC1 to SCn. Switching element Q55 clamps scan electrodes SC1 to SCn to voltage Vs, and switching element Q56 clamps scan electrodes SC1 to SCn to voltage 0 (V). The switching element Q59 is a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

  Scan pulse generating circuit 70 includes switching elements Q71H1 to Q71Hn, Q71L1 to Q71Ln, and switching element Q72. Then, a scan pulse is generated based on the power source of voltage Va and the power source E71 of voltage (Vc−Va) superimposed on the reference potential (potential of node A shown in FIG. 6) of scan pulse generating circuit 70, A scan pulse is sequentially applied to each of scan electrodes SC1 to SCn at the timing shown in FIG. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 50 as it is during the sustain operation. That is, the voltage at node A is output to scan electrodes SC1 to SCn.

  The ramp waveform voltage generating circuit 60 includes Miller integrating circuits 61, 62, and 63, and generates the ramp waveform voltage shown in FIG. Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61. By applying a constant voltage to input terminal IN61, Miller integrating circuit 61 generates an upward ramp waveform voltage that gradually rises toward voltage Vi2. Miller integrating circuit 62 includes transistor Q62, capacitor C62, resistor R62, and diode D62 for preventing backflow, and by applying a constant voltage to input terminal IN62, it rises gently toward voltage Vr. Generate waveform voltage. Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63, and applies a constant voltage to input terminal IN63 to generate a downward ramp waveform voltage that gradually decreases toward voltage Vi4. The switching element Q69 is also a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode drive circuit 43.

  In addition, these switching elements and transistors can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the switching elements and transistors generated by the timing generation circuit 45.

  FIG. 7 is a circuit diagram of sustain electrode drive circuit 44 of plasma display device 40 in accordance with the exemplary embodiment of the present invention. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 80 and constant voltage generation circuit 85.

  Sustain pulse generation circuit 80 includes power recovery circuit 81, switching element Q83, and switching element Q84, and generates sustain pulses to be applied to sustain electrodes SU1 to SUn. The power recovery circuit 81 recovers and reuses power when driving the sustain electrodes SU1 to SUn. Switching element Q83 clamps sustain electrodes SU1 to SUn to voltage Vs, and switching element Q84 clamps sustain electrodes SU1 to SUn to voltage 0 (V).

  Constant voltage generation circuit 85 has switching elements Q86 and Q87, and applies voltage Ve to sustain electrodes SU1 to SUn.

  In addition, these switching elements can also be comprised using generally known elements, such as MOSFET and IGBT. These switching elements are also controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 45.

  Drive voltage waveforms applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn in the initializing period of subfield SF2 using scan electrode drive circuit 43 shown in FIG. 6 and sustain electrode drive circuit 44 shown in FIG. A method for generating the error will be described. It is assumed here that the voltage Vr is set to the same voltage as the voltage Vs.

  To apply voltage 0 (V) to sustain electrodes SU1 to SUn, switching element Q84 is turned on. In order to apply an upward ramp waveform voltage that gradually rises to voltage Vr to scan electrodes SC1 to SCn, switching elements Q71L1 to Q71Ln and switching element Q69 are turned on, and a voltage is applied to input terminal IN62 to set Miller integrating circuit 62. Make it work.

  Next, in order to apply a downward ramp waveform voltage that gradually decreases from voltage 0 (V) to voltage Vi4 to scan electrodes SC1 to SCn, transistor Q62 of Miller integrating circuit 62 is turned off and switching element Q56 is turned on. Then, voltage 0 (V) is applied to scan electrodes SC1 to SCn. Then, the switching elements Q56 and Q69 are turned off, and a voltage is applied to the input terminal IN63 to operate the Miller integrating circuit 63.

  Thereafter, to apply a rectangular voltage Vr to scan electrodes SC1 to SCn, transistor Q63 of Miller integrating circuit 63 is turned off, and switching elements Q69, Q59, and Q55 are turned on.

  Thereafter, in order to apply a downward ramp waveform voltage that gradually decreases from voltage 0 (V) to voltage Vi4 to scan electrodes SC1 to SCn, transistor Q62 of Miller integrating circuit 62 is turned off and switching element Q56 is turned on. Then, voltage 0 (V) is applied to scan electrodes SC1 to SCn. Then, the switching elements Q56 and Q69 are turned off, and a voltage is applied to the input terminal IN63 to operate the Miller integrating circuit 63.

  Thereafter, in order to apply voltage Ve to sustain electrodes SU1 to SUn, switching element Q84 is turned off and switching elements Q86 and Q87 are turned on.

  In order to apply a downward ramp waveform voltage that gradually decreases from voltage 0 (V) to voltage Vi4 to scan electrodes SC1 to SCn, transistor Q62 of Miller integrating circuit 62 is turned off, switching element Q56 is turned on, Voltage 0 (V) is applied to scan electrodes SC1 to SCn. Then, the switching elements Q56 and Q69 are turned off, and a voltage is applied to the input terminal IN63 to operate the Miller integrating circuit 63.

  Note that switching elements Q86 and Q87 of sustain electrode drive circuit 44 may be turned off immediately before scan electrodes SC1 to SCn reach voltage Vi4, and sustain electrodes SU1 to SUn may be in a high impedance state. By driving in this way, the subsequent write operation can be generated more stably. FIG. 3 shows such a driving voltage waveform.

  In this way, the drive voltage waveform of the panel shown in FIG. 3 can be generated. However, the drive circuits shown in FIGS. 5 to 7 are examples, and the present invention is not limited to the circuit configurations of these drive circuits.

  The specific numerical values and the like shown in the embodiments are merely examples, and it is desirable to set them optimally according to the panel characteristics, the specifications of the plasma display device, and the like.

  INDUSTRIAL APPLICABILITY The present invention is useful as a panel driving method because an image with high display quality can be displayed by generating a stable address discharge while ensuring a sufficient voltage setting margin.

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 40 Plasma display apparatus 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50, 80 Sustain pulse generation circuit 51, 81 Power recovery circuit 60 Ramp waveform voltage generation circuit 61, 62, 63 Miller integration circuit 70 Scan pulse generation circuit 85 Constant voltage generation circuit

Claims (3)

A plasma display for driving a plasma display panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, with a plurality of subfields having an initialization period, an address period, and a sustain period. A panel driving method,
In the initializing period, a forced initializing operation that generates an initializing discharge regardless of the operation of the immediately preceding subfield, and a selective initializing that generates an initializing discharge only in a discharge cell that has generated an address discharge in the immediately preceding address period Do one of the actions,
In the selective initialization operation, a first voltage is applied to the sustain electrode, an ascending ramp waveform voltage is applied to the scan electrode, and then a descending ramp waveform voltage is applied to the scan electrode, and then the scan is performed. A positive rectangular voltage is applied to the electrode, a downward ramp waveform voltage is then applied to the scan electrode, and then a second voltage higher than the first voltage is applied to the sustain electrode and the scan electrode is applied A method of driving a plasma display panel, which is performed by applying a downward ramp waveform voltage. The method of claim 1, wherein the rising ramp waveform voltage rises toward a positive voltage, and the falling ramp waveform voltage falls toward a negative voltage. A plasma display for driving a plasma display panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, with a plurality of subfields having an initialization period, an address period, and a sustain period. A panel driving method,
In the initializing period, a forced initializing operation that generates an initializing discharge regardless of the operation of the immediately preceding subfield, and a selective initializing that generates an initializing discharge only in a discharge cell that has generated an address discharge in the immediately preceding address period Do one of the actions,
The selective initializing operation generates a first discharge using the sustain electrode as a cathode and the scan electrode as an anode, and then generating a first discharge using the scan electrode as a cathode and the data electrode as an anode. Then, a second discharge is generated using the sustain electrode as a cathode and the scan electrode as an anode, and then a second discharge is generated using the scan electrode as a cathode and the data electrode as an anode. A method for driving a plasma display panel, comprising performing a third discharge with a scanning electrode as a cathode and the data electrode as an anode.

Images