JP2010266648A - Driving method of plasma display panel, and plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To display an image of high contrast and high image display quality by reducing black luminance and luminance of gradation being lower next to black. <P>SOLUTION: In a driving method of a plasma display panel, one field includes a first sub-fields SF2 to SF11 in which rising tilt waveform voltage rising to first voltage Vr1 is applied to a scanning electrode after a maintenance pulse is applied to a scanning electrode and a maintenance electrode in a maintenance period and second sub-field SF1 in which rising tilt waveform voltage rising to second voltage Yr2 being higher than the first voltage Yr1 is applied to the scanning electrode without applying the maintenance pulse to the scanning electrode and the maintenance electrode in the maintenance period, also the one field includes a field in which the sub-field SF2 having an initialization period in which selection initialization operation causing initialization discharge by only a discharge cell causing writing discharge in immediately preceding sub-field is arranged next to the second sub-field SF1. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an AC surface discharge type plasma display panel driving method and a plasma display apparatus.

  A plasma display panel (hereinafter abbreviated as “panel”) includes a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode. Red, green, and blue light are generated by ultraviolet rays generated by gas discharge in the discharge cell. Color display is performed by exciting and emitting phosphors of each color.

  As a method for driving the panel, a subfield method, that is, a method in which a single field is formed using a plurality of subfields having an initialization period, an address period, and a sustain period, and gradation display is performed by combining subfields that emit light. Is common. An initialization operation is performed during the initialization period of each subfield, a write operation is performed during the write period, and a maintenance operation is performed during the sustain period. The initialization operation is an operation that generates initialization discharge and forms wall charges necessary for the subsequent address operation. The initializing operation includes a forced initializing operation that generates an initializing discharge regardless of the operation of the immediately preceding subfield, and a selective initializing operation that generates an initializing discharge in a discharge cell that has performed an address discharge in the immediately preceding subfield. There is. The address operation is an operation in which an address discharge is selectively generated in the discharge cells in accordance with an image to be displayed to form wall charges, and the sustain operation is to generate a sustain discharge by alternately applying a sustain pulse to the display electrode pair, This is an operation of causing the phosphor layer of the corresponding discharge cell to emit light.

  There is a driving method that improves the contrast by lowering the luminance (hereinafter abbreviated as “black luminance”) when displaying black, which is the lowest gradation among the subfield methods, and reducing light emission not related to gradation display as much as possible. It is being considered. For example, Patent Document 1 discloses a driving method in which the forced initialization operation is performed once per field and the forced initialization operation is performed using a slowly changing ramp waveform voltage.

  Further, in Patent Document 2, the display electrode pair is divided into n, the number of times of forced initialization operation is set to once per n fields, light emission not related to gradation display is further reduced, black luminance is further reduced, and contrast is further increased. An improved driving method is disclosed.

JP 2000-242224 A JP 2006-091295 A

  However, when the black luminance, which is the lowest gradation, is reduced, the luminance difference between the black luminance and the luminance of the next lowest gradation increases, and the continuity of displayable luminance is impaired, particularly in dark images. There was a problem that the image display quality deteriorated.

  The present invention has been made in view of these problems, and a panel driving method capable of displaying an image with high contrast and high image display quality by reducing black luminance and luminance of the next lowest gradation after black, and An object is to provide a plasma display device.

  To achieve the above object, according to the present invention, a discharge cell having a scan electrode, a sustain electrode, and a data electrode is formed by using a plurality of subfields having an initialization period, an address period, and a sustain period. A panel driving method for driving a plurality of panels, wherein one field rises to a first voltage after applying a sustain pulse for causing discharge in a discharge cell to a scan electrode and a sustain electrode in a sustain period A first subfield for applying an up-slope waveform voltage to the scan electrode, and an up-slope waveform that rises to a second voltage higher than the first voltage without applying a sustain pulse to the scan electrode and the sustain electrode in the sustain period And a second subfield for applying a voltage to the scan electrode, and an address discharge is generated in the immediately preceding subfield after the second subfield. The discharge cell only contains the field of arranging the sub-field having a setup period in which the selective initializing operation for causing an initializing discharge, characterized was. By this method, it is possible to provide a panel driving method capable of reducing the black luminance and the luminance of the second lowest gradation after black and capable of displaying an image with high contrast and high image display quality.

  According to the panel driving method of the present invention, the discharge cell is forcibly initialized only during the initialization period of one subfield of a plurality of consecutive fields. Is desirable.

  The panel driving method according to the present invention also applies a rising ramp waveform voltage that rises to a predetermined voltage at which an initializing discharge is generated in an initializing period of a subfield next to the second subfield, and then applies a falling ramp to the scan electrode. A discharge cell that applies a waveform voltage to the scan electrode to perform a forced initialization operation, and an up-gradient waveform voltage that rises to a voltage lower than the predetermined voltage in the initialization period of the subfield next to the second subfield. It may include a field in which a discharge cell that performs a selective initializing operation by applying a downward ramp waveform voltage to the scan electrode after being applied to the scan electrode may be included.

  In addition, the present invention constitutes one field using a panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, and a plurality of subfields having an initialization period, an address period, and a sustain period. And a driving circuit for generating a driving voltage waveform and applying the driving voltage waveform to each electrode of the panel, wherein the driving circuit has a sustain pulse for causing a discharge to occur in the scan cell and the sustain electrode in the sustain period. A first subfield for applying an upward ramp waveform voltage that rises to the first voltage after applying to the scan electrode, and the first voltage without applying a sustain pulse to the scan electrode and the sustain electrode in the sustain period. One field to include a second subfield that applies a rising ramp waveform voltage that rises to a high second voltage to the scan electrode. The panel is configured to include a field in which a subfield having an initializing period in which an initializing discharge is generated only in a discharge cell in which an address discharge has been generated in the immediately preceding subfield is arranged next to the second subfield. It is characterized by being driven. With this configuration, it is possible to provide a plasma display device capable of displaying an image with high contrast and high image display quality by reducing black luminance and luminance of the next lowest gradation after black.

  According to the present invention, it is possible to provide a panel driving method and a plasma display device capable of displaying an image with high contrast and high image display quality by reducing black luminance and luminance of the next lowest gradation after black. It becomes possible.

It is a disassembled perspective view of the panel used for the plasma display apparatus in Embodiment 1 of this invention. It is an electrode array figure of the panel used for the plasma display apparatus. It is a drive voltage waveform figure applied to each electrode of the plasma display apparatus. It is a figure which shows the relationship between the scanning electrode and field which perform forced initialization operation | movement in Embodiment 1 of this invention. It is a circuit block diagram of the plasma display apparatus in Embodiment 1 of the present invention. It is a circuit diagram of the scan electrode drive circuit of the plasma display device. It is a circuit diagram of the sustain electrode drive circuit of the plasma display device. 4 is a timing chart for explaining operations of a scan electrode drive circuit and a sustain electrode drive circuit of the plasma display device. It is another drive voltage waveform figure applied to each electrode of the plasma display apparatus. It is a figure which shows the relationship between the discharge cell which performs the forced initialization operation | movement in Embodiment 2 of this invention, and a field.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. A plurality of display electrode pairs 24 each including a scanning electrode 22 and a sustaining electrode 23 are formed on a glass front substrate 21. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. The protective layer 26 is formed using magnesium oxide, which is a material having high electron emission performance, in order to easily generate discharge. A plurality of data electrodes 32 are formed on the back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front substrate 21 and the rear substrate 31 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer periphery thereof is sealed with a sealing material such as glass frit. Has been. In the discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 2 is an electrode array diagram of panel 10 used in the plasma display device in accordance with the first exemplary embodiment of the present invention. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 1) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 1) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 1) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed.

  Next, a driving voltage waveform for driving panel 10 and its operation will be described. The plasma display apparatus displays an image by subfield method, that is, by dividing one field into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. In each subfield, an initialization operation, a write operation, and a sustain operation are performed. The initialization operation is an operation in which initialization discharge is generated and wall charges necessary for subsequent address discharge are formed on each electrode. The initializing operation at this time includes a forced initializing operation in which an initializing discharge is generated in the discharge cell regardless of whether or not there is a previous discharge, and an initializing discharge only in the discharge cell that has undergone the sustain discharge in the immediately preceding subfield. And a selective initialization operation that generates The address operation is an operation in which address discharge is selectively generated in the discharge cells to emit light to form wall charges. The sustain operation is an operation in which sustain pulses of the number corresponding to the luminance weight determined in advance for each subfield are alternately applied to the display electrode pair to generate a sustain discharge in the discharge cell that has generated the address discharge. It is.

  As a subfield configuration, for example, one field is divided into 11 subfields (SF1, SF2,..., SF11), and each subfield is (1/2, 1, 2, 3, 6, 11). , 18, 30, 44, 60, 80). Here, the luminance weight of SF1 is described as “1/2”, which indicates that SF1 is a second subfield in which no sustain pulse is applied to the display electrode pair. Here, the value “½” itself has no strict meaning, and indicates that gradation display lower than the first subfields SF2 to SF11 in which the sustain pulse is applied to the display electrode pair is performed. As described above, one field includes a first subfield that applies a sustain pulse to the scan electrode and the sustain electrode in the sustain period, and a second subfield that does not apply the sustain pulse to the scan electrode and the sustain electrode in the sustain period. Including. Hereinafter, the second subfield and the first subfield are also simply referred to as “subfields”.

  In the present embodiment, the forced initialization operation or the selective initialization operation is performed in SF2, and the selective initialization operation is performed in SF1, SF3 to SF10. However, the present invention is not limited to the subfield configuration described above.

  In this embodiment, the forced initialization operation is not performed in all discharge cells in SF2, but the forced initialization operation is performed in discharge cells having a specific scan electrode, and the forced initialization operation is performed in other discharge cells. Do not do. The details of the specific scan electrode will be described later. First, an example of the drive voltage waveform will be described.

  FIG. 3 is a drive voltage waveform diagram applied to each electrode of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 3 shows drive voltage waveforms applied to scan electrode SC1, scan electrode SC2, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm, from SF1 to SF3. In FIG. 3, it is assumed that the forced initialization operation is performed in the discharge cell having scan electrode SC1, and the forced initialization operation is not performed in the discharge cell having scan electrode SC2.

  In the initialization period of SF1, voltage 0 (V) is applied to data electrodes D1 to Dm, and voltage Ve2 is applied to sustain electrodes SU1 to SUn. The voltage Ve2 is set higher than a voltage Ve1 described later. Then, a downward ramp waveform voltage that gently falls toward voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, a weak initializing discharge is generated in the discharge cell that has generated the sustain discharge in the immediately preceding subfield, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. Further, the excessive portion of the wall voltage of the data electrode Dk is discharged, and the wall voltage is adjusted to be suitable for the address operation. In this way, the selective initialization operation is completed. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the subsequent address period of SF1, voltage 0 (V) is continuously applied to data electrodes D1 to Dm, voltage Ve2 is continuously applied to sustain electrodes SU1 to SUn, and voltage Vc is applied to scan electrodes SC1 to SCn. Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 exceeds the discharge start voltage by adding the positive wall voltage on the data electrode Dk to the difference (Vd−Va) of the externally applied voltage. Then, the discharge generated between data electrode Dk and scan electrode SC1 extends between scan electrode SC1 and sustain electrode SU1, and an address discharge occurs. A positive wall voltage is accumulated on scan electrode SC1, a negative wall voltage is accumulated on sustain electrode SU1, and a negative wall voltage is also accumulated on data electrode Dk. In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection between the data electrode to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur.

  Next, a scan pulse is applied to scan electrode SC2 in the second row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, address discharge occurs between data electrode Dk and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1, positive wall voltage is accumulated on scan electrode SC1, and negative wall voltage is applied on sustain electrode SU1. And a negative wall voltage is also accumulated on the data electrode Dk. In this manner, an address operation is performed in which an address discharge is caused in the discharge cell to be lit in the second row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection between the data electrode to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur.

  Thereafter, the same addressing operation is performed until reaching the n-th scan electrode SCn, and wall charges necessary for the subsequent sustain discharge are formed.

  In the subsequent sustain period of SF1, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and scan electrode SC1 to SCn is gently supplied to second voltage Vr2 (hereinafter simply referred to as “voltage Vr2”). Apply rising ramp waveform voltage. The voltage Vr2 is set higher than a first voltage Vr1 (hereinafter simply referred to as “voltage Vr1”) described later. Then, a weak erasing discharge occurs between the scan electrode SCi and the sustain electrode SUi in the discharge cell in which the address discharge has been performed, and the phosphor layer 35 emits light due to the ultraviolet rays generated at this time. Then, the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. Further, since the voltage Vr2 is set to a voltage exceeding the discharge start voltage between the scan electrode SCi and the data electrode Dk of the discharge cell in which the address discharge has been performed, a weak discharge is also generated between the scan electrode SCi and the data electrode Dk. Occurs and a positive wall voltage is accumulated on the data electrode Dk.

  In this manner, in the sustain period of SF1, without applying a sustain pulse to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, an upward ramp waveform voltage that gradually rises toward voltage Vr2 is applied to scan electrodes SC1 to SCn. To do. In this way, since SF1 generates a weak discharge using the ramp waveform voltage following the address operation, it is possible to display a darker gradation than the subfield displaying the gradation using the sustain pulse. Thus, the maintenance operation of SF1 is completed.

  In the first half of the subsequent initialization period of SF2, voltage 0 (V) is applied to data electrodes D1 to Dm, and voltage 0 (V) is also applied to sustain electrodes SU1 to SUn. The scan electrode SC1, which is a scan electrode for applying a drive voltage waveform for performing the forced initialization operation (hereinafter abbreviated as “scan electrode for performing the forced initialization operation”), starts from the voltage Vi1 at which no discharge occurs. An upward ramp waveform voltage that gently rises to a predetermined voltage Vi2 (hereinafter simply referred to as “voltage Vi2”) at which an initializing discharge occurs regardless of the presence or absence of a previous discharge is applied. Then, weak initializing discharge occurs between scan electrode SC1 and sustain electrode SU1, and between scan electrode SC1 and data electrodes D1 to Dm, and negative wall voltage is accumulated on scan electrode SC1. A positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrode SU1. In addition, priming that shortens the discharge delay time of the address discharge also occurs.

  On the other hand, scan electrode SC2, which is a scan electrode that does not apply a drive voltage waveform for performing the forced initialization operation (hereinafter abbreviated as “scan electrode that does not perform the forced initialization operation”), has a voltage of 0 (V), An upward ramp waveform voltage that gently rises toward a voltage Vi5 lower than the voltage Vi2 is applied. In this case, however, no discharge occurs.

  In this way, in the first half of the initialization period of SF2, the scan electrode that performs the forced initialization operation has an upward ramp waveform voltage that gradually rises toward the voltage Vi2 at which discharge occurs regardless of the presence or absence of the previous discharge. Apply. Further, an upward ramp waveform voltage that gently rises toward the voltage Vi5 lower than the voltage Vi2 is applied to the scan electrode that does not perform the forced initialization operation.

  In the second half of the subsequent initialization period of SF2, voltage 0 (V) is applied to data electrodes D1 to Dm, and voltage Ve1 lower than voltage Ve2 is applied to sustain electrodes SU1 to SUn. Then, a downward ramp waveform voltage that gently falls from voltage Vi3 to voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, in the first half of the initialization period of SF2, a weak initialization discharge is generated in the discharge cell in which a weak initialization discharge is generated and in the discharge cell in which a discharge is generated in SF1 and excessive wall charges are accumulated. As a result, the wall voltage on the scan electrode and the sustain electrode of the discharge cell is weakened, and an excessive portion of the wall voltage of the data electrodes D1 to Dm is discharged and adjusted to a wall voltage suitable for the address operation. In addition, priming that shortens the discharge delay time of the address discharge also occurs. On the other hand, no discharge is generated in the discharge cells in which no discharge is caused in SF1 and no initializing discharge is generated in the first half of the initializing period in SF2, and the previous wall voltage is maintained.

  In this way, the forced initialization operation is performed in the discharge cell having the scan electrode to which the rising ramp waveform voltage rising toward the voltage Vi2 at which the discharge is generated regardless of the presence or absence of the previous discharge. On the other hand, in the discharge cell having the scan electrode to which the rising ramp waveform voltage rising toward the voltage Vi5 lower than the voltage Vi2 is applied, the forced initializing operation is not performed and the selective initializing operation is performed.

  As described above, in the present embodiment, the discharge for performing the selective initializing operation in the initializing period of subfield SF2 next to SF1 in which the rising ramp waveform voltage is applied to the scan electrode without applying the sustain pulse in the sustain period. There are a mixture of cells and discharge cells that perform a forced initialization operation. The discharge cell that performs the forced initializing operation applies a rising ramp waveform voltage that rises up to a voltage Vi2 at which an initializing discharge is generated in an initializing period of a subfield subsequent to the second subfield, and then applies a falling ramp. A discharge cell that applies a waveform voltage to the scan electrode and does not perform the forced initialization operation has an upward ramp waveform voltage that rises to a voltage Vi5 that is lower than the voltage Vi2 in the initialization period of the next subfield of the second subfield. After being applied to the scan electrode, a downward ramp waveform voltage is applied to the scan electrode.

  In the subsequent address period of SF2, the voltage 0 (V) is continuously applied to the data electrodes D1 to Dm, and the voltage Ve1 is continuously applied to the sustain electrodes SU1 to SUn. Then, a scan pulse of voltage Va is sequentially applied to scan electrodes SC1 to SCn, and an address operation is performed by applying an address pulse of voltage Vd to data electrode Dk corresponding to the discharge cell to emit light.

  In the subsequent sustain period of SF2, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and a sustain pulse of voltage Vs is applied to scan electrodes SC1 to SCn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the voltage Vs plus the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. The discharge start voltage is exceeded. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. On the other hand, the sustain discharge does not occur in the discharge cells in which the address discharge has not occurred, and the wall voltage at the end of the initialization operation is maintained.

  Subsequently, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and a sustain pulse of voltage Vs is applied to sustain electrodes SU1 to SUn. Then, the sustain discharge occurs again in the discharge cell in which the sustain discharge has occurred, and the phosphor layer 35 emits light. Then, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and sustain discharge is continuously generated in the discharge cells in which address discharge has occurred.

  Thereafter, an upward ramp waveform voltage that gently rises toward voltage Vr1 lower than voltage Vr2 is applied to scan electrodes SC1 to SCn. Then, an erasing discharge is generated in the discharge cell in which the sustain discharge has been performed, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. Since a positive wall voltage is accumulated on data electrode Dk, no discharge is generated between scan electrode SCi and data electrode Dk. Thus, the maintenance operation is finished.

  In the initialization period of SF3, the voltage 0 (V) is applied to the data electrodes D1 to Dm, and the voltage Ve1 is applied to the sustain electrodes SU1 to SUn. Then, a downward ramp waveform voltage that gently falls toward voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, a weak initializing discharge is generated in the discharge cell that has generated the sustain discharge in the immediately preceding subfield, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. In addition, an excessive portion of the wall voltage on the data electrode Dk is discharged and adjusted to a wall voltage suitable for the address operation. In this way, the selective initialization operation is completed.

  In the subsequent address period of SF3, as in the address period of SF2, the voltage Ve1 is continuously applied to the sustain electrodes SU1 to SUn. Then, a scan pulse is sequentially applied to scan electrodes SC1 to SCn, and an address pulse is applied to data electrode Dk corresponding to a discharge cell to emit light to perform an address operation.

  The operation in the subsequent sustain period of SF3 is the same as the sustain period of SF2 except for the number of sustain pulses. That is, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and sustain discharge is continuously generated in the discharge cells in which the address discharge has occurred. After that, an upward ramp waveform voltage that gradually rises toward the voltage Vr1 is applied to the scan electrodes SC1 to SCn, leaving the positive wall voltage on the data electrode Dk, and on the scan electrode SCi and the sustain electrode SUi. Decrease the upper wall voltage.

  The subsequent operations in SF4 to SF11 are the same as those in SF3 except for the number of sustain pulses.

  In this embodiment, the voltage Vi1 is 145 (V), the voltage Vi2 is 360 (V), the voltage Vi3 is 200 (V), the voltage Vi4 is -167 (V), the voltage Vi5 is 215 (V), The voltage Vc is −40 (V), the voltage Va is −185 (V), the voltage Vs is 200 (V), the voltage Vr1 is 200 (V), the voltage Vr2 is 220 (V), the voltage Ve1 is 115 (V), The voltage Ve2 is 130 (V), and the voltage Vd is 75 (V). However, these voltage values are not limited to the values described above, and are desirably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.

  As described above, in the present embodiment, SF1, that is, the second sub waveform in which the rising ramp waveform voltage that gently rises toward voltage Vr2 is applied to scan electrodes SC1 to SCn without applying the sustain pulse in the sustain period. By using the field, it is possible to display a gradation that is darker than the first subfield that displays the gradation using the sustain pulse. Further, in the present embodiment, the rising voltage Vr2 of the rising ramp waveform voltage applied to scan electrodes SC1 to SCn in the sustain period of SF1 is applied to scan electrodes SC1 to SCn at the end of the sustain period of the other subfields. It is set higher than the ultimate voltage Vr1 of the ramp waveform voltage. The reason will be described below.

  As described above, in the present embodiment, a subfield having a selective initializing period in which an initializing discharge is generated only in a discharge cell that has generated an address discharge in the immediately preceding subfield is arranged next to the second subfield. There is a discharge cell having a field configuration. Specifically, this corresponds to a discharge cell having a scan electrode that does not perform the forced initialization operation.

  The address discharge is generated by applying a voltage exceeding the discharge start voltage to the intersection between the data electrode Dk and the scan electrode SC1, and the voltage difference at the intersection is the difference between the externally applied voltages (Vd−Va). The wall voltage on the data electrode Dk is added and determined. An address discharge can be generated using an address pulse of a relatively low voltage Vd by accumulating an appropriate positive wall voltage on the data electrode in advance.

  When the address discharge is performed, as described above, a negative wall voltage is accumulated on the data electrode Dk. However, in the first subfield SF2 to SF11, after the address operation, the sustain discharge is performed by applying the sustain pulse to the display electrode pair, so that a positive wall voltage is accumulated on the data electrode. Therefore, the subsequent write operation can be performed only by adjusting the positive wall voltage on the data electrode to an appropriate value in the subsequent subfield initialization period.

  However, in the first subfield SF1, after the address discharge is performed, the sustain discharge in which the sustain pulse is applied to the display electrode pair is not performed. Therefore, in the present embodiment, the rising voltage Vr2 of the rising ramp waveform voltage applied to scan electrodes SC1 to SCn in the sustain period of SF1 is higher than voltage Vr1, and scan electrode SCi of the discharge cell in which the address discharge has been performed. The voltage Vr2 exceeds the discharge start voltage with the data electrode Dk. A weak discharge is generated between the scan electrode SCi and the data electrode Dk, and a positive wall voltage is accumulated on the data electrode Dk. By driving in this way, even when the sub-field having a selective initialization period is arranged next to the second sub-field and the selective initialization operation is performed in the subsequent sub-field initialization period. The positive wall voltage on the data electrode can be adjusted to an appropriate value, and the subsequent write operation can be performed.

  However, if the voltage Vr2 is too high, discharge occurs in the discharge cells that did not generate the address discharge in the address period of SF1, the black luminance increases, and the contrast decreases. Therefore, the voltage Vr2 is a voltage in which a positive wall voltage necessary on the data electrode of the discharge cell in which the address discharge is generated in the address period of SF1 is accumulated, and the discharge is not generated in the discharge cell in which the address discharge is not generated. The voltage must not be generated.

  In the present embodiment, the voltage Ve2 applied to the sustain electrodes SU1 to SUn in the address period of SF1 in which gradation display is performed lower than the subfield to which the sustain pulse is applied to the display electrode pair is applied to the other subfields. It is set higher than the voltage Ve1 applied to the sustain electrodes SU1 to SUn in the address period. The reason will be described below.

  SF1 is a subfield for displaying the luminance of the second lowest gradation after black, and is a subfield used for displaying a smooth luminance change when displaying a dark image. Therefore, there are many proportions of discharge cells that emit light alone with SF1, or discharge cells that emit light with subfield and SF1 having a relatively small luminance weight. In such a discharge cell, since priming is insufficient, there is a high probability that a stable address discharge will not occur even if an address pulse is applied.

  However, in the present embodiment, the high voltage Ve2 is applied to the sustain electrodes SU1 to SUn in the address period of SF1 to easily generate the address discharge. Therefore, even in a discharge cell that lacks priming, an address discharge can be stably generated in a discharge cell to which a data pulse is applied. Of course, in a discharge cell in which priming is sufficiently present, there is a high probability of erroneous writing in which an address discharge occurs in a discharge cell to which no data pulse is applied. However, since discharge cells with sufficient priming are limited to discharge cells that emit light in a subfield with high luminance weight, such erroneous writing does not deteriorate image display quality.

Next, the relationship between a specific scan electrode that performs the forced initialization operation and the field will be described. In the present embodiment, a specific scan electrode for performing a forced initialization operation is set for each field based on the following rules. When a forced initialization operation is performed only once in one field among N consecutive fields (N is a natural number) for one scan electrode, the N fields that are temporally continuous are defined as one field group, N scan electrodes arranged in series are defined as one scan electrode group. Moreover,
(Rule 1) The field where the forced initialization operation is performed by one scan electrode is one in each field group.
(Rule 2) There is one scan electrode in each scan electrode group that performs the forced initialization operation in one field.

Furthermore, if N ≧ 5,
(Rule 3) In the scan electrode adjacent to the scan electrode that performs the forced initialization operation in a certain field, the forced initialization operation is not performed in at least the field and the next field.

  FIG. 4 is a diagram showing the relationship between the scan electrode that performs the forced initializing operation and the field in the first embodiment of the present invention. In the case of N = 5 where five consecutive fields are one field group. An example is shown. The horizontal axis represents the field, and the vertical axis represents the scan electrode. The fields Fj to Fj + 4 constitute one field group, and the scan electrodes SCi to SCi + 4 constitute one scan electrode group. Further, “◯” indicates that the forced initialization operation is performed, and “X” indicates that the forced initialization operation is not performed.

  As is apparent from FIG. 4, each scan electrode SCi performs a forced initialization operation in one field in each field group. The same applies to the other scan electrodes (Rule 1). As a result, the number of forced initialization operations is reduced by a factor of 5 compared to the case where the forced initialization operation is performed every time in all the discharge cells for each field, so the black luminance of the display image is also 5 minutes. It can be reduced to 1. For each field Fj, a forced initialization operation is performed with one scan electrode in the scan electrode group. The same applies to the other fields (Rule 2). As a result, the scan electrodes that perform the forced initialization operation can be dispersed in each field, and flicker can be reduced. Scan electrode SCi performs a forced initialization operation in field Fj, and scan electrode SCi-1 and scan electrode SCi + 1 adjacent to scan electrode SCi do not perform a forced initialization operation in field Fj and the next field Fj + 1. The same applies to the other scan electrodes (Rule 3). As a result, the temporal and spatial continuity of the scan electrodes that perform the forced initialization operation can be reduced, so that light emission due to the forced initialization operation is hardly recognized.

  As described above, in the present embodiment, each of the discharge cells is forcibly initialized to forcibly generate an initializing discharge in the initializing period of one subfield belonging to one of a plurality of consecutive fields. Perform the action. As a result, the black luminance is lowered and an image display with high contrast is performed.

  In addition, one field includes a first subfield that applies an upward ramp waveform voltage that rises to the first voltage Vr1 after applying a sustain pulse to the scan electrode and the sustain electrode in the sustain period, and a sustain period in the sustain period. A second subfield that applies an upward ramp waveform voltage that rises to a second voltage Vr2 that is higher than the first voltage Vr1 without applying a sustain pulse to the scan electrode and the sustain electrode. A subfield having an initializing period for performing a selective initializing operation for generating an initializing discharge only in a discharge cell in which an address discharge is generated in the subfield is configured to include a field arranged after the second subfield. Yes. As a result, the luminance of the next lowest gradation after black is reduced to perform image display with high image display quality.

  Next, a driving circuit for driving the panel 10 and its operation will be described. FIG. 5 is a circuit block diagram of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. The plasma display device 40 includes the panel 10 and its drive circuit. The drive circuit includes an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and each of them. A power supply circuit (not shown) for supplying necessary power to the circuit block is provided.

  The image signal processing circuit 41 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode driving circuit 42 converts the image data for each subfield into address pulses corresponding to the data electrodes D1 to Dm, and applies them to the data electrodes D1 to Dm. The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block on the basis of the vertical and horizontal synchronization signals, and supplies them to the respective circuit blocks. Scan electrode drive circuit 43 generates the drive voltage waveform described above based on the timing signal and applies it to each of scan electrodes SC1 to SCn. Sustain electrode drive circuit 44 generates the drive voltage waveform described above based on the timing signal and applies it to sustain electrodes SU1 to SUn.

  FIG. 6 is a circuit diagram of scan electrode drive circuit 43 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. Scan electrode drive circuit 43 includes sustain pulse generation circuit 50, ramp waveform voltage generation circuit 60, and scan pulse generation circuit 70.

  Sustain pulse generation circuit 50 includes power recovery circuit 51, switching element Q55, switching element Q56, and switching element Q59, and generates sustain pulses to be applied to scan electrodes SC1 to SCn. The power recovery circuit 51 recovers and reuses power when driving the scan electrodes SC1 to SCn. Switching element Q55 clamps scan electrodes SC1 to SCn to voltage Vs, and switching element Q56 clamps scan electrodes SC1 to SCn to voltage 0 (V). The switching element Q59 is a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43.

  Scan pulse generating circuit 70 includes switching elements Q71H1 to Q71Hn, Q71L1 to Q71Ln, and switching element Q72. Then, a scan pulse is generated based on the power source of voltage Va and the power source of voltage Vp superimposed on the reference potential (potential of node A shown in FIG. 6) of scan pulse generating circuit 70, and scan electrodes SC1 to SCn. A scan pulse is sequentially applied to each of them at the timing shown in FIG. Scan pulse generation circuit 70 outputs the output voltage of sustain pulse generation circuit 50 as it is during the sustain operation. That is, the voltage at node A is output to scan electrodes SC1 to SCn.

  The ramp waveform voltage generation circuit 60 includes Miller integration circuits 61 to 63, and generates the ramp waveform voltage shown in FIG. Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61, and applies a constant voltage to input terminal IN61 to generate an upward ramp waveform voltage that gradually rises toward voltage Vt. Miller integrating circuit 62 includes transistor Q62, capacitor C62, resistor R62, and diode D62 for preventing backflow, and by applying a constant voltage to input terminal IN62, it rises gently toward voltage Vr1. Generate waveform voltage. Miller integrating circuit 63 includes transistor Q63, capacitor C63, and resistor R63, and applies a constant voltage to input terminal IN63 to generate a downward ramp waveform voltage that gradually decreases toward voltage Vi4. The switching element Q69 is also a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode drive circuit 43.

  In addition, these switching elements and transistors can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the switching elements and transistors generated by the timing generation circuit 45.

  FIG. 7 is a circuit diagram of sustain electrode drive circuit 44 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. Sustain electrode drive circuit 44 includes sustain pulse generation circuit 80 and constant voltage generation circuit 90.

  Sustain pulse generation circuit 80 includes power recovery circuit 81, switching element Q85, and switching element Q86, and generates sustain pulses to be applied to sustain electrodes SU1 to SU1080. The power recovery circuit 81 recovers and reuses power when driving the sustain electrodes SU1 to SU1080. Switching element Q85 clamps sustain electrodes SU1 to SU1080 to voltage Vs, and switching element Q86 clamps sustain electrodes SU1 to SU1080 to voltage 0 (V).

  Constant voltage generation circuit 90 includes switching elements Q91 and Q92 and backflow prevention diodes D91 and D92, and applies voltage Ve1 or voltage Ve2 to sustain electrodes SU1 to SU1080.

  Note that these switching elements can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements are controlled by timing signals corresponding to the respective switching elements generated by the timing generation circuit 45.

  Next, operations of scan electrode drive circuit 43 and sustain electrode drive circuit 44, particularly operations from SF1 to SF2 will be described. In the present embodiment, the voltage Vi1 shown in FIG. 3 is equal to the voltage Vp, the voltage Vi2 is equal to the voltage (Vt + Vp), the voltage Vi3 is equal to the voltage Vs, the voltage Vi5 is equal to the voltage Vt, and the voltage Vc is equal to the voltage Vc. The description will be made assuming that it is equal to (Va + Vp). However, these voltages are not limited to the above, and can be appropriately set according to the circuit configuration.

  FIG. 8 is a timing chart for explaining operations of scan electrode drive circuit 43 and sustain electrode drive circuit 44 of plasma display device 40 in accordance with the first exemplary embodiment of the present invention. In FIG. 8, among the scan electrodes SC1 to SCn, the scan electrode that performs the forced initializing operation is indicated by the scan electrode SCx, and the scan electrode that does not perform the forced initializing operation is indicated by the scan electrode SCy. Of the switching elements Q71H1 to Q71Hn, a switching element corresponding to the scan electrode SCx is indicated by a switching element Q71Hx, and a switching element corresponding to the scan electrode SCy is indicated by a switching element Q71Hy. Similarly, among switching elements Q71L1 to Q71Ln, a switching element corresponding to scan electrode SCx is indicated by switching element Q71Lx, and a switching element corresponding to scan electrode SCy is indicated by switching element Q71Ly.

  In the initialization period of SF1, switching element Q92 of sustain electrode drive circuit 44 is turned on, and voltage Ve2 is applied to sustain electrodes SU1 to SUn. Then, the switching elements Q71Lx and Q71Ly of the scan electrode driving circuit 43 are turned on, and a constant voltage is applied to the input terminal IN63 of the Miller integrating circuit 63 to operate the Miller integrating circuit 63, and the voltage Vi4 is applied to the scanning electrodes SCx and SCy. Apply a downward ramp waveform voltage that gently falls to

  In the subsequent address period of SF1, the transistor Q63 of the Miller integrating circuit 63 of the scan electrode driving circuit 43 is turned off, the switching element Q72 is turned on to set the voltage at the node A to the voltage Va, and the switching elements Q71Lx and Q71Ly are turned off and switched. The elements Q71Hx and Q71Hy are turned on, and a voltage (Va + Vp) is applied to each of the scan electrodes SCx and SCy.

  Next, switching element Q71H1 is turned off and switching element Q71L1 is turned on. After a certain time, switching element Q71L1 is turned off and switching element Q71H1 is turned back on. In this way, a scan pulse is applied to scan electrode SC1. Similarly, scanning pulses are sequentially applied until reaching the scanning electrode SCn.

  Thereafter, switching element Q72, switching elements Q71Hx, Q71Hy are turned off, switching element Q56, switching element Q69, switching elements Q71Lx, Q71Ly are turned on, and voltage 0 (V) is applied to scan electrodes SCx, SCy.

  In the subsequent sustain period of SF1, switching element Q92 of sustain electrode drive circuit 44 is turned off, switching element Q86 is turned on, and voltage 0 (V) is applied to sustain electrodes SU1 to SUn. Then, the switching element Q56 of the scan electrode driving circuit 43 is turned off, and a constant voltage is applied to the input terminal IN61 of the Miller integrating circuit 61 to operate the Miller integrating circuit 61, so that the scanning electrodes SCx and SCy rise gently. Apply up-slope waveform voltage. When the voltage of scan electrodes SCx and SCy reaches voltage Vr2, transistor Q61 of Miller integrating circuit 61 is turned off. In this way, an upward ramp waveform voltage that gently rises to voltage Vr2 is applied to scan electrodes SCx and SCy.

  In the first half of the initialization period of SF2, first, the switching element Q56 of the scan electrode drive circuit 43 is turned on to apply the voltage 0 (V) to the scan electrodes SCx and SCy. Next, switching element Q56 is turned off, and switching element Q71Lx is turned off and switching element Q71Hx is turned on to apply voltage Vp to scan electrode SCx that performs the forced initialization operation. On the other hand, voltage 0 (V) is still applied to scan electrode SCy that does not perform the forced initialization operation.

  Next, a constant voltage is applied to the input terminal IN61 of the Miller integrating circuit 61, and the voltage at the node A is gradually increased to the voltage Vt. Then, an upward ramp waveform voltage that gently rises from the voltage Vp to the voltage (Vt + Vp) is applied to the scan electrode SCx that performs the forced initialization operation. On the other hand, an upward ramp waveform voltage that gently rises from voltage 0 (V) to voltage Vt is applied to scan electrode SCy that does not perform the forced initialization operation.

  In the latter half of the initializing period of SF2, the switching element Q86 of the sustain electrode driving circuit 44 is turned off, the switching element Q91 is turned on, and the voltage Ve1 is applied to the sustain electrodes SU1 to SUn. Then, the switching element Q71Hx of the scan electrode drive circuit 43 is turned off, the switching element Q71Lx is turned back on, the switching element Q55 and the switching element Q59 are turned on, and the voltage Vs is first applied to the scan electrodes SCx and SCy. After that, the switching element Q69 is turned off and a constant voltage is applied to the input terminal IN63 of the Miller integrating circuit 63 to operate the Miller integrating circuit 63, so that the downward slope gradually falls to the voltage Vi4 on the scan electrodes SCx and SCy. A waveform voltage is applied.

  The subsequent writing period of SF2 is the same as the writing period of SF1, and the description thereof is omitted.

  In the subsequent sustain period of SF2, using sustain pulse generation circuit 50 of scan electrode drive circuit 43 and sustain pulse generation circuit 80 of sustain electrode drive circuit 44, brightness is applied to scan electrodes SCx and SCy and sustain electrodes SU1 to SUn. A sustain pulse corresponding to the weight is applied. After that, the switching element Q56 of the scan electrode driving circuit 43 is turned off, and a constant voltage is applied to the input terminal IN62 of the Miller integrating circuit 62 to operate the Miller integrating circuit 62. An upward ramp waveform voltage that gradually rises to Vr1 is applied.

  Thus, in the present embodiment, drive voltage waveforms shown in FIG. 3 are applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn using scan electrode drive circuit 43 and sustain electrode drive circuit 44.

  FIG. 8 shows an example in which the voltage Vt is set to a voltage value higher than the voltage Vs. However, the voltage Vt and the voltage Vs may be equal to each other, and the voltage Vt is higher. The voltage value may be lower than the voltage Vs.

  Also, as shown in FIG. 3, in the above description, the field is defined as starting in the initialization period of SF1 and ending in the maintenance period of SF11. However, the start time and end time of the field can be arbitrarily defined. FIG. 9 is another drive voltage waveform diagram applied to each electrode of the plasma display device in accordance with the first exemplary embodiment of the present invention. In FIG. 9, the field is defined as starting in the writing period of SF1, and ending after applying a voltage waveform similar to the driving voltage waveform in the initializing period of SF1 to each electrode after the sustaining period of SF11. . However, the wall voltage for the write operation in the write period of SF1 is formed with a voltage waveform similar to the drive voltage waveform in the initialization period of SF1 provided after the sustain period of SF11. Therefore, the drive voltage waveform provided after the sustain period of SF11 can be considered substantially as an initialization period of SF1. Thus, the start and end of the field may be arbitrarily defined as long as a series of drive voltage waveforms are correctly applied.

  In addition, as shown in FIG. 9, a positive voltage Vd may be applied to the data electrodes D1 to Dm in the first half of the initialization period of SF2, which is a subfield performing the forced initialization operation. By driving in this way, the forced initialization operation can be stably generated.

  Further, as shown in FIG. 9, in the initialization period of SF2 to SF11, which are subfields having a sustain period in which an up-slope waveform voltage is applied to the scan electrode after the sustain pulse is applied to the scan electrode and the sustain electrode, the scan electrode When applying the downward ramp waveform voltage to SC1 to SCn, the output impedance of sustain electrode drive circuit 44 may be set to a high impedance state. By driving in this way, the address discharge can be stably generated and the initialization discharge accompanying the application of the ramp waveform voltage can be stably generated.

  In the present embodiment, whether or not to perform the forced initialization operation for each scan electrode and each field is set based on the above (Rule 1) and (Rule 2). When N ≧ 5, the setting was made based on (Rule 3) in addition to (Rule 1) and (Rule 2). However, the present invention is not limited to this, and can be applied to driving with relaxed conditions. One example will be described below.

(Embodiment 2)
In the second embodiment, a specific scan electrode for performing a forced initialization operation is set for each field based on the following rules. When the forced initialization operation is performed once per N fields for one scan electrode, the N fields that are temporally continuous are regarded as one field group, and M lines (however, M ≦ N) is defined as one scan electrode group. Moreover,
(Rule 1) The field where the forced initialization operation is performed by one scan electrode is one in each field group.
(Rule 2 ′) The number of scan electrodes that perform the forced initialization operation in one field is one or zero in each scan electrode group.

Furthermore, if N ≧ 4,
(Rule 3) In the scan electrode adjacent to the scan electrode that performs the forced initialization operation in a certain field, the forced initialization operation is not performed in at least the field and the next field.

  FIG. 10 is a diagram showing the relationship between the discharge cell performing the forced initialization operation and the field in the second embodiment of the present invention, and shows an example in the case of N = 4 and M = 2. The horizontal axis represents a field, and the vertical axis represents a scan electrode. The fields Fj to Fj + 3 constitute one field group, and the scan electrodes SCi and SCi + 1 constitute one scan electrode group. Further, “◯” indicates that the forced initialization operation is performed, and “X” indicates that the forced initialization operation is not performed.

  As is apparent from FIG. 10, the field in which the scan electrode SCi performs the forced initialization operation is one field in each field group. The same applies to the other scan electrodes (Rule 1). As a result, the number of forced initialization operations is reduced by a factor of four compared to the case where the forced initialization operation is performed every time in all discharge cells for each field, so that the black luminance of the display image is also reduced to four minutes. It can be reduced to 1. Further, the number of scan electrodes that perform the forced initialization operation for the field Fj is one or zero in each scan electrode group. The same applies to the other fields (Rule 2 '). As a result, the scan electrodes that perform the forced initialization operation can be dispersed in each field, and flicker can be reduced. Further, for example, scan electrode SCi performs a forced initialization operation in field Fj, and scan electrode SCi-1 and scan electrode SCi + 1 adjacent to scan electrode SCi do not perform a forced initialization operation in field Fj and the next field Fj + 1. . The same applies to the other scan electrodes (Rule 3). As a result, the temporal and spatial continuity of the scan electrodes that perform the forced initialization operation can be reduced, so that light emission due to the forced initialization operation is hardly recognized.

  The specific numerical values shown in the first and second embodiments are merely examples, and the present invention is not limited to these numerical values. The panel characteristics and the specifications of the plasma display device are not limited to these numerical values. It is desirable to set optimally according to the above. In addition, these numerical values are allowed to vary within a range where the above-described effects can be obtained.

  The present invention reduces the black luminance and the luminance of the second lowest gradation after black, and can display an image with high contrast and high image display quality. As a panel driving method and a plasma display device using the same Useful.

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 40 Plasma display apparatus 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50 Sustain pulse generation circuit 51, 81 power recovery circuit 60 ramp waveform voltage generation circuit 61, 62, 63 Miller integration circuit 70 scan pulse generation circuit 80 sustain pulse generation circuit 90 constant voltage generation circuit

Claims (4)

A plasma display for driving a plasma display panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, with a plurality of subfields having an initialization period, an address period, and a sustain period. A panel driving method,
In the one field, an upward ramp waveform voltage that rises to a first voltage is applied to the scan electrode after applying a sustain pulse for causing discharge in the discharge cell to the scan electrode and the sustain electrode in the sustain period. The first subfield and an upward ramp waveform voltage that rises to a second voltage higher than the first voltage without applying the sustain pulse to the scan electrode and the sustain electrode during the sustain period are applied to the scan electrode. A second subfield to be applied,
Subsequent to the second subfield, a field in which a subfield having an initializing period for performing a selective initializing operation in which an initializing discharge is generated only in a discharge cell in which an address discharge has been generated in the immediately preceding subfield is disposed is included. A method for driving a plasma display panel. 2. The forced initializing operation for forcibly generating an initializing discharge is performed on the discharge cell only in an initializing period of one subfield of a plurality of consecutive fields. Driving method of the plasma display panel. An up-slope waveform voltage rising to a predetermined voltage at which an initializing discharge is generated in an setup period of a sub-field next to the second sub-field is applied to the scan electrode, and then a down-slope waveform voltage is applied to the scan electrode. A discharge cell that performs a forced initializing operation, and a downward ramp waveform voltage that rises to a voltage lower than the predetermined voltage in the initializing period of the subfield next to the second subfield is applied to the scan electrode and then The method of claim 1, further comprising a field in which a discharge cell that performs the selective initializing operation by applying a ramp waveform voltage to the scan electrode is present. A plasma display panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, and a plurality of subfields having an initialization period, an address period, and a sustain period are used to form one field and drive voltage waveform A plasma display device comprising a drive circuit that generates and applies to each electrode of the plasma display panel,
The drive circuit is
A first subfield for applying an upward ramp waveform voltage that rises to a first voltage after applying a sustain pulse for causing a discharge in the discharge cell to the scan electrode and the sustain electrode in the sustain period; In the sustain period, a second sub-waveform voltage applied to the scan electrode is applied to the scan electrode and an up-slope waveform voltage that rises to a second voltage higher than the first voltage without applying the sustain pulse to the sustain electrode. Configuring the one field to include a field,
In addition, the plasma display panel includes a field in which a subfield having an initializing period in which an initializing discharge is generated only in a discharge cell in which an address discharge is generated in the immediately preceding subfield is arranged next to the second subfield. A plasma display device.

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