JP2010107547A - Driving method for plasma display panel and plasma display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a sharp image display that has further improved contrast by suppressing the black luminance of a plasma display device. <P>SOLUTION: A driving method includes displaying gradation by using: a first field that includes an all-cell initialization sub-field for causing all discharge cells to initially discharge during an initialization period; and a second filed that includes no all-cell initialization sub-fields. In a sustaining period of the sub-field of the second field having the same luminance weight as the all-cell initialization sub-field of the first field, an inclination waveform voltage for causing elimination discharge is successively applied more than one time to each of scanning electrodes SC1 to SCn. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a driving method of an AC surface discharge type plasma display panel and a plasma display device using the same.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate arranged to face each other.

  FIG. 7 is an exploded perspective view of the panel 10. The front plate 20 has a plurality of scanning electrodes 22 and sustain electrodes 23 formed on a glass front substrate 21. A pair of scanning electrodes 22 and sustain electrodes 23 form one display electrode pair 24. A dielectric layer 25 is formed so as to cover the display electrode pair 24, and a protective layer 26 is formed on the dielectric layer 25. In the back plate 30, a plurality of data electrodes 32 are formed on a glass back substrate 31, a dielectric layer 33 is formed so as to cover the data electrodes 32, and a grid-like partition wall 34 is formed thereon. . A phosphor layer 35 that emits red, green, and blue light is provided on the side surface of the partition wall 34 and on the dielectric layer 33.

  The front plate 20 and the back plate 30 are arranged to face each other so that the display electrode pair 24 and the data electrode 32 intersect each other with a minute discharge space interposed therebetween, and the outer peripheral portion thereof is sealed with a sealing material such as glass frit. Has been. For example, a discharge gas containing xenon is enclosed in the discharge space. The discharge space is partitioned into a plurality of sections by partition walls 34, and discharge cells are formed at the intersections between the display electrode pairs 24 and the data electrodes 32. These discharge cells discharge and emit light to display an image.

  Note that the structure of the panel 10 is not limited to the above-described structure, and for example, the panel 10 may include a stripe-shaped partition wall.

  FIG. 8 is an electrode array diagram of the panel 10. In panel 10, n scanning electrodes SC1 to SCn (scanning electrode 22 in FIG. 7) and n sustaining electrodes SU1 to SUn (sustaining electrode 23 in FIG. 7) long in the row direction are arranged and long in the column direction. M data electrodes D1 to Dm (data electrode 32 in FIG. 7) are arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed.

  Next, a method for driving the panel 10 will be described. Panel 10 is driven using the subfield method. That is, according to the initialization period in which the initializing discharge is generated in the discharge cell, the address period in which the address discharge is selectively generated in the discharge cell, and the luminance weight determined for each subfield in the discharge cell in which the address discharge is generated A plurality of subfields having a number of sustain discharges and then an erasing discharge are formed to form one field, and the light emission / non-light emission of each discharge cell is controlled for each subfield. Displays the key.

  In the initialization period, an initialization operation is performed in which an initialization discharge is generated and a wall voltage necessary for the address discharge is formed. The wall voltage represents a voltage generated by wall charges accumulated in the discharge cell. The initializing operation at this time includes all-cell initializing operation in which initializing discharge is generated in all discharge cells, and selective initializing operation in which initializing discharge is generated in the discharge cell that has performed address discharge in the immediately preceding subfield. There is.

  Discharge occurs when the absolute value of the total voltage difference Vtot of the voltage difference Vsup applied to the display electrode pair 24 and the wall voltage difference Vwall inside the discharge cell exceeds the discharge start voltage Vf. In the initial state of the panel 10, the absolute value of the voltage difference Vtot is less than the discharge start voltage Vf. However, since no voltage is applied to the display electrode pair 24, assuming that the voltage difference Vsup = 0 (V), the wall voltage difference The absolute value of Vwall is less than the discharge start voltage Vf. The voltage difference Vwall can take any value within the range of −Vf <Vwall <Vf.

  FIG. 9 is a diagram for explaining conditions for performing the all-cell initialization operation. For example, as shown in FIG. 9A, if the voltage difference Vwall of the wall voltage of a certain discharge cell is a voltage difference Vwall (a) that is slightly lower than the discharge start voltage Vf, a slight voltage difference Vsup of the same polarity. By simply applying (a) to the display electrode pair 24, the total voltage difference Vtot (a) exceeds the discharge start voltage Vf and discharge occurs. As shown in FIG. 9B, if the voltage difference Vwall of the wall voltage of a certain discharge cell is 0 (V), the voltage difference Vsup (b) exceeding the discharge start voltage Vf is represented by the display electrode pair 24. Is applied, the total voltage difference Vtot (b) exceeds the discharge start voltage Vf and discharge occurs. Further, as shown in FIG. 9C, the voltage difference Vwall of the wall voltage of a certain discharge cell is slightly lower than the discharge start voltage Vf, and the voltage difference Vwall (a) shown in FIG. It is assumed that the voltage Vwall (c) = − Vwall (a) having a polarity opposite to that of FIG. In this case, if a voltage difference Vsup (c) that is approximately twice or more than the discharge start voltage Vf is not applied to the display electrode pair 24, the total voltage difference Vtot (c) is the discharge start voltage Vf. No discharge occurs without exceeding. Therefore, in order to generate the initialization discharge in all the discharge cells, it is necessary to set the amplitude of the voltage difference Vsup applied to the display electrode pair 24 to be twice or more of the discharge start voltage Vf.

  When image display is started, in the initial state of the panel 10, the voltage difference Vwall of the wall voltage of the discharge cell can take an arbitrary value in a range of −Vf <Vwall <Vf, and the same value is obtained in each of the discharge cells. Not necessarily. Therefore, it is necessary to determine the wall voltages of all the discharge cells by once performing the all-cell initialization operation. The all-cell initialization operation also has an effect of generating priming inside the discharge cells, and is necessary for stably generating discharges in all the discharge cells. However, since all the discharge cells emit light, there is a side effect of increasing the luminance of the black display region (hereinafter abbreviated as “black luminance”) and decreasing the contrast.

  This all-cell initialization operation is performed once per field, and the all-cell initialization operation is performed using a slowly changing ramp waveform voltage, thereby reducing light emission not related to gradation display as much as possible and improving the contrast. For example, Patent Document 1 discloses a new improved driving method.

Further, Patent Document 2 discloses a panel driving method capable of performing a stable address operation even during high-speed driving by applying a ramp-shaped upward ramp waveform voltage at the end of the sustain period.
JP 2000-242224 A JP 2007-114805 A

  In recent years, panels have become increasingly larger and higher in definition, and accordingly, there has been a demand for higher contrast and higher image quality of displayed images.

  Patent Document 1 describes a driving method in which the contrast is increased by setting the sub-field for performing the all-cell initialization operation once per field, but in order to increase the contrast further, It is possible to consider driving in which the number of subfields for performing the digitizing operation is further reduced. For example, the contrast can be doubled by performing the all-cell initialization operation once every two fields.

  However, the strength of the address discharge when the all-cell initialization operation is performed is different from the strength of the address discharge when the all-cell initialization operation is not performed. When the switching operation and the selective initialization operation are alternately switched, there is a problem that flicker occurs and the image display quality is deteriorated.

  The present invention has been made in view of the above problems, and even if the subfield for performing the all-cell initialization operation is set to a ratio of less than once per field, the black luminance is suppressed and the contrast is suppressed while flicker is suppressed. An object of the present invention is to provide a panel driving method and a plasma display device capable of displaying a powerful image with a further enhanced image quality.

  In order to achieve the above object, the present invention provides a method of driving a panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode. An address period in which an address discharge is selectively generated in a cell and a sustain period in which a sustain discharge is generated a number of times according to the luminance weight determined for each subfield in the discharge cell in which the address discharge is generated and then an erasure discharge is generated. The first field including the all-cell initializing subfield and the all-cell initializing subfield not including the all-cell initializing subfield, in which one subfield is configured using a plurality of subfields and the initializing discharge is generated in all discharge cells in the initializing period The second field having the same luminance weight as the luminance weight of the all-cell initialization subfield of the first field. In the sustain period of a subfield of Rudo, and applying successively a plurality of times an inclined waveform voltage for generating the erasing discharge to the scan electrodes. By this method, it is possible to provide a panel driving method capable of displaying a powerful image with suppressed black luminance and further enhanced contrast.

  The first field and the second field may be used alternately.

  In the present invention, the pulse width of the scan pulse applied to the scan electrode in the address period of the second field subfield having the same luminance weight as the luminance weight of the all-cell initialization subfield of the first field is You may set longer than the pulse width of the scanning pulse applied to a scanning electrode in the write period of all the cell initialization subfields. By this method, the address discharge can be surely generated.

  The plasma display apparatus of the present invention controls a scan electrode drive circuit and a scan electrode drive circuit that generate a drive voltage waveform to be applied to the scan electrode, a panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode. A timing generation circuit for generating a timing signal to generate an initializing period for generating an initializing discharge in the discharge cell, an addressing period for selectively generating an address discharge in the discharge cell, and an addressing discharge One field is formed by using a plurality of subfields having a sustain period for generating the number of sustain discharges corresponding to the luminance weight determined for each subfield in the discharge cell and then generating an erasing discharge, and in the initialization period A first field including all cell initialization subfields for generating an initializing discharge in all discharge cells and all cells The gray level is displayed using the second field that does not include the initialization subfield, and the scan electrode driving circuit has the second field sub-field having the same luminance weight as the luminance weight of the all-cell initialization subfield of the first field. In the sustain period of the field, a ramp waveform voltage for generating an erasing discharge is continuously applied to the scan electrode a plurality of times. With this configuration, it is possible to provide a plasma display device capable of displaying a powerful image with reduced black luminance and further enhanced contrast.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the panel drive method and plasma display apparatus which can perform powerful image display which suppressed the black luminance and further improved the contrast.

  Hereinafter, a plasma display device according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment)
The panel 10 used in the plasma display device according to the embodiment of the present invention is the same as the panel 10 shown in FIG. 7, and the electrode arrangement of the panel 10 is also the same as the electrode arrangement shown in FIG. Omitted.

  Next, a method for driving the panel 10 will be described. Panel 10 is driven using the subfield method. That is, according to the initialization period in which the initializing discharge is generated in the discharge cell, the address period in which the address discharge is selectively generated in the discharge cell, and the luminance weight determined for each subfield in the discharge cell in which the address discharge is generated A plurality of subfields having a number of sustain discharges and then an erasing discharge are formed to form one field, and the light emission / non-light emission of each discharge cell is controlled for each subfield. Displays the key.

  In the initialization period, an initialization operation is performed in which an initialization discharge is generated and a wall voltage necessary for the address discharge is formed. The wall voltage represents a voltage generated by wall charges accumulated in the discharge cell. The initializing operation at this time includes all-cell initializing operation in which initializing discharge is generated in all discharge cells, and selective initializing operation in which initializing discharge is generated in the discharge cell that has performed address discharge in the immediately preceding subfield. There is.

  In the present embodiment, in order to suppress the increase in black luminance as much as possible, the all-cell initialization operation is performed at a rate of once every two fields, instead of performing the all-cell initialization operation for each field. That is, a gray scale is displayed using a first field including an all-cell initializing subfield that generates an initializing discharge in all discharge cells during an initializing period, and a second field not including an all-cell initializing subfield. is doing. As a result, the contrast can be improved approximately twice as compared with the conventional plasma display device.

  Specifically, as will be described in detail below, the slope that generates the erasing discharge in the sustain period of the subfield of the second field having the same luminance weight as the luminance weight of the all-cell initialization subfield of the first field. By applying the waveform voltage to scan electrodes SC1 to SCn a plurality of times in succession, a first field including a subfield for performing all-cell initialization operation while suppressing flicker, and a subfield for performing all-cell initialization operation By alternately using the second field that does not include, a powerful image display with further enhanced contrast is performed.

  Hereinafter, for the sake of explanation, one field is divided into 10 subfields (SF1, SF2,..., SF10), and each of the subfields is, for example, (1, 2, 3, 6, 12, 22). , 37, 45, 57, 71). The first field is a field in which the all-cell initialization operation is performed in the initialization period of SF1 and the selective initialization operation is performed in the initialization period of SF2 to SF10. The second field is selected in the initialization period of SF1 to SF10. It is assumed that the field performs an initialization operation.

  First, the first field having subfields for performing the all-cell initialization operation will be described in detail. FIG. 1 is a drive voltage waveform diagram applied to each electrode of panel 10 in the embodiment of the present invention, and is a drive voltage waveform diagram in a first field.

  In the initializing period of SF1 of the first field, the all-cell initializing operation is performed. Specifically, first, voltage 0 (V) is applied to data electrodes D1 to Dm, and voltage 0 (V) is also applied to sustain electrodes SU1 to SUn. Scanning electrodes SC1 to SCn are applied with an upward ramp waveform voltage that gradually rises from voltage Vi1 equal to or lower than the discharge start voltage to sustain electrodes SU1 to SUn toward voltage Vi2 that exceeds the discharge start voltage. Then, weak initialization discharges occur between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm, respectively, and negative charges are generated on scan electrodes SC1 to SCn. A wall voltage is accumulated, and a positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer 25 covering the electrode, the protective layer 26, the phosphor layer 35, and the like.

  Next, voltage Ve1 is applied to sustain electrodes SU1 to SUn, and a downward ramp waveform voltage that gently decreases from voltage Vi3 to voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, weak initializing discharge occurs again between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. Then, the negative wall voltage on scan electrodes SC1 to SCn and the positive wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage on data electrodes D1 to Dm is adjusted to a value suitable for the write operation. Is done. In this way, regardless of the image signal, initialization discharge is generated in all the discharge cells, priming for facilitating subsequent discharge is generated, and wall charges necessary for address discharge are formed.

  In this way, the voltage difference Vsup applied to the display electrode pair changes from the voltage (Vi2-0) to the voltage (Vi4-Ve1), and the amplitude becomes the voltage (Vi2-Vi4 + Ve1), which is 2 of the discharge start voltage Vf. More than double. However, the voltage Vi4 is a negative voltage. Thus, the all-cell initializing operation for generating the initializing discharge for all the discharge cells is performed in the initializing period of SF1 in the first field.

  In the subsequent address period of SF1, scan pulses are sequentially applied to scan electrodes SC1, SC2,..., SCn, and address pulses are applied to data electrodes Dk (k = 1 to m) corresponding to discharge cells to emit light. Thus, an address discharge is generated, and wall charges necessary for the subsequent sustain discharge are formed.

  Specifically, first, voltage Vc is applied to scan electrodes SC1 to SCn, voltage 0 (V) is applied to data electrodes D1 to Dm, and voltage Ve2 is applied to sustain electrodes SU1 to SUn.

  Next, a scan pulse of voltage Va is applied to scan electrode SC1 in the first row, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, address discharge occurs between data electrode Dk and scan electrode SC1, and between sustain electrode SU1 and scan electrode SC1, positive wall voltage is accumulated on scan electrode SC1, and negative wall is applied on sustain electrode SU1. A voltage is accumulated, and a negative wall voltage is also accumulated on the data electrode Dk. In this manner, an address operation is performed in which an address discharge is caused in the discharge cells to be lit in the first row and wall voltage is accumulated on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the address pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that address discharge does not occur.

  The above address operation is repeated until the discharge cell in the n-th row, and an address discharge is selectively generated in the discharge cells to emit light to form wall charges.

  Note that the address discharge after the all-cell initializing operation tends to be a stronger discharge than the address discharge after performing the selective initializing operation described later, and the light emission accompanying the address discharge becomes brighter. It can be considered that this is because the region where the wall charges are formed by the all-cell initializing operation is wider than the region where the wall charges are formed by the selective initializing operation.

  In the subsequent sustain period of SF1, the number of sustain pulses (including “0”) corresponding to the luminance weight is applied to the display electrode pair, and the sustain discharge is generated in the discharge cells that have caused the address discharge in the address period. At the end of the sustain period, erasing discharge for erasing the wall voltage is performed.

  Specifically, first, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and a sustain pulse of voltage Vs is applied to scan electrodes SC1 to SCn. Then, in the discharge cell in which the address discharge has occurred, the voltage difference between scan electrode SCi and sustain electrode SUi is the voltage Vs plus the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi. The discharge start voltage is exceeded. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 35 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi. Further, a positive wall voltage is accumulated on the data electrode Dk. On the other hand, in the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

  Subsequently, voltage 0 (V) is applied to scan electrodes SC1 to SCn, and a sustain pulse of voltage Vs is applied to sustain electrodes SU1 to SUn. Then, the sustain discharge occurs again in the discharge cell in which the sustain discharge has occurred, and the phosphor layer 35 emits light. Then, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi. Thereafter, similarly, sustain pulses of the number corresponding to the luminance weight are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and sustain discharge is continuously generated in the discharge cells in which the address discharge is caused in the address period. Let

  At the end of the sustain period, an upward ramp waveform voltage that gradually rises toward the ultimate voltage Vr1 is applied to scan electrodes SC1 to SCn. Then, an erasing discharge is generated in the discharge cell in which the sustain discharge has been performed, and the wall voltage on the scan electrode SCi and the sustain electrode SUi is erased while leaving the positive wall voltage on the data electrode Dk.

  When the number of sustain pulses corresponding to the luminance weight is “0”, the sustain pulses gradually increase toward the ultimate voltage Vr1 without applying sustain pulses to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. An upward ramp waveform voltage is applied to scan electrodes SC1 to SCn to generate an erasing discharge.

  Thus, the maintenance operation in the maintenance period is completed.

  In the subsequent initialization period of SF2, a selective initialization operation is performed. Specifically, voltage Ve1 is applied to sustain electrodes SU1 to SUn, and a ramp waveform voltage that gently decreases toward voltage Vi4 is applied to scan electrodes SC1 to SCn. Then, a weak initializing discharge is generated in the discharge cell in which a sustain discharge (erase discharge when the number of sustain pulses is “0”) is generated in the sustain period of SF1, and the wall on scan electrode SCi and sustain electrode SUi. The voltage is weakened. For data electrode Dk, a sufficient positive wall voltage is accumulated on data electrode Dk by the last sustain discharge, so that an excessive portion of this wall voltage is discharged, and the wall voltage suitable for the write operation is obtained. Adjusted to On the other hand, the discharge cells that did not cause the sustain discharge in SF1 are not discharged, and the wall charges at the end of the initialization operation of SF1 are maintained as they are.

  In the subsequent address period of SF2, a scan pulse is sequentially applied to scan electrodes SC1, SC2,..., SCn, and voltage Vd is written to data electrode Dk (k = 1 to m) corresponding to the discharge cell to emit light. A pulse is applied to generate an address discharge, and wall charges necessary for the subsequent sustain discharge are formed.

  In the subsequent sustain period of SF2, the number of sustain pulses corresponding to the luminance weight is applied to the display electrode pair, and the sustain discharge is generated in the discharge cells that have caused the address discharge in the address period. At the end of the sustain period, erasing discharge for erasing the wall voltage is performed. The erasing discharge at this time is generated by applying an upward ramp waveform voltage that gradually rises toward the ultimate voltage Vr2 to the scan electrodes SC1 to SCn. The ultimate voltage Vr2 may be equal to the ultimate voltage Vr1, or may be different from the voltage Vr1, for example, higher than the voltage Vr1.

  Subsequent operations in SF3 to SF10 are the same as those in SF2 except for the number of sustain pulses, and thus description thereof is omitted. The above is the first field for performing the all-cell initializing operation in the initializing period of SF1.

  Next, the second field having no subfield for performing the all-cell initialization operation will be described in detail. FIG. 2 is a drive voltage waveform diagram applied to each electrode of panel 10 in the embodiment of the present invention, and is a drive voltage waveform diagram in the second field.

  The selective initialization operation is performed in the initialization period of SF1 in the second field. Specifically, the voltage 0 (V) is applied to the data electrodes D1 to Dm, the voltage Ve1 is applied to the sustain electrodes SU1 to SUn, and the downward slope waveform that gradually decreases toward the voltage Vi4 on the scan electrodes SC1 to SCn. Apply voltage. Then, a weak initializing discharge is generated in the discharge cell that has caused the sustain discharge in the sustain period of the immediately preceding subfield, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. For data electrode Dk, a sufficient positive wall voltage is accumulated on data electrode Dk by the last sustain discharge, so that an excessive portion of this wall voltage is discharged, and the wall voltage suitable for the write operation is obtained. Adjusted to On the other hand, the discharge cells that have not caused the sustain discharge in the immediately preceding subfield are not discharged, and the wall charges at the end of the initialization operation in the immediately preceding subfield or the preceding subfield are maintained as they are.

  In the subsequent address period of SF1, a scan pulse of voltage Va is sequentially applied to scan electrodes SC1, SC2,..., SCn, and an address pulse of voltage Vd is applied to data electrode Dk corresponding to the discharge cell to emit light. Thus, address discharge is generated, and wall charges necessary for the subsequent sustain discharge are formed.

  Note that the address discharge after the selective initialization operation is weaker than the address discharge after the all-cell initialization operation. Accordingly, the address discharge of SF1 in the second field is weaker than the address discharge of SF1 in the first field, and the light emission associated with the address discharge of SF1 in the second field is darker than the light emission associated with the address discharge of SF1 in the first field.

  In the subsequent sustain period of SF1, the number of sustain pulses corresponding to the luminance weight is applied to the display electrode pair, and the sustain discharge is generated in the discharge cells that have caused the address discharge in the address period. At the end of the sustain period, erasing discharge for erasing the wall voltage is performed.

  The erasing discharge at this time is continuously generated a plurality of times. Specifically, first, while maintaining sustain electrodes SU1 to SUn at a voltage of 0 (V), an upward ramp waveform voltage that gradually rises toward positive voltage Vr3 is applied to scan electrodes SC1 to SCn for the first time. Generate a discharge. Next, voltage Ve1 is applied to sustain electrodes SU1 to SUn, and a downward ramp waveform voltage that gently falls toward negative voltage Vr4 is applied to scan electrodes SC1 to SCn to generate a second discharge. Thereafter, voltage 0 (V) is applied to sustain electrodes SU1 to SUn, and an upward ramp waveform voltage that gently rises toward positive voltage Vr5 is applied to scan electrodes SC1 to SCn to generate a third discharge. Thus, in the present embodiment, a weak discharge is continuously generated three times as an erasing discharge. For this reason, light emission associated with the erase discharge of SF1 in the second field is brighter than light emission associated with the erase discharge of SF1 in the first field. Although details will be described later, in this embodiment, the occurrence of flicker is suppressed by driving in this way.

  The subsequent operations in SF2 to SF10 in the second field are the same as those in SF2 to SF10 in the first field, and thus the description thereof is omitted. The above is the second field in which the all-cell initialization operation is not performed.

  In the present embodiment, voltage Vi1 applied to scan electrodes SC1 to SCn is 145 (V), voltage Vi2 is 300 (V), voltage Vi3 is 190 (V), voltage Vi4 is -150 (V), The voltage Va is −155 (V), the voltage Vs is 190 (V), the voltage Vr1 and the voltage Vr2 are 190 (V), the voltage Vr3 is 200 (V), the voltage Vr4 is −150 (V), and the voltage Vr5 is 200 (V). V), the voltage Ve1 applied to the sustain electrodes SU1 to SUn is 140 (V), and the voltage Ve2 is 155 (V). The slopes of the rising ramp waveform voltage and the falling ramp waveform voltage applied to scan electrodes SC1 to SCn are both 12 (V / μ) or less. The voltage Vd applied to the data electrodes D1 to Dm is 75 (V). However, these voltage values are not limited to the values described above, and are desirably set optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.

  In the present embodiment, by driving the panel 10 by alternately using the first field and the second field described above, it is possible to display an image with further enhanced contrast while suppressing flicker. The reason will be described below.

FIG. 3 is a diagram showing an example of the light emission intensity associated with the discharge of the panel 10 according to the embodiment of the present invention. The numerical values shown are for only a predetermined discharge at a rate of once per field in all discharge cells. The luminance value observed when it is assumed that it is generated is shown. The luminance value of the light emission associated with each discharge is as follows: initialization discharge luminance in all-cell initialization operation = 0.1 (cd / cm ² ); initialization discharge luminance in selective initialization operation = 0.05 (cd / cm ² ), address discharge brightness after all-cell initializing operation = 0.35 (cd / cm ² ), address discharge brightness after selective initializing operation = 0.2 (cd / cm ² ), maintained Brightness of discharge = 0.5 (cd / cm ² ), brightness of erase discharge by ramp waveform voltage rising to voltage Vr1 = 0.1 (cd / cm ² ), erase discharge by ramp waveform voltage rising to voltage Vr3 Luminance = 0.15 (cd / cm ² ). In this embodiment, since the voltage Vr4 and the voltage Vi4 are equal, and the voltage Vr5 and the voltage Vr3 are equal, the luminance of the erasing discharge due to the ramp waveform voltage falling to the voltage Vr4 = 0.05 (cd / cm ² ), The luminance of the erasing discharge due to the ramp waveform voltage rising to the voltage Vr5 = 0.15 (cd / cm ² ).

Here, when the luminance of the area displaying the darkest gradation, that is, the black luminance, is estimated, the light emission is only the light emission accompanying the all-cell initialization operation in the initialization period of SF1 of the first field, and the luminance is 0.1 / 2 = 0.05 (cd / cm ² ). This value is ½ of the case where the all-cell initialization operation is performed for each field. At this time, light is emitted once every two fields, but the luminance itself is very low, so it is not recognized as flicker.

  Next, the brightness of the area displaying the second darkest gradation is estimated. The first field light emission is the light emission of the all-cell initialization operation in the initialization period of SF1, the light emission of the address discharge of SF1, the light emission of the sustain discharge and the erase discharge in the sustain period of SF1, and the light emission of the SF2 in the initialization period. This is the light emission of the selective initialization operation. The light emission of the second field is light emission of address discharge of SF1, light emission of three times of sustain discharge and erase discharge in the sustain period of SF1, and light emission of selective initialization operation in the initialization period of SF2.

Assuming one sustain discharge, the luminance of each field is estimated, and the first field emission is (0.1 + 0.35 + 0.5 + 0.1 + 0.05) /2=0.55 (cd / cm ² ), The light emission in the second field is (0.2 + 0.5 + 0.15 + 0.05 + 0.15 + 0.05) /2=0.55 (cd / cm ² ), which is almost equal. Therefore, flicker does not occur even at this gradation.

  Since the luminance of light emission in SF2 to SF10 in the first field and the luminance of light emission in SF2 to SF10 in the second field are equal to each other if the luminance weights in the subfields are equal, flicker occurs even in other gradations. There is no.

  Here, the reason why the luminance of light emission in the first field is equal to the luminance of light emission in the second field is that the difference between the luminance of the address discharge of SF1 in the first field and the luminance of the address discharge of SF1 in the second field. This is because the difference between the luminance of the erasing discharge of SF1 in the first field and the luminance of the erasing discharge generated continuously a plurality of times in SF1 of the second field is offset.

Assuming that the erasure discharge in the second field is only one erasure discharge, the emission in the second field is (0.2 + 0.5 + 0...) With respect to the emission of 0.55 (cd / cm ² ) in the first field. 15 + 0.05) /2=0.45 (cd / cm ² ), and a luminance difference of about 20% occurs, and this luminance difference is recognized as flicker.

  However, in this embodiment, the erase discharge of SF1 in the second field is continuously generated a plurality of times so that the brightness of the erase discharge of SF1 in the second field is higher than the brightness of the erase discharge of SF1 in the first field. Brightening cancels the difference between the luminance of the address discharge in the first field and the luminance of the address discharge in the second field. As a result, no flicker occurs even if the all-cell initialization operation is performed once every two fields.

  Of course, the higher the value of the reaching voltage Vr3 of the ramp waveform voltage, the higher the luminance of the erasing discharge caused by this ramp waveform voltage. Therefore, the brightness of the address discharge of SF1 in the first field and the address discharge of SF1 in the second field are increased. If the difference from the luminance is small, flicker can be suppressed only by setting the ultimate voltage Vr3 high. However, if the ultimate voltage Vr3 becomes too high, a discharge occurs even in a discharge cell that has not caused a sustain discharge in the immediately preceding subfield, and the contrast is rapidly deteriorated. Therefore, when the difference between the brightness of the address discharge of SF1 in the first field and the brightness of the address discharge of SF1 in the second field is large, the same brightness weight as the brightness weight of the all-cell initialization subfield in the first field is used. In the sustain period of the subfield of the second field, the ramp waveform voltage for generating the erasing discharge is continuously applied to the scan electrode a plurality of times, so that the luminance of the address discharge in the first field and the luminance of the address discharge in the second field By canceling out the difference, it is possible to display an image with further enhanced contrast while suppressing flicker.

  The difference between the brightness of the address discharge of SF1 in the first field and the brightness of the address discharge of SF1 in the second field is, for example, in the all-cell initialization period in order to perform a stable all-cell initialization operation in a low-temperature environment. When the ultimate voltage Vi2 of the rising ramp waveform voltage is set high, it tends to increase. In such a case, flicker can be suppressed without lowering contrast by continuously applying a ramp waveform voltage for generating an erasing discharge to the scan electrodes SC1 to SCn a plurality of times in the second field SF1. .

  Note that “applying a ramp waveform voltage that generates an erasing discharge in a sustain period of a specific subfield to a scan electrode a plurality of times in succession” means that “the sustain pulse of a specific subfield and the next of the specific subfield are This means that a ramp waveform voltage for generating an erasing discharge is continuously applied to the scan electrode a plurality of times during the subfield address period.

  In the present embodiment, the first field and the second field described above are used alternately, that is, the all-cell initialization operation is performed once every two fields. However, the present invention is not limited to this. It is not limited. For example, by repeating the first field, the second field, the second field, the first field, the second field, the second field,..., The all-cell initialization operation is performed once every three fields. Also good. Also, for example, the first field, the second field, the first field, the second field, the second field, the first field, the second field, the first field, the second field, the second field,... Thus, the all-cell initialization operation may be performed twice every five fields. However, in any case, the ramp waveform voltage for generating the erasing discharge is applied to the scan electrodes SC1 to SC1 in the sustain period of the second field subfield having the same luminance weight as the luminance weight of the all-cell initialization subfield of the first field. Flicker can be suppressed by continuously applying to SCn a plurality of times. As described above, the ratio of performing the all-cell initialization operation can be set according to the characteristics of the panel, the specifications of the plasma display device, and the like.

  Next, a driving circuit for driving the panel 10 and its operation will be described. FIG. 4 is a circuit block diagram of plasma display device 40 in accordance with the exemplary embodiment of the present invention. The plasma display device 40 includes a panel 10, an image signal processing circuit 41, a data electrode drive circuit 42, a scan electrode drive circuit 43, a sustain electrode drive circuit 44, a timing generation circuit 45, and a power supply circuit that supplies necessary power to each circuit block. (Not shown).

  The image signal processing circuit 41 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 42 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The timing generation circuit 45 generates various timing signals for controlling the operation of each circuit block on the basis of the vertical and horizontal synchronization signals, and supplies them to the respective circuit blocks. Scan electrode driving circuit 43 drives each of scan electrodes SC1 to SCn based on the timing signal. Sustain electrode drive circuit 44 drives sustain electrodes SU1 to SUn based on the timing signal.

  FIG. 5 is a circuit diagram of scan electrode drive circuit 43 of plasma display device 40 in accordance with the exemplary embodiment of the present invention.

  Scan electrode driving circuit 43 generates sustain pulse generating circuit 50 for generating a sustain pulse for generating a sustain discharge in the sustain period, and generates a ramp waveform voltage for generating an initializing discharge in the initializing period, and sustain period Are provided with a ramp waveform voltage generating circuit 60 for generating a ramp waveform voltage for generating an erasing discharge and a scan pulse generating circuit 70 for generating a scan pulse for generating an address discharge in the address period.

  Sustain pulse generation circuit 50 includes a power recovery circuit 51 for recovering and reusing power when driving scan electrodes SC1 to SCn, and a switching element Q55 for clamping scan electrodes SC1 to SCn to voltage Vs. And switching element Q56 for clamping scan electrodes SC1 to SCn to voltage 0 (V). Switching element Q91 is a separation switch, and is provided to prevent the current from flowing back through the parasitic diode of switching element Q55.

  Scan pulse generating circuit 70 includes switching elements Q71H1 to Q71Hn, Q71L1 to Q71Ln, and switching element Q72. A scan pulse is generated based on the power source of voltage Va and the power source of voltage Vp superimposed on the power source of voltage Va, and the scan pulse is sequentially applied to each of scan electrodes SC1 to SCn in the address period. Scan pulse generation circuit 70 outputs the output voltages of sustain pulse generation circuit 50 and ramp waveform voltage generation circuit 60 as they are during the initialization period and the sustain period. That is, the potential at point A shown in FIG. 5 is output to scan electrodes SC1 to SCn.

  In this embodiment, the voltage Vi1 shown in FIG. 1 is equal to the voltage Vp, and the voltage Vi3 is equal to the voltage Vs. That is, voltage Vi1 can be applied to scan electrodes SC1 to SCn by turning on switching element Q56, switching element Q92, and switching elements Q71H1 to Q71Hn, and switching element Q55, switching element Q91, and switching elements Q71L1 to Q71Ln are turned on. Thus, voltage Vi3 can be applied to scan electrodes SC1 to SCn. The voltage Vc shown in FIGS. 1 and 2 is equal to the voltage (Vp + Va). That is, voltage Vc can be applied to scan electrodes SC1 to SCn by turning on switching element Q72 and switching elements Q71H1 to Q71Hn. However, these voltages are not limited to the above, and can be appropriately set according to the circuit configuration.

  The ramp waveform voltage generation circuit 60 includes Miller integration circuits 61, 62, and 63, and generates the ramp waveform voltage described above. Miller integrating circuit 61 includes transistor Q61, capacitor C61, and resistor R61, and generates an upward ramp waveform voltage that gradually rises to voltage Vi2. Miller integrating circuit 62 includes transistor Q62, capacitor C62, and resistor R62, and generates a downward ramp waveform voltage that gradually decreases to voltage Vi4. Miller integrating circuit 63 includes transistor Q63, capacitor C63, resistor R63, and backflow prevention diode D63, and generates an upward ramp waveform voltage that gradually rises to any one of voltages Vr1 to Vr5. The switching element Q92 is also a separation switch, and is provided to prevent a current from flowing backward through a parasitic diode or the like of the switching element constituting the scan electrode driving circuit 43. Then, by making the switching element Q92 conductive, the potential at the point B and the potential at the point A shown in FIG. 5 become equal.

  In addition, these switching elements and transistors can be configured using generally known elements such as MOSFETs and IGBTs. These switching elements and transistors are controlled by timing signals corresponding to the switching elements and transistors generated by the timing generation circuit 45.

  Next, the operation of the ramp waveform voltage generation circuit 60, particularly the operation for continuously generating the erasure discharge in the second field SF1 will be described. FIG. 6 is a timing chart for explaining the operation of the ramp waveform voltage generation circuit 60 of the plasma display device 40 according to the embodiment of the present invention. In the sustain period, switching element Q92 is on and scan pulse generating circuit 70 outputs the voltage at point A as it is, so that the output of ramp waveform voltage generating circuit 60 is scanned via switching element Q92 and scan pulse generating circuit 70. Output to electrodes SC1 to SCn.

  In order to generate the erasing discharge continuously a plurality of times in SF1 of the second field, first, at time t1, a constant voltage, for example, voltage 15 (V) is applied to the input terminal IN63 of Miller integrating circuit 63. Then, a constant current flows from the resistor R63 toward the capacitor C63, the source voltage of the transistor Q63 rises with a constant gradient, and the output voltage of the scan electrode drive circuit 43 starts to rise with a constant gradient. While the constant voltage is applied to the input terminal IN63, the output voltage of the scan electrode drive circuit 43 continues to rise.

  In order to generate a ramp waveform voltage that rises to the voltage Vr3, the voltage 0 (V) is applied to the input terminal IN63 at time t2 when the output voltage of the Miller integrating circuit 63 reaches the voltage Vr3. Then, the output voltage of the scan electrode drive circuit 43 holds the voltage Vr3.

  Next, in order to generate the ramp waveform voltage that drops to the voltage Vr4, the switching element Q56 is once turned on at time t3, and the output of the scan electrode drive circuit 43 is set to the voltage 0 (V). Thereafter, switching elements Q56 and Q92 are turned off, and a constant voltage, for example, voltage 15 (V) is applied to input terminal IN62 of Miller integrating circuit 62 at time t4. Then, a constant current flows from the resistor R62 toward the capacitor C62, the drain voltage of the transistor Q62 decreases with a constant gradient, and the output voltage of the scan electrode drive circuit 43 also starts decreasing with a constant gradient. At time t5 when the output voltage of Miller integrating circuit 62 reaches voltage Vr4, voltage 0 (V) is applied to input terminal IN62. Then, the output voltage of the scan electrode driving circuit 43 maintains the voltage Vr4.

  Next, in order to generate the ramp waveform voltage that rises to the voltage Vr5, the switching elements Q56 and Q92 are once turned on at time t6, and the output of the scan electrode driving circuit 43 is set to the voltage 0 (V). Thereafter, switching elements Q56 and Q92 are turned off, and voltage 15 (V) is applied again to input terminal IN63 of Miller integrating circuit 63 at time t7. Then, the output voltage of the scan electrode driving circuit 43 also rises again with a constant gradient. At time t8 when the output voltage of Miller integrating circuit 63 reaches voltage Vr5, voltage 0 (V) is applied to input terminal IN63. Then, the output voltage of the scan electrode drive circuit 43 holds the voltage Vr5.

  In this way, it is possible to generate a plurality of ramp waveform voltages for generating an erasing discharge continuously a plurality of times using Miller integration circuit 63 and Miller integration circuit 62 of ramp waveform voltage generation circuit 60.

  Here, each of the ultimate voltage Vr3, the ultimate voltage Vr4, and the ultimate voltage Vr5 has a higher erase discharge luminance as its absolute value increases. Of course, the values of the ultimate voltage Vr3, ultimate voltage Vr4, and ultimate voltage Vr5 are as follows. It is desirable to set the light emission luminance of the field and the light emission luminance of the second field to be equal. Further, the luminance may be made uniform by changing the voltage applied to sustain electrodes SC1 to SCn as necessary.

  The drive circuit shown in FIG. 5 is an example of a circuit configuration for generating the drive voltage waveform shown in FIGS. 1 and 2, and the plasma display device of the present invention is not limited to this circuit configuration. Absent.

  1, 2, and 6, the driving waveform applied to scan electrodes SC <b> 1 to SCn is once returned to a voltage of 0 (V) after the rising ramp waveform voltage for generating the erasing discharge, and then selected. A drive waveform for applying a downward ramp waveform voltage for performing the initialization operation is shown. However, it is not always necessary to return the voltage to 0 (V) after applying the rising ramp waveform voltage and before applying the falling ramp waveform voltage. For example, after applying an upward ramp waveform voltage, a downward ramp waveform voltage that gradually decreases from that voltage may be applied. Alternatively, for example, a driving waveform may be applied in which a voltage higher than the voltage 0 (V) is applied after an upward ramp waveform voltage is applied, and then a downward ramp waveform voltage for performing a selective initialization operation is applied.

  Further, as shown in FIG. 1, the drive voltage waveform applied to scan electrodes SC1 to SCn gradually rises to voltage Vr2 at the end of the sustain period of the last subfield of the first field, and then gradually falls to voltage Vi4. A ramp waveform voltage may be applied. In this case, the selective initialization period of the first subfield of the second field may be omitted. Further, as shown in FIG. 2, a ramp waveform voltage that gently rises to voltage Vr2 and then gradually falls to voltage Vi4 may be applied at the end of the sustain period of the last subfield of the second field.

  In the present embodiment, no particular reference is made to the scan pulse applied to the scan electrode and the address pulse applied to the data electrode in the address period. However, if all cells are not initialized, priming will be insufficient. As a result, the time from when the scan pulse is applied to the scan electrode and the address pulse is applied to the data electrode until the address discharge occurs (discharge delay time) Tend to be longer. Therefore, the pulse width of the scan pulse and the write pulse in the SF1 address period of the second field in which the all-cell initialization operation is not performed is set as the scan pulse and the write pulse in the SF1 address period of the first field in which the all-cell initialization operation is performed. It may be set longer than the pulse width. For example, the pulse width of the scan pulse and the write pulse in the write period of SF1 in the first field is set to 1.0 ns, and the pulse width of the scan pulse and the write pulse in the write period of SF1 in the second field is set to 1.6 ns, which is longer than that. can do. As a result, even if the discharge delay time in the address period of SF1 in the second field becomes long, the address discharge can be surely generated.

  Further, the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the values appropriately according to the characteristics of the panel, the specifications of the plasma display device, and the like.

  INDUSTRIAL APPLICABILITY The present invention enables powerful image display in which contrast is further increased by suppressing black luminance, and is useful as a panel driving method and a plasma display device.

Drive voltage waveform diagram applied to each electrode of the panel in the embodiment of the present invention Drive voltage waveform diagram applied to each electrode of the panel The figure which shows an example of the luminescence intensity accompanying the discharge of the panel Circuit block diagram of plasma display device in accordance with exemplary embodiment of the present invention Circuit diagram of scan electrode driving circuit of same plasma display device Timing chart for explaining the operation of the ramp waveform voltage generation circuit of the plasma display device Panel exploded perspective view Panel electrode layout Diagram for explaining conditions for performing all-cell initialization operation

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Panel 22 Scan electrode 23 Sustain electrode 24 Display electrode pair 32 Data electrode 40 Plasma display apparatus 41 Image signal processing circuit 42 Data electrode drive circuit 43 Scan electrode drive circuit 44 Sustain electrode drive circuit 45 Timing generation circuit 50 Sustain pulse generation circuit 60 Inclination Waveform voltage generation circuit 70 Scanning pulse generation circuit 61, 62, 63 Miller integration circuit

Claims (4)

A method of driving a plasma display panel comprising a plurality of discharge cells having scan electrodes, sustain electrodes, and data electrodes,
An initializing period for generating an initializing discharge in the discharge cells, an addressing period for selectively generating an address discharge in the discharge cells, and a luminance weight determined for each subfield in the discharge cells in which the address discharge has been generated. A plurality of subfields having a sustain period for generating a corresponding number of sustain discharges and then generating an erasure discharge;
The gray level is determined using a first field including an all-cell initializing subfield for generating an initializing discharge in all the discharge cells during the initializing period, and a second field not including the all-cell initializing subfield. As well as display
In the sustain period of the subfield of the second field having the same luminance weight as the luminance weight of the all-cell initialization subfield of the first field, the ramp waveform voltage for generating the erasing discharge is continuously applied to the scan electrode a plurality of times. And applying the plasma display panel. The method of claim 1, wherein the first field and the second field are used alternately. The pulse width of the scan pulse applied to the scan electrode in the address period of the subfield of the second field having the same luminance weight as the luminance weight of the all-cell initialization subfield of the first field is the first field. 2. The method of driving a plasma display panel according to claim 1, wherein the pulse width of the scan pulse applied to the scan electrode is set longer during the address period of the all-cell initialization subfield. A plasma display panel having a plurality of discharge cells each having a scan electrode, a sustain electrode, and a data electrode, a scan electrode drive circuit for generating a drive voltage waveform to be applied to the scan electrode, and a timing signal for controlling the scan electrode drive circuit And a timing generation circuit for generating
The timing generation circuit includes:
An initializing period for generating an initializing discharge in the discharge cell, an addressing period for selectively generating an address discharge in the discharge cell, and a luminance weight determined for each subfield in the discharge cell in which the address discharge is generated. A plurality of subfields having a sustain period for generating a sustain discharge of a corresponding number of times and then generating an erasing discharge;
The gray level is determined using a first field including an all-cell initializing subfield for generating an initializing discharge in all the discharge cells during the initializing period, and a second field not including the all-cell initializing subfield. Display
The scan electrode driving circuit generates a ramp waveform voltage that generates the erasing discharge in a sustain period of the subfield of the second field having the same luminance weight as the luminance weight of the all-cell initialization subfield of the first field. A plasma display device, wherein the plasma display device is applied to a scanning electrode continuously a plurality of times.

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