JP2005338217A - Method of driving plasma display panel, and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of driving a plasma display panel which suppresses rising of black luminance while guaranteeing stable write-in operation. <P>SOLUTION: In the method of driving the plasma display panel, in which one field period is composed of: a whole cell initializing sub-field including an initializing period for performing initialization discharge to the whole discharge cells; and a selective initialization sub-field including an initializing period for performing initialization discharge to specific discharge cells, the write time to one discharge cell in a write period of the selective initialization sub-field is set longer than write time to one discharge cell in the write period of the other sub-fields when two or more subfields for performing non-luminescence control continue during a sustaining period just before the selective initialization subfield for performing luminescence control of the discharge cell during sustaining period. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for driving a plasma display panel and a display device using the plasma display panel.

  A typical AC surface discharge type panel as a plasma display panel (hereinafter abbreviated as “panel”) has a large number of discharge cells formed between a front plate and a back plate of two substrates arranged opposite to each other. .

  In the front plate, a plurality of pairs of display electrodes made up of a pair of scan electrodes and sustain electrodes are formed on the front glass substrate in parallel with each other, and a dielectric layer and a protective layer are formed so as to cover the display electrodes. The back plate has a plurality of parallel data electrodes on the back glass substrate, a dielectric layer so as to cover them, and a plurality of partition walls formed in parallel to the data electrodes on each of the dielectric layers. A phosphor layer is formed on the side surface of the partition wall.

  Then, the front plate and the back plate are arranged opposite to each other so that the display electrode and the data electrode are three-dimensionally crossed and sealed, and a discharge gas is sealed in the internal discharge space. Here, a discharge cell is formed in a portion where the display electrode and the data electrode face each other.

  Each electrode is provided with a driving means for applying a voltage to drive, specifically, a scanning electrode driving means for applying a voltage to the scanning electrode, a sustaining electrode driving means for the sustaining electrode, and a data electrode. Is provided with data electrode driving means.

  In each discharge cell of the panel having such a configuration, a gas discharge is caused by applying a voltage to each electrode by each driving means, and the phosphors of each color of RGB of the discharge cell are excited to emit light by ultraviolet rays generated thereby. Color display.

  As a method of driving the panel, a subfield method, that is, a method of performing gradation display by combining subfields to emit light after dividing one field period into a plurality of subfields. Also, among the subfield methods, for example, Patent Document 1 discloses a novel driving method in which light emission not related to gradation expression is reduced as much as possible to suppress an increase in black luminance and an contrast ratio is improved.

  The subfield method will be briefly described below. Each subfield has an initialization period, an address period, and a sustain period. In addition, the initializing period is an initializing operation for all the cells that perform initializing discharge for all the discharge cells that perform image display, or selectively for the discharge cells that have undergone sustain discharge in the immediately preceding subfield. One of the selective initializing operations for causing the igniting discharge is performed.

  First, during the all-cell initialization period, all discharge cells perform an initializing discharge all at once, erasing the wall charge history for each previous discharge cell, and forming the wall charge necessary for the subsequent address operation. To do. In addition, priming (priming agent for discharge) for reducing discharge delay (for example, the time from application of an address pulse to the data electrode in the address period until address discharge) and stably generating address discharge = It has the function of generating excited particles.

  In the subsequent address period, a scan pulse is sequentially applied to the scan electrodes, and an address pulse corresponding to an image signal to be displayed is applied to the data electrodes, thereby selectively causing an address discharge between the scan electrodes and the data electrodes. , Selective wall charge formation. In the sustain period, a predetermined number of sustain pulses corresponding to the luminance weight are applied between the scan electrodes and the sustain electrodes, and the discharge cells in which the wall charges are formed by the address discharge are selectively discharged to emit light. In the selective initializing period, a weak initializing discharge occurs in the discharge cells that have undergone the sustain discharge in the sustain period of the previous subfield, and wall charges necessary for the subsequent address operation are formed.

On the other hand, the discharge cells that did not perform the address discharge and the sustain discharge in the previous subfield are not discharged, and the wall charge state at the end of the initialization period of the previous subfield is maintained as it is. The initializing operation of the selective initializing subfield is a selective initializing operation in which initializing discharge is performed in the discharge cells that have undergone sustain discharge in the previous subfield.
JP 2000-242224 A

  Since the priming generated by the discharge decreases with the passage of time, the priming generated by the initialization discharge is insufficient for the address discharge in which a long time has elapsed from the initialization discharge, and the discharge delay increases. Therefore, in order to perform the address operation stably, the address time for one discharge cell is set long, and as a result, there is a problem that the address period becomes too long.

  The panel driving method and the display device thereof according to the present invention have been made in view of the above problems, and an object thereof is to guarantee a stable writing operation.

  In the panel driving method of the present invention, one field period has an initializing period, an address period, and a sustaining period in which an all-cell initializing operation is performed in which initializing discharge is performed on all discharge cells that perform image display. A cell initializing subfield, and a selective initializing subfield having an initializing period, an addressing period, and a sustaining period for performing a selective initializing operation for performing initializing discharge on a specific discharge cell. A driving method of a plasma display panel that performs multi-grayscale display by controlling light emission or non-light emission of a discharge cell, and does not emit light in a sustain period immediately before a selective initialization subfield for controlling light emission of the discharge cell in the sustain period When two or more subfields to be controlled are consecutive, when writing to one discharge cell in the address period of the selective initialization subfield Is to set longer than the writing time to the one discharge cell of the write period of the other subfields. This driving method makes it possible to guarantee a stable write operation.

  Further, the panel driving method of the present invention is such that the APL (average luminance level of the image signal to be displayed: for example, when the APL is 0%, the entire panel is not displayed, ie, all black is displayed, and when the APL is 100%, the entire panel is displayed. In other words, it is desirable to reduce the number of all-cell initialization subfields when the white display is low, and to increase the number of all-cell initialization subfields when APL is high. With this driving method, it is possible to provide a driving method of a plasma display panel that suppresses the increase in black luminance and shortens the driving period, and the time difference between subfields constituting one field can be set small. .

  The present invention also relates to a display device for realizing the driving method as described above. A subfield for non-emission control in the sustain period immediately before the selective initialization subfield for controlling emission of discharge cells in the sustain period is provided. When two or more consecutive, a control signal that makes the address time to one discharge cell in the address period of the selective initialization subfield longer than the address time to one discharge cell in the address period of the other subfield is scanned. Write time control means for transmitting to scan electrode driving means for driving electrodes and data electrode driving means for driving data electrodes is provided. With this display device, a stable write operation can be guaranteed.

  Further, the APL detection means and the APL control means for reducing the number of all-cell initialization subfields when the APL of the image signal to be displayed is low and increasing the number of all-cell initialization subfields when the APL is high are provided. It is desirable to include. With this display device, it is possible to provide a plasma display panel driving method that suppresses the increase in black luminance and shortens the driving period, and the time difference between the subfields constituting one field can be set small. .

  According to the present invention, it is possible to provide a method for driving a plasma display panel and a display device for the same, in which a stable writing operation is ensured and an increase in black luminance is suppressed.

  Hereinafter, a panel driving method according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a perspective view showing a main part of a panel used in Embodiment 1 of the present invention. The panel 1 is configured such that a glass front substrate 2 and a back substrate 3 are disposed to face each other and a discharge space is formed therebetween. On the front substrate 2, a plurality of scanning electrodes 4 and sustaining electrodes 5 constituting display electrodes are formed in parallel with each other. A dielectric layer 6 is formed so as to cover the scan electrode 4 and the sustain electrode 5, and a protective layer 7 is formed on the dielectric layer 6.

  A plurality of data electrodes 9 covered with an insulator layer 8 are provided on the back substrate 3, and a partition wall 10 is provided in parallel with the data electrodes 9 on the insulator layer 8 between the data electrodes 9. Yes. A phosphor layer 11 is provided on the surface of the insulator layer 8 and the side surfaces of the partition walls 10. The front substrate 2 and the rear substrate 3 are arranged to face each other in the direction in which the scan electrode 4 and the sustain electrode 5 intersect with the data electrode 9, and in the discharge space formed between them, for example, neon And a mixed gas of xenon.

  FIG. 2 is an electrode array diagram of the panel used in the first embodiment of the present invention. N scan electrodes SCN1 to SCNn (scan electrode 4 in FIG. 1) and n sustain electrodes SUS1 to SUSn (sustain electrode 5 in FIG. 1) are alternately arranged in the row direction, and m data electrodes in the column direction. D1 to Dm (data electrodes 9 in FIG. 1) are arranged. A discharge cell is formed at a portion where a pair of scan electrode SCNi and sustain electrode SUSi (i = 1 to n) and one data electrode Dj (j = 1 to m) intersect, and the discharge cell is in the discharge space. M × n are formed.

  FIG. 3 is a configuration diagram of a plasma display device using the panel driving method according to the first embodiment of the present invention. The plasma display device includes a panel 1, a data electrode drive circuit 12, a scan electrode drive circuit 13, a sustain electrode drive circuit 14, a timing generation circuit 15, an AD (analog / digital) converter 18, a scan number conversion unit 19, and a subfield. A conversion unit 20 and a power supply circuit (not shown) are provided.

  In FIG. 3, the image signal sig is input to the AD converter 18. Further, the horizontal synchronizing signal H and the vertical synchronizing signal V are given to the timing generation circuit 15, the AD converter 18, the scanning number conversion unit 19, and the subfield conversion unit 20. The AD converter 18 converts the image signal sig into digital image data, and supplies the image data to the scanning number conversion unit 19. The scanning number conversion unit 19 converts the image data into image data corresponding to the number of pixels of the panel 1 and supplies the image data to the subfield conversion unit 20.

  The subfield conversion unit 20 divides the image data of each pixel into a plurality of bits corresponding to a plurality of subfields, and outputs the image data for each subfield to the data electrode driving circuit 12. The data electrode drive circuit 12 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes.

  Timing generating circuit 15 generates a timing signal based on horizontal synchronizing signal H and vertical synchronizing signal V, and supplies the timing signal to data electrode driving circuit 12, scan electrode driving circuit 13, and sustain electrode driving circuit 14, respectively. Scan electrode drive circuit 13 supplies a drive waveform to scan electrodes SCN1 to SCNn based on the timing signal, and sustain electrode drive circuit 14 supplies a drive waveform to sustain electrodes SUS1 to SUSn based on the timing signal. Here, the timing generation circuit 15 corresponds to address time control means, and outputs the address time to one discharge cell in the address period for each subfield to the data electrode drive circuit 12 and the scan electrode drive circuit 13.

  Next, a method for driving the panel will be described. In the first embodiment, one field is divided into 14 subfields (SF1, SF2,..., SF14), and each subfield is (1, 2, 4, 8, 16, 32, 56, 72). , 80, 8, 24, 44, 72, and 92) have luminance weights in the display order. In order to prevent flicker when an image signal of 50 Hz is input, this luminance weight constitutes two subfield groups in which the luminance weight increases in the rear subfield in one field. .

  FIG. 4 is a diagram showing combinations of display gradations and subfields that emit light to express the gradations. Here, the subfield indicated by “1” is a subfield that emits light, and the subfield indicated by “0” is a subfield that does not emit light. FIG. 4 shows a range of gradation values from “0” to “47” in the total number of gradations 512.

  Next, a driving waveform for driving the panel and its operation will be described. FIG. 5 is a drive waveform diagram applied to each electrode of the panel in the present embodiment, and FIG. 6 is a configuration diagram of subfields constituting one field. FIG. 7A is a waveform diagram of signals applied to the respective electrodes during the first SF, second SF, and fifth SF to fourteenth SF write periods, and FIG. 7B is a third SF and fourth SF write. It is a wave form diagram of a signal impressed to each electrode in a period. Here, the first SF, the fifth SF, and the tenth SF are all-cell initializing subfields that perform the all-cell initializing operation in the initializing period, and the other subfields are selected to perform the selective initializing operation in the initializing period. Initialization subfield.

  In the present embodiment, the address time to one discharge cell from the first SF to the 14th SF is set to (1.8 μs (= microsecond), 1.8 μs, respectively) so as not to impair the stability of the address discharge. 2.3 μs, 2.3 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.8 μs, 1.8 μs) did.

  In the initializing period of the first SF, the data electrodes D1 to Dm and the sustain electrodes SUS1 to SUSn are held at 0 (V), and rise toward the voltage Vr (V) exceeding the discharge start voltage with respect to the scan electrodes SCN1 to SCNn. Apply the ramp voltage. Thereafter, sustain electrodes SUS1 to SUSn are maintained at positive voltage Vh (V), and a ramp voltage that decreases toward voltage Va (V) is applied to scan electrodes SCN1 to SCNn. Then, two weak initializing discharges are caused in all the discharge cells, wall charges necessary for the subsequent address operation are formed, and priming occurs in all the discharge cells.

  In the subsequent address period, scan electrodes SCN1 to SCNn are temporarily held at Vs (V). Next, a positive address pulse voltage Vw (V) is applied to the data electrode Dk of the discharge cell to be displayed in the first row among the data electrodes D1 to Dm, and the scan pulse voltage is applied to the scan electrode SCN1 in the first row. Vb (V) is applied. Then, address discharge occurs between scan electrode SCN1, data electrode Dk (k = 1 to m), and sustain electrode SUS1, and wall charges necessary for the sustain discharge following this discharge cell are accumulated. On the other hand, wall charges are not accumulated in the discharge cells to which the positive address pulse voltage Vw (V) is not applied. The above address operation is sequentially performed until the discharge cell in the nth row, and the address period ends.

  In the subsequent sustain period, first, sustain electrodes SUS1 to SUSn are returned to 0 (V), and positive sustain pulse voltage Vm (V) is applied to scan electrodes SCN1 to SCNn. At this time, in the discharge cell in which the address discharge has occurred, a voltage due to the wall charges is added to the sustain pulse voltage Vm (V), and the sustain discharge is generated exceeding the discharge start voltage. Then, the wall charges with reversed polarity accumulate in the discharge cells. Subsequently, when the scan electrodes SCN1 to SCNn are returned to 0 (V) and a positive sustain pulse voltage Vm (V) is applied to the sustain electrodes SUS1 to SUSn, a sustain discharge occurs in the discharge cell and the polarity of the wall charges is reversed. To do.

  Thereafter, similarly, by applying sustain pulses alternately to scan electrodes SCN1 to SCNn and sustain electrodes SUS1 to SUSn, sustain discharge is continuously performed in the discharge cells in which the address discharge has occurred in the address period. It should be noted that a large amount of priming occurs in the discharge cell in which the sustain discharge has occurred along with the sustain discharge at this time.

  In the initialization period of the second SF, sustain electrodes SUS1 to SUSn are held at Vh (V), data electrodes D1 to Dm are held at 0 (V), and scan electrodes SCN1 to SCNn are supplied with voltage Va (V). Apply ramp-down voltage. Then, in a discharge cell that has undergone a sustain discharge in the sustain period of the previous subfield, a weak initializing discharge occurs, and wall charges necessary for the subsequent address operation are formed.

  On the other hand, the discharge cells that did not perform the address discharge and the sustain discharge in the previous subfield are not discharged, and the wall charge state at the end of the initialization period of the previous subfield is maintained as it is. As described above, the initializing operation in the selective initializing subfield is a selective initializing operation in which initializing discharge is performed in the discharge cells that have undergone sustain discharge in the previous subfield.

  As shown in FIG. 4, subfields in which two or more non-light emitting subfields continue immediately before the light emitting subfield are the third SF, the fourth SF, the fifth SF, the tenth SF, and the eleventh SF. In order to perform stable address discharge in these subfields, the addressing time to one discharge cell is set to other subfields (selective initialization subfields in which two or more non-light emitting subfields do not continue immediately before the light emitting subfields). (Or all-cell initialization subfield) is set longer than the addressing time for one discharge cell to compensate for the discharge delay due to insufficient priming, or perform all-cell initialization operation in the initialization period, and reduce the discharge delay by priming. It is effective to do.

  These operations are executed by sending control signals from the timing generation circuit 15 to the data electrode drive circuit 12 and the scan electrode drive circuit 13.

  In the third SF and the fourth SF, by setting the addressing time to one discharge cell to 2.3 μs, which is longer than the addressing time 1.8 μs to one discharge cell of another subfield, a discharge delay due to insufficient priming occurs. In addition, stable address discharge can be performed. In this operation, as shown in FIG. 7B, a signal is transmitted from the timing generation circuit 15 to the data electrode drive circuit 12 and the scan electrode drive circuit 13 so that the application time of each drive pulse is 2.3 μs. . That is, the signals sent from the timing generation circuit 15 to the data electrode drive circuit 12 and the scan electrode drive circuit 13 in the address period of each subfield are different, and as a result, the address period of each subfield may be different.

  Further, in the fifth SF and the tenth SF, priming is generated by performing the all-cell initializing operation in the initializing period, so that stable address discharge with a small discharge delay can be performed.

  Furthermore, since the priming of the all-cell initializing operation performed during the initializing period of the tenth SF remains, the eleventh SF can perform stable address discharge with a small discharge delay.

  Here, the reason why the third SF and the fourth SF are set in the selective initialization subfield, the address time for one discharge cell is set to 2.3 μs, and the fifth SF is set in the all-cell initialization subfield will be described again. Suppose that the third SF is an all-cell initializing subfield, and the addressing time for one discharge cell is set to 2.3 μs in the fourth and fifth SFs in a selective initializing subfield. In this case, in the third SF, a stable address discharge with a small discharge delay can be performed by performing the all-cell initialization operation. In the fourth SF and the fifth SF, the address time for one discharge cell is set to another subfield. By making it longer, stable address discharge can be performed even if a discharge delay due to insufficient priming occurs.

  However, by extending the address time to one discharge cell of the fourth SF and the fifth SF, the operation time of the address discharge becomes longer, and the priming remaining in the surrounding cells is absorbed, and the surrounding cells are address-discharged. A discharge delay occurs when performing the operation, and there is a side effect that the surrounding cells cannot perform a stable address discharge. Once an address failure occurs, the address discharge up to the ninth SF immediately before the tenth SF for performing the next all-cell initializing operation becomes unstable.

  On the other hand, in the present embodiment, the third SF and the fourth SF are set in the selective initialization subfield, the address time for one discharge cell is set to 2.3 μs, and the fifth SF is set in the all-cell initialization subfield. By extending the address time for one discharge cell of the third SF and the fourth SF, the operation time of the address discharge becomes longer, and the priming remaining in the surrounding cells is absorbed, and the surrounding cells perform the address discharge. Even when a discharge delay occurs, priming occurs in all cells during the fifth SF in which the next all-cell initializing operation is performed. Therefore, stable address discharge can be performed in subfields after the fifth SF. . As described above, the first embodiment is the best mode capable of stably performing the address discharge of the surrounding cells.

  In the present embodiment, it is assumed that one field is composed of 14 subfields, but the number of subfields and the luminance weight of each subfield are not limited.

(Embodiment 2)
FIG. 8 is a configuration diagram of a plasma display device using the panel driving method according to the second embodiment of the present invention.

  As in (Embodiment 1), the plasma display device according to the present embodiment includes a panel 1, a data electrode drive circuit 12, a scan electrode drive circuit 13, a sustain electrode drive circuit 14, a timing generation circuit 15, an AD converter 18, A scanning number conversion unit 19 and a subfield conversion unit 20 are provided. A significant difference from the first embodiment is that an APL (average luminance level) detection unit 30 is provided. Here, the APL detection unit 30 corresponds to an APL detection unit, and the timing generation circuit 15 corresponds to an APL control unit.

  In FIG. 8, the image signal sig is input to the AD converter 18, and the APL detection unit 30 detects the average luminance level of the image data. Timing generating circuit 15 generates a timing signal based on horizontal synchronizing signal H and vertical synchronizing signal V, and supplies the timing signal to data electrode driving circuit 12, scan electrode driving circuit 13, and sustain electrode driving circuit 14, respectively. Scan electrode drive circuit 13 supplies a drive waveform to scan electrodes SCN1 to SCNn based on the timing signal, and sustain electrode drive circuit 14 supplies a drive waveform to sustain electrodes SUS1 to SUSn based on the timing signal. Here, the timing generation circuit 15 determines the initialization operation of each subfield constituting one field based on the APL output from the APL detection unit 30 as either all-cell initialization or selective initialization, The number of all-cell initialization operations in one field is controlled, and the address time to one discharge cell in each subfield is controlled.

  Next, the subfield configuration of the driving method of the present embodiment will be described. In the present embodiment, one field is divided into 11 subfields (SF1, SF2,..., SF11), and each subfield is (1, 2, 4, 6, 12, 22, 36, 60). , 88, 120, 160) have luminance weights in the display order.

  FIG. 9 is a diagram showing a combination of display gradations and subfields that emit light to express the gradations. Here, the subfield indicated by “1” is a subfield that emits light, and the subfield indicated by “0” is a subfield that does not emit light. FIG. 9 shows a range of gradation values from “0” to “47” in the total number of gradations 512.

  FIG. 10 is a diagram showing a subfield configuration of the panel driving method according to the embodiment of the present invention, and the subfield configuration is switched based on the APL of the image signal to be displayed. FIG. 10A shows a configuration used for an image signal having an APL of 0 to 2%, which is an all-cell initialization subfield that performs an all-cell initialization operation only during the initialization period of the first SF, and the second SF to the second SF. 11SF is a selective initialization subfield for performing a selective initialization operation during the initialization period. FIG. 10B shows a configuration used when an APL is 2 to 10% of an image signal. The first SF and the fifth SF are all-cell initializing subfields, and the other subfields are selective initializing subfields. Yes.

  FIG. 10C shows a configuration used for an image signal with APL of 10 to 100%. The first SF, the third SF, and the fifth SF are all-cell initializing subfields, and the other subfields are selective initializing subfields. It has become. FIG. 11 shows the relationship between the above-described subfield configuration and APL. FIG. 11 also shows the address time for one discharge cell at the same time.

  As described above, in the present embodiment, when displaying an image with a high APL, it is considered that there is no black display region or a small area. We are trying to make it. Conversely, when an image with a low APL is displayed, the black image display area is considered to be wide, so the number of all-cell initializations is reduced and the black display quality is improved. Therefore, even if there is a region with high luminance, if the APL is low, it is possible to display an image with low luminance and high contrast in the black display region.

  As shown in FIG. 9, subfields in which two or more non-light-emitting subfields continue immediately before the light-emitting subfield are the third SF, the fifth SF, and the sixth SF. In order to perform stable address discharge in these subfields, the addressing time to one discharge cell is set to other subfields (selective initialization subfields in which two or more non-light emitting subfields do not continue immediately before the light emitting subfields). (Or all-cell initialization subfield) is set longer than the addressing time for one discharge cell to compensate for the discharge delay due to insufficient priming, or perform all-cell initialization operation in the initialization period, and reduce the discharge delay by priming. It is effective to do.

  When the APL is 10 to 100%, the third SF and the fifth SF can perform stable address discharge with a small discharge delay because priming occurs by performing the all-cell initializing operation in the initializing period. In addition, since the priming of the all-cell initialization operation performed during the initialization period of the fifth SF remains, the sixth SF can perform a stable address discharge with a small discharge delay. Further, although not shown in FIG. 9, in the gradation after the gradation value “48”, the seventh SF and the eighth SF exist as subfields in which two non-light-emitting subfields continue immediately before the light-emitting subfield. In this case, since the subfield that emits light immediately before is a subfield having a relatively large luminance weight, priming after the sustain discharge remains to some extent, so that the all-cell initializing operation or one discharge cell is transferred during the initializing period. Even if the address time is not set long, stable address discharge can be performed.

  When the APL is 2 to 10%, the fifth SF can perform stable address discharge with a small discharge delay because priming occurs by performing the all-cell initialization operation in the initialization period. In addition, by setting the third SF to 2.3 μs, which is longer than the address time of 1.8 μs to one discharge cell in another subfield, stable address discharge can be performed even if a discharge delay occurs due to insufficient priming. . The other subfields are the same as in the case of APL 10 to 100%.

  Here, the reason why the subfield for performing the all-cell initializing operation in the initializing period in the first and fifth SFs when the APL is 2 to 10% will be described. Assume that the first SF and the third SF are all-cell initializing subfields, and that the fifth SF is a selective initializing subfield and the addressing time for one discharge cell is set to 2.3 μs. In this case, in the third SF, it is possible to perform a stable address discharge with a small discharge delay by performing the all-cell initialization operation, and in the fifth SF, the address time to one discharge cell is made longer than the other subfields. Thus, stable address discharge can be performed even if a discharge delay due to insufficient priming occurs.

  However, when the address time for one discharge cell of the fifth SF is lengthened, the operation time of the address discharge is lengthened and the priming remaining in the surrounding cells is absorbed, and the surrounding cells perform the address discharge. Discharge delay occurs, and there is a side effect that surrounding cells cannot perform stable address discharge. Once an address failure occurs, the address discharge up to the eleventh SF becomes unstable because there is no subfield for performing the all-cell initialization operation in that field.

  On the other hand, in the present embodiment, the third SF is set to the selective initialization subfield, the addressing time for one discharge cell is set to 2.3 μs, and the fifth SF is set to the all-cell initialization subfield. By extending the address time to one discharge cell of the third SF, the operation time of the address discharge is lengthened and the priming remaining in the surrounding cells is absorbed, and the discharge occurs when the surrounding cells perform the address discharge. Even if a delay occurs, priming occurs in all cells during the fifth SF in which the next all-cell initializing operation is performed. Therefore, stable address discharge can be performed in subfields after the fifth SF.

  Thus, the present embodiment is the best mode in which address discharge of surrounding cells can be performed stably. In other words, when all cell initialization subfields are reduced as APL decreases, selection is made from all cell initialization subfields other than the fastest all cell initialization subfield in the display order and the slowest all cell initialization subfield in the display order. In the present embodiment, switching to the initialization subfield means that, in the first SF, the third SF, and the fifth SF, which are all cell initialization subfields, it is possible to eliminate the third SF all cell initialization operation. This is an effective technique for stably performing address discharge while suppressing the rise.

  When APL is 0 to 2%, the third and fifth SFs are set to 2.1 μs, which is longer than the write time of 1.8 μs to one discharge cell of another subfield, Stable address discharge can be performed even if a discharge delay due to insufficient priming occurs.

  In the present embodiment, the address time for one discharge cell is set to 2.1 μs, which is longer than the other subfields in the third SF and the fifth SF. However, in the case of APL 2 to 10%, 1 The address time for one discharge cell is shorter than 2.3 μs. As described above, by increasing the address time for one discharge cell, the priming remaining in the surrounding cells is absorbed, and a discharge delay occurs when the surrounding cells perform the address discharge. This is to reduce the side effect that the surrounding cells cannot perform stable address discharge. In addition, in an image signal with a low APL of about 0 to 2% APL, since there is a high probability of using a small luminance weight, all cells are initialized during the initialization period of the first SF so that stable address discharge can be performed in the low gradation portion. Set the action.

  In the present embodiment, it is assumed that one field is composed of 11 subfields, but the number of subfields and the luminance weight of each subfield are not limited.

  According to the panel driving method of the present invention, it is possible to suppress an increase in black luminance while guaranteeing a stable writing operation, which is useful as an image display device using the panel.

1 is a perspective cross-sectional view showing a main part of a plasma display panel used in Embodiment 1 of the present invention. The figure which shows the electrode arrangement of the panel The figure which shows the structure of the display apparatus in the 1st Embodiment of this invention. The figure which shows a part of light emission pattern of each subfield in the display device The figure which shows the drive waveform applied to each electrode of a panel in the display apparatus The figure which shows the outline of the time structure of the subfield which comprises 1 field in the display apparatus. The figure which shows the drive waveform of the writing period in the display apparatus The figure which shows the structure of the display apparatus in the 2nd Embodiment of this invention. The figure which shows a part of light emission pattern of each subfield in the display device The figure which shows the outline of the time structure of the subfield which comprises 1 field in the display apparatus. The figure which shows the relationship of the write time to one discharge cell according to APL in the same display device

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Panel 2 Front substrate 3 Back substrate 4 Scan electrode 5 Sustain electrode 9 Data electrode 12 Data electrode drive circuit 13 Scan electrode drive circuit 14 Sustain electrode drive circuit 15 Timing generation circuit 30 APL detection part

Claims (4)

An all-cell initializing subfield having an initializing period, an address period, and a sustaining period for performing an all-cell initializing operation in which one field period performs initializing discharge for all discharge cells that perform image display; A selective initializing subfield having a selective initializing operation for performing initializing discharge with respect to the discharge cells, an address period, and a sustain period, and controlling or not controlling the discharge cells in the sustain period. A driving method of a plasma display panel that performs multi-grayscale display by controlling light emission, and has two subfields that perform non-emission control in the sustain period immediately before the selective initialization subfield that controls light emission of the discharge cells in the sustain period. In the case where the above is continued, the address time for one discharge cell in the address period of the selective initialization subfield is set to the other sub-fields. The driving method of the plasma display panel and setting longer than the writing time to the one discharge cell of the write period of Rudo. The number of all cell initialization subfields is reduced when the APL of an image signal to be displayed is low, and the number of all cell initialization subfields is increased when the APL is high. Driving method of plasma display panel. All of the one-field period performs image display for discharge cells formed at positions where scan electrodes and sustain electrodes arranged in parallel on the same substrate intersect with data electrodes arranged on another substrate. An initializing discharge is performed on a specific discharge cell, and an all-cell initializing subfield having an initializing period, an address period, and a sustaining period for performing an initializing operation for causing an initializing discharge to the discharge cells A selective initialization subfield having an initializing period for performing selective initializing operation, an address period, and a sustaining period, and performing multi-grayscale display by controlling emission or non-emission of the discharge cells in the sustaining period. There are two subfields for performing non-emission control in the sustain period immediately before the selective initialization subfield for controlling emission of discharge cells in the sustain period. In the case of continuous, the control signal for making the address time to one discharge cell in the address period of the selective initialization subfield longer than the address time to one discharge cell in the address period of the other subfield, A display device comprising: a scanning electrode driving means for driving an electrode; and a writing time control means for transmitting to a data electrode driving means for driving the data electrode. APL detection means and APL control means for reducing the number of all-cell initialization subfields when the APL of the image signal to be displayed is low and increasing the number of all-cell initialization subfields when the APL is high The display device according to claim 3, further comprising:

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