JP2009265465A - Plasma display panel display and method for driving the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To stably display an image at a high speed by generating a stable writing discharge, even in a high-definition PDP display. <P>SOLUTION: In a method for driving a plasma display panel, one field includes a plurality of subfields having an initialization period for generating an initialization discharge by a discharge cell, a writing period for generating a writing discharge, and a sustained period for generating a sustained discharge. In the initialization period, a first voltage is applied to a sustain electrode, a reference voltage is applied to a data electrode and a rising waveform voltage is applied to a scanning electrode. A voltage higher than the first voltage is applied to the sustain electrode, a voltage lower than the reference voltage is applied to the data electrode and a falling waveform voltage is applied to the scanning electrode. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a plasma display panel display device used for a wall-mounted television or a large monitor and a driving method thereof.

  Currently, an AC surface discharge type PDP display device is a representative example of a plasma display panel (hereinafter abbreviated as “PDP”) display device. In the AC surface discharge type PDP display device, a large number of discharge cells are formed by arranging a front substrate and a rear substrate to face each other. The configuration of the AC surface discharge type PDP display device will be described below.

  On the front substrate, a plurality of pairs of display electrodes including a pair of scan electrodes and sustain electrodes are formed in parallel to each other. A dielectric layer and a protective layer are laminated on the front substrate so as to cover the display electrode pair. A plurality of data electrodes are formed on the back substrate so as to be parallel to each other. A dielectric layer is formed on the back substrate so as to cover the data electrodes, and a grid-like partition is further formed thereon. In a space formed by the upper surface of the dielectric layer and the side surfaces of the partition walls, phosphor layers that emit red, green, and blue light are provided.

  The front substrate and the rear substrate formed as described above are arranged to face each other with a minute discharge space so that the display electrode pair and the data electrode intersect three-dimensionally, and the outer periphery thereof is sealed with a sealing material. Worn. A discharge gas is sealed in the internal discharge space. In this way, discharge cells are formed at the intersections between the display electrode pairs and the data electrodes. In each discharge cell, ultraviolet light is generated by gas discharge, and each phosphor is excited to emit light by this ultraviolet light to perform color display.

  As a driving method of the PDP display device, a subfield method, that is, a method in which one field period is divided into a plurality of subfields and gradation display is performed by a combination of subfields to emit light is generally used. Each subfield has an initialization period, an address period, and a sustain period.

  In the initialization period, a predetermined voltage is applied to the scan electrode and sustain electrode that are the display electrode pair to generate an initialization discharge, and wall charges necessary for the next address discharge are formed on each electrode. In the address period, scan pulses are sequentially applied to the scan electrodes, and address pulses are applied to the data electrodes of the discharge cells to be lit to generate an address discharge, thereby forming wall charges on each electrode. In the sustain period, sustain pulses are alternately applied to the scan electrode and the sustain electrode, and a sustain discharge is generated in the discharge cell in which the address discharge has occurred, thereby exciting the discharge gas. The phosphor layer is excited by ultraviolet rays generated when the excited discharge gas transitions to a stable state, and visible light is generated, thereby performing image display.

  In such a driving method of the PDP display device, the voltage of the scan pulse and the voltage of the sustain electrode applied to the scan electrode in the address period are set to the voltage of the scan electrode and the voltage of the sustain electrode at the end of the application of the initialization waveform. A method has been disclosed in which the withstand voltage of the data electrode driving circuit is lowered to reduce the cost by setting the voltage lower than that, and the power consumption of the data electrode driving circuit is reduced (see, for example, Patent Document 1).

In addition, a method is disclosed in which the number of times that the initializing discharge is generated in all the discharge cells in the initializing period is limited, thereby reducing the light emission not related to the gradation display as much as possible and improving the contrast ratio (for example, , See Patent Document 2).
JP 2000-305510 A JP 2000-242224 A

  However, if the number of times that the initializing discharge is generated in all the discharge cells is limited, the address discharge becomes unstable, so that no sustain discharge occurs in the discharge cells that should be sustained discharge, or in the discharge cells that should not be sustained discharge. There was a risk of malfunctions such as In particular, in recent years, this tendency has become stronger as the PDP display device has been improved in definition and the discharge cells have become finer. In addition, as the number of scanning electrodes increases due to higher definition, higher driving speed is required.

  The present invention has been made in view of the above problems, and even a high-definition PDP display device can generate a stable address discharge and can perform a high-speed and stable image display. And a driving method thereof.

  In order to achieve the above object, a PDP display device and a driving method thereof according to the present invention include a PDP display device including a plurality of discharge cells each having a display electrode pair including a scan electrode and a sustain electrode, and a data electrode, and a driving method thereof. A plurality of subfields each having an initializing period for generating an initializing discharge in the discharge cell, an addressing period for generating an addressing discharge, and a sustaining period for generating a sustaining discharge constitute one field. A first voltage is applied to the sustain electrode, a reference voltage is applied to the data electrode, an upward ramp waveform voltage is applied to the scan electrode, a voltage higher than the first voltage is applied to the sustain electrode, and a reference is applied to the data electrode. A voltage lower than the voltage is applied, and a downward ramp waveform voltage is applied to the scan electrode. By this method, even in a high-definition PDP display device, stable address discharge can be generated and stable image display can be performed at high speed.

  Further, in the initialization period, a second voltage higher than the first voltage, an upward ramp waveform voltage rising from the second voltage to a third voltage higher than the second voltage, and the third voltage are sequentially applied to the sustain electrodes. You may apply.

  According to the present invention, it is possible to provide a PDP display device capable of generating stable address discharge and capable of performing stable and high-speed image display even in a high-definition PDP display device, and a driving method thereof. Is possible.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing the structure of PDP 10 according to Embodiment 1 of the present invention. As shown in FIG. 1, a plurality of display electrode pairs 14 including scan electrodes 12 and sustain electrodes 13 are formed on a glass front substrate 11 so as to be parallel to each other. A dielectric layer 15 and a protective layer 16 are laminated on the front substrate 11 so as to cover the display electrode pair 14. A plurality of data electrodes 22 are formed on the back substrate 21 so as to be parallel to each other. Further, a dielectric layer 23 is formed on the back substrate 21 so as to cover the data electrodes 22, and further, a grid-like partition wall 24 is formed thereon. In the space formed by the upper surface of the dielectric layer 23 and the side surface of the partition wall 24, a phosphor layer 25 that emits red, green, and blue light is provided.

  The front substrate 11 and the back substrate 21 formed as described above are arranged to face each other with a minute discharge space so that the display electrode pair 14 and the data electrode 22 are three-dimensionally intersected, It is sealed with a sealing material such as glass frit. In the internal discharge space, for example, a mixed gas of neon and xenon is sealed as a discharge gas and divided into a plurality of spaces by the partition walls 24. In this way, the PDP 10 according to the first embodiment is configured, and discharge cells are formed at the portions where the display electrode pairs 14 and the data electrodes 22 intersect. In each discharge cell, each phosphor is excited to emit light by ultraviolet rays generated by gas discharge to perform color display.

  FIG. 2 is an electrode array diagram of PDP 10 according to the first exemplary embodiment of the present invention. As shown in FIG. 2, in the PDP 10 according to the first embodiment, scan electrodes 12 (SC1 to SCn) and sustain electrodes 13 (SU1 to SUn) are arranged in the row direction, and data electrodes 22 (D1 to Dm). Are arranged in the column direction. In FIG. 2, the discharge cells are formed, for example, at a portion where a pair of scan electrodes SC2 and sustain electrodes SU2 and one data electrode D2 intersect, and as a whole, m × n discharge cells are formed. Become.

  Next, a driving voltage waveform and its operation for driving the PDP 10 according to the first embodiment will be described.

  In the PDP display device using the PDP 10 according to the first embodiment, the subfield method, that is, one field period is divided into a plurality of subfields, and light emission / non-light emission of each discharge cell is controlled for each subfield. Is used to perform gradation display. Each subfield has an initialization period, an address period, and a sustain period.

  In the initialization period, a predetermined voltage is applied to the scan electrode 12 and the sustain electrode 13 which are the display electrode pair 14 to generate an initialization discharge, and wall charges necessary for the next address discharge are formed on each electrode. The initializing operation in the first embodiment includes an initializing operation for generating initializing discharge in all discharge cells (hereinafter abbreviated as “all cell initializing operation”), and a sustain discharge in the immediately preceding subfield. There is an initialization operation (hereinafter abbreviated as “selective initialization operation”) in which an initialization discharge is generated only in the performed discharge cells. For example, one field is divided into 10 subfields (first SF, second SF,..., 10th SF), and each subfield has a luminance weight (1, 2, 3, 6, 11, 18, 30). , 44, 60, 80). In the initialization period of the first SF, the all-cell initialization operation is performed, and in the initialization period of the second SF to the tenth SF, the selective initialization operation is performed.

  In the address period, scan pulses are sequentially applied to the scan electrodes 12, and address pulses are selectively applied to the data electrodes 22 of the discharge cells to be lit to generate an address discharge, thereby forming wall charges on the electrodes. To do.

  In the sustain period, a number of sustain pulses proportional to the luminance weight are alternately applied to the scan electrode 12 and the sustain electrode 13 to generate a sustain discharge proportional to the luminance weight in the discharge cell in which the address discharge is generated. Excites the gas. The phosphor layer 25 is excited by ultraviolet rays generated when the excited discharge gas transitions to a stable state, and visible light is generated, thereby performing image display.

  FIG. 3 is a waveform diagram of the drive voltage applied to each electrode of PDP 10 in the first exemplary embodiment of the present invention. Hereinafter, the subfield for performing the all-cell initialization operation and the subfield for performing the selective initialization operation in the first embodiment will be described in detail with reference to FIG. In FIG. 3, the subfield in which the all-cell initializing operation is performed is the first SF, and the subfield in which the selective initializing operation is performed is the second SF. However, the present invention is not limited to this.

<Subfield for initializing all cells>
In the initialization period T1, a reference voltage of 0 V is applied to the data electrodes D1 to Dm, and 0 V is applied to the sustain electrodes SU1 to SUn as a first voltage. Scanning electrodes SC1 to SCn are applied with an upward ramp waveform voltage that gradually increases from voltage Vi1 that is equal to or lower than the discharge start voltage to voltage Vi2 that exceeds the discharge start voltage. During this time, a weak initializing discharge occurs between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. Thereby, negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

  In the initialization period T2, a voltage Vt lower than the reference voltage 0V is applied to the data electrodes D1 to Dm. For this reason, the positive wall voltage on the data electrodes D1 to Dm is higher by the absolute value of the voltage Vt than when the reference voltage 0V is applied. Further, the second voltage Ve2 higher than the first voltage 0V is applied to the sustain electrodes SU1 to SUn. Scanning electrodes SC1 to SCn are applied with a downward ramp waveform voltage that gradually decreases from voltage Vi3 that is equal to or lower than the discharge start voltage to voltage Vi4 that exceeds the discharge start voltage. During this time, a weak initializing discharge occurs between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. Thereby, the negative wall voltage on scan electrodes SC1 to SCn and the positive wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage on data electrodes D1 to Dm is set to a value suitable for the write operation. The all-cell initialization operation for adjusting and performing the initializing discharge for all the discharge cells is completed.

  In the subsequent address period, first, voltage Vc is applied to scan electrodes SC1 to SCn. In the period T3, priming due to discharge generated between scan electrodes SC1 to SCn and sustain electrodes and between scan electrodes SC1 to SCn and data electrodes D1 to Dm converges. Thereafter, a reference voltage of 0 V is applied to the data electrodes D1 to Dm, and a voltage Ve4 higher than the first voltage of 0 V is applied to the sustain electrodes SU1 to SUn.

  Next, a scan pulse having a voltage Va is applied to the scan electrode SC1 in the first row, and an address pulse voltage Vd is applied to the data electrode Dk (k is any one of 1 to m) of the discharge cell to be lit. To do. At this time, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is the difference between the externally applied voltage (address pulse voltage Vd−scan pulse voltage Va) and the wall voltage on the data electrode Dk and the wall on the scan electrode SC1. The difference from the voltage is added and exceeds the discharge start voltage. As a result, a discharge is started between data electrode Dk and scan electrode SC1, and later progresses to a discharge between sustain electrode SU1 and scan electrode SC1, and an address discharge occurs. As a result, a positive wall voltage is accumulated on scan electrode SC1, and a negative wall voltage is accumulated on sustain electrode SU1 and data electrode Dk.

  On the other hand, the voltage at the intersection between the data electrode to which the write pulse voltage Vd has not been applied and the scan electrode SC1 does not exceed the discharge start voltage, so no write discharge occurs.

  Next, after completion of the address operation in the first row, a scan pulse having a voltage Va is applied to the scan electrode SC2 in the second row, and an address pulse voltage Vd is applied to the data electrode Dk of the discharge cell to be lit. . At this time, in the discharge cells in the second row to which the scan pulse voltage Va and the address pulse voltage Vd are simultaneously applied, an address discharge is generated and an address operation is performed.

  The address operation is repeated until the discharge cell in the n-th row, and an address discharge is selectively generated for the discharge cells to emit light, thereby forming wall charges on each electrode.

  In the sustain period, first, positive sustain pulse voltage Vs is applied to scan electrodes SC1 to SCn, and first voltage 0V is applied to sustain electrodes SU1 to SUn. At this time, in the discharge cell in which the address discharge has occurred, the voltage difference between the scan electrode SCi (i is any one of 1 to n) and the sustain electrode SUi (i is any one of 1 to n) is the sustain pulse voltage Vs. The difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi is added and exceeds the discharge start voltage. Thereby, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi. As a result, a negative wall voltage is accumulated on scan electrode SCi, and a positive wall voltage is accumulated on sustain electrode SUi and data electrode Dk.

  On the other hand, in the discharge cells in which no address discharge has occurred in the address period, no sustain discharge occurs, and the wall voltage on each electrode at the end of the initialization period is maintained.

  Next, 0 V is applied to scan electrodes SC1 to SCn, and positive sustain pulse voltage Vs is applied to sustain electrodes SU1 to SUn. At this time, in the discharge cell in which the sustain discharge has occurred, the voltage difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi. As a result, a negative wall voltage is accumulated on sustain electrode SUi, and a positive wall voltage is accumulated on scan electrode SCi and data electrode Dk.

  Thereafter, similarly, sustain pulses of the number obtained by multiplying the luminance weight by the luminance magnification are alternately applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn. By applying a potential difference to the discharge cell, the sustain discharge is continuously performed in the discharge cells that have caused the address discharge in the address period.

  At the end of the sustain period, a pulse or gradient voltage difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, leaving a positive wall voltage on data electrode Dk, and scanning. The wall voltage on electrode SCi and sustain electrode SUi is erased. Thus, the maintenance operation in the maintenance period is finished.

<Subfield for selective initialization operation>
The selective initializing operation is an operation for selectively performing initializing discharge on the discharge cells that have undergone the sustain operation in the sustain period of the immediately preceding subfield.

  In the initialization period in which selective initialization is performed, the same driving as in the period T2 in the initialization period in which the all-cell initialization operation is performed is performed.

  That is, a voltage Vt lower than the reference voltage 0V is applied to the data electrodes D1 to Dm. For this reason, as in the subfield in which the all-cell initializing operation is performed, the positive wall voltage on the data electrodes D1 to Dm becomes higher by the absolute value of the voltage Vt than when the reference voltage 0V is applied. Further, the second voltage Ve2 higher than the first voltage 0V is applied to the sustain electrodes SU1 to SUn. Scanning electrodes SC1 to SCn are applied with a downward ramp waveform voltage that gradually decreases from voltage Vi3 that is equal to or lower than the discharge start voltage to voltage Vi4 that exceeds the discharge start voltage. During this time, a weak initializing discharge occurs in the discharge cell that has generated a sustain discharge in the sustain period of the previous subfield, and the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi are weakened. For data electrode Dk, a sufficient positive wall voltage is accumulated on data electrode Dk by the last sustain discharge, so that the excess is discharged and adjusted to a wall voltage suitable for the address operation.

  On the other hand, the discharge cells that did not cause sustain discharge in the previous subfield are not discharged, and the wall charges on the electrodes at the end of the initialization period of the previous subfield are maintained as they are.

  The operation in the writing period is the same as the operation in the writing period of the subfield in which the all-cell initializing operation is performed, and the operation in the sustaining period is also the sustaining period of the subfield in which the all-cell initializing operation is performed except for the number of sustaining pulses Since the operation is the same as that in FIG.

  In the next subfield, the operation is the same as that of the subfield performing the above-described selective initialization operation, and thus the description thereof is omitted.

  Thus, in the first embodiment, the positive wall voltage on the data electrodes D1 to Dm is obtained by applying the voltage Vt lower than the reference voltage 0V to the data electrodes D1 to Dm in the period T2 of the initialization period. However, it becomes higher by the absolute value of the voltage Vt than when the reference voltage 0 V is applied. Therefore, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is increased, and a stable address discharge can be generated at high speed.

  In the first embodiment, voltage Vi1 applied to scan electrodes SC1 to SCn is 180V, voltage Vi2 is 420V, voltage Vi3 is 180V, voltage Vi4 is −100V, and scan pulse voltage Va is −100V. The second voltage Ve2 applied to the sustain electrodes SU1 to SUn was 150V, and the fourth voltage Ve4 was 150V. Sustain pulse voltage Vs applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn was set to 180V. The voltage Vt applied to the data electrodes D1 to Dm was −10V, and the address pulse voltage Vd was 70V. The slopes of the rising ramp waveform voltage and the falling ramp waveform voltage applied to scan electrodes SC1 to SCn are both 10 V / μ or less. The voltage value is not limited to the above-described value, and is desirably set optimally based on the discharge characteristics of the PDP and the specifications of the PDP display device. For example, in FIG. 3, the fourth voltage Ve4 is set to the same voltage value as the second voltage Ve2, but is equal to or lower than the voltage higher than the second voltage Ve2 by the absolute value of the voltage Vt and lower by the absolute value of the voltage Vt. It may be a voltage within a voltage range. The scan pulse voltage Va is set to the same voltage value as the voltage Vi4, but may be a voltage different from the voltage Vi4, for example, a voltage lower than the voltage Vi4.

  In the first embodiment, the number of subfields and the luminance weight value of each subfield are not limited to the above. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient. Moreover, the structure of PDP10 is not restricted above, For example, you may provide the stripe-shaped partition 24. FIG.

(Embodiment 2)
In the second embodiment of the present invention, the voltage is applied to sustain electrodes SU1 to SUn in the initial period T2 of the subfield in which the all-cell initializing operation is performed and in the initializing period of the subfield in which the selective initializing operation is performed. The waveform of the drive voltage is different from that of the first embodiment. Note that the structure and electrode arrangement of the PDP used in Embodiment 2 of the present invention are the same as the structure and electrode arrangement of the PDP 10 shown in FIGS.

  FIG. 4 is a waveform diagram of the drive voltage applied to each electrode of the PDP 10 in the second embodiment of the present invention. Hereinafter, the subfield for performing the all-cell initialization operation and the subfield for performing the selective initialization operation in the second embodiment will be described in detail with reference to FIG. In FIG. 4, the subfield in which the all-cell initializing operation is performed is the first SF, and the subfield in which the selective initializing operation is performed is the second SF. However, the present invention is not limited to this.

<Subfield for initializing all cells>
The period T11 of the initialization period is the same as the period T1 in the first embodiment. That is, 0 V, which is a reference voltage, is applied to the data electrodes D1 to Dm, and 0 V is applied as the first voltage to the sustain electrodes SU1 to SUn. Scanning electrodes SC1 to SCn are applied with an upward ramp waveform voltage that gradually increases from voltage Vi1 equal to or lower than the discharge start voltage to voltage Vi2 that exceeds the discharge start voltage. During this time, a weak initializing discharge occurs between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. As a result, negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn.

  In the initialization period T12 to T14, a voltage Vt lower than the reference voltage 0V is applied to the data electrodes D1 to Dm. Therefore, also in the second embodiment, in the initialization period T12 to T14, the positive wall voltage on the data electrodes D1 to Dm is the absolute value of the voltage Vt compared to the case where the reference voltage 0V is applied. Increases by the value. Further, a downward ramp waveform voltage that gently decreases from voltage Vi3 that is equal to or lower than the discharge start voltage to voltage Vi4 that exceeds the discharge start voltage is applied to scan electrodes SC1 to SCn. The sustain electrodes SU1 to SUn are sequentially supplied with a second voltage Ve2 higher than the first voltage V0, an upward ramp waveform voltage rising from the second voltage Ve2 to the third voltage Ve3, and the third voltage Ve3. Apply. The details will be described below.

  In the initialization period T12, a positive second voltage Ve2 higher than the first voltage 0V is applied to the sustain electrodes SU1 to SUn. During this time, a weak initializing discharge is started between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn.

  In the initial period T13, an upward ramp waveform voltage that gradually rises from the second voltage Ve2 is applied to the sustain electrodes SU1 to SUn toward the third voltage Ve3 that is higher than the second voltage Ve2. During this time, the weak wall discharge between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn causes negative wall voltage on scan electrodes SC1 to SCn and positive wall voltage on sustain electrodes SU1 to SUn. Weakened.

  In the initialization period T14, the positive third voltage Ve3 is applied to the sustain electrodes SU1 to SUn. During this time, in addition to the weak setup discharge between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, a weak setup discharge also occurs between scan electrodes SC1 to SCn and data electrodes D1 to Dm. Thereby, the negative wall voltage on scan electrodes SC1 to SCn and the positive wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage on data electrodes D1 to Dm is suitable for the write operation. The all-cell initializing operation for adjusting the value to perform initializing discharge for all the discharge cells is completed.

  Since the writing period and the sustain period are the same as those in the first embodiment, description thereof is omitted.

<Subfield for selective initialization operation>
In the initialization period in which the selective initialization is performed, the same driving as in the initialization period T12 to the period T14 in which the all-cell initialization operation is performed is performed. That is, a voltage Vt lower than the reference voltage 0V is applied to the data electrodes D1 to Dm. For this reason, as in the subfield in which the all-cell initializing operation is performed, the positive wall voltage on the data electrodes D1 to Dm becomes higher by the absolute value of the voltage Vt than when the reference voltage 0V is applied. Further, a downward ramp waveform voltage that gently decreases from voltage Vi3 that is equal to or lower than the discharge start voltage to voltage Vi4 that exceeds the discharge start voltage is applied to scan electrodes SC1 to SCn. The sustain electrodes SU1 to SUn are sequentially supplied with the second voltage Ve2 higher than the first voltage 0V, the rising ramp waveform voltage rising from the second voltage Ve2 to the third voltage Ve3, and the third voltage Ve3. Apply. During this time, a weak initializing discharge occurs in the discharge cell that has generated a sustain discharge in the sustain period of the previous subfield, and the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi are weakened. For data electrode Dk, a sufficient positive wall voltage is accumulated on data electrode Dk by the last sustain discharge, so that the excess is discharged and adjusted to a wall voltage suitable for the address operation.

  On the other hand, the discharge cells that did not cause sustain discharge in the previous subfield are not discharged, and the wall charges on the electrodes at the end of the initialization period of the previous subfield are maintained as they are.

  The operation in the writing period is the same as the operation in the writing period of the subfield in which the all-cell initializing operation is performed, and the operation in the sustaining period is also the sustaining period of the subfield in which the all-cell initializing operation is performed except for the number of sustaining pulses Since the operation is the same as that in FIG.

  In the next subfield, the operation is the same as that of the subfield performing the above-described selective initialization operation, and thus the description thereof is omitted.

  As described above, in the second embodiment, the positive wall voltage on the data electrodes D1 to Dm is obtained by applying the voltage Vt lower than the reference voltage 0V to the data electrodes D1 to Dm in the period T2 of the initialization period. However, it becomes higher by the absolute value of the voltage Vt than when the reference voltage 0 V is applied. Therefore, the voltage difference at the intersection between the data electrode Dk and the scan electrode SC1 is increased, and a stable address discharge can be generated at high speed.

  In FIG. 4, the fourth voltage Ve4 is set to a voltage value lower than the third voltage Ve3. However, the fourth voltage Ve4 is lower than the third voltage Ve3 by a voltage higher than the absolute value of the voltage Vt and lower by the absolute value of the voltage Vt. It may be a voltage within a voltage range. In FIG. 4, the scanning pulse voltage Va is shown as the same voltage value as the voltage Vi4, but may be a voltage different from the voltage Vi4, for example, a voltage lower than the voltage Vi4.

  Next, the driving method for the PDP display device of the present invention will be described using the driving circuit for generating the driving voltage waveform in the second embodiment as an example.

  FIG. 5 is a circuit block diagram of PDP display device 100 according to Embodiment 2 of the present invention. As shown in FIG. 5, the PDP display device 100 according to the second embodiment includes a PDP 10, an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, In addition, a power supply circuit (not shown) for supplying necessary power to each circuit block is provided.

  The image signal processing circuit 31 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 32 converts the image data for each subfield sent from the image signal processing circuit 31 into signals corresponding to the data electrodes D1 to Dm, and drives the data electrodes D1 to Dm. The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit block based on the horizontal synchronization signal and the vertical synchronization signal, and transmits them to each circuit block. Scan electrode drive circuit 33 drives each of scan electrodes SC1 to SCn based on the timing signal sent from timing generation circuit 35. Sustain electrode drive circuit 34 drives sustain electrodes SU1 to SUn based on the timing signal sent from timing generation circuit 35.

  FIG. 6 is a circuit diagram of the data electrode driving circuit 32 according to the second embodiment of the present invention, FIG. 7 is a circuit diagram of the scan electrode driving circuit 33 according to the second embodiment of the present invention, and FIG. 8 is an embodiment of the present invention. FIG. 10 is a circuit diagram of a sustain electrode drive circuit 34 in the second embodiment.

  As shown in FIG. 6, the data electrode drive circuit 32 in the second embodiment applies the floating power supply E41 of the write pulse voltage Vd and the voltage on the high voltage side of the floating power supply E41 to the corresponding data electrodes D1 to Dm, respectively. Switching elements Q45H1 to Q45Hm for switching, the switching element Q45L1 to Q45Lm for applying the low voltage side voltage of the floating power supply E41 to the corresponding data electrodes D1 to Dm, and the low voltage side voltage of the floating power supply E41 are fixed to 0V Switching elements Q41 and Q42 for switching, and a switching element Q43 for fixing the low-voltage side voltage of the floating power supply E41 to the voltage Vd.

  As shown in FIG. 7, scan electrode drive circuit 33 in the second embodiment includes sustain pulse generation circuit 50, initialization waveform generation circuit 60, and scan pulse generation circuit 70. Sustain pulse generating circuit 50 includes a switching element Q55 for applying sustain pulse voltage Vs to scan electrodes SC1 to SCn, a switching element Q56 for applying voltage 0V to scan electrodes SC1 to SCn, and scan electrodes SC1 to SCn. And a power recovery unit 59 for recovering power when applying the sustain pulse. Initialization waveform generation circuit 60 includes Miller integration circuit 61 for applying an up-slope waveform voltage to scan electrodes SC1 to SCn, and Miller integration circuit 62 for applying a down-slope waveform voltage to scan electrodes SC1 to SCn. Have. Switching element Q63 and switching element Q64 are provided in order to prevent a current from flowing back through a parasitic diode or the like of another switching element. Scan pulse generation circuit 70 includes floating power supply E71 of voltage Vscn applied to the write IC, switching elements Q72H1 to Q72Hn for applying the high-voltage side voltage of floating power supply E71 to corresponding scan electrodes SC1 to SCn, and floating Switching elements Q72L1 to Q72Ln for applying the low-voltage side voltage of power supply E71 to corresponding scan electrodes SC1 to SCn, and switching element Q73 for fixing the low-voltage side voltage of floating power supply E71 to scan pulse voltage Va. .

  As shown in FIG. 8, sustain electrode drive circuit 34 in the second exemplary embodiment includes sustain pulse generation circuit 80 and initialization / write voltage generation circuit 90. Sustain pulse generation circuit 80 includes a switching element Q85 for applying sustain pulse voltage Vs to sustain electrodes SU1 to SUn, a switching element Q86 for applying voltage 0V to sustain electrodes SU1 to SUn, and sustain electrodes SU1 to SUn. And a power recovery unit 89 for recovering power when a sustain pulse is applied. The initialization / writing voltage generation circuit 90 is configured to gradually apply the switching element Q92 and the diode D92 for applying the second voltage Ve2 to the sustain electrodes SU1 to SUn, and the sustain electrodes SU1 to SUn toward the third voltage Ve3. Miller integrating circuit 93 and diode D93 for applying the rising ramp waveform voltage, and switching element Q94 and diode D94 for applying fourth voltage Ve4 to sustain electrodes SU1 to SUn are provided.

  In addition, these switching elements can be comprised using generally known elements, such as MOSFET and IGBT.

  Next, operations of the data electrode drive circuit 32, the scan electrode drive circuit 33, and the sustain electrode drive circuit 34 will be described.

  FIG. 9 is a detailed diagram showing the waveform of the drive voltage applied to each electrode of PDP 10 in the second embodiment of the present invention. In the second embodiment, voltage Vi1 and voltage Vi3 are both assumed to be equal to sustain pulse voltage Vs.

<Period T11>
When the switching element Q55 of the scan electrode driving circuit 33 is turned on at time t1, the scan electrodes SC1 to SCn receive Vi1 (voltage Vs below the discharge start voltage) via the switching elements Q55, Q63, Q64, Q72L1 to Q72Ln. ) Is applied. After that, when switching element Q63 is turned off and Miller integrating circuit 61 is operated, scan electrodes SC1 to SCn gradually increase from Vi1 (voltage Vs) equal to or lower than the discharge start voltage toward voltage Vi2 exceeding the discharge start voltage. Ascending ramp waveform voltage rising is applied.

  During this time, when the switching element Q41 of the data electrode driving circuit 32 is turned on and the switching elements Q45L1 to Q45Lm are turned on, 0 V, which is a reference voltage, is applied to the data electrodes D1 to Dm.

  When switching element Q86 of sustain electrode drive circuit 34 is turned on, 0 V is applied as the first voltage to sustain electrodes SU1 to SUn.

  A weak initializing discharge occurs between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. Thereby, negative wall voltage is accumulated on scan electrodes SC1 to SCn, and positive wall voltage is accumulated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn.

<Period T12>
At time t2, when Miller integrating circuit 61 of scan electrode drive circuit 33 is stopped and switching elements Q55 and Q63 are turned on, Vi3 (voltage Vs) equal to or lower than the discharge start voltage is applied to scan electrodes SC1 to SCn. . Thereafter, when switching element Q64 is turned off, Miller integrating circuit 62 operates, and scan electrodes SC1 to SCn are gradually applied to scan electrode SC1 to SCn from Vi3 (voltage Vs) equal to or lower than the discharge start voltage toward voltage Vi4 exceeding the power start voltage. A falling ramp waveform voltage is applied. This downward ramp waveform voltage is applied to scan electrodes SC1 to SCn over periods T12 to T14.

  When the switching element Q41 of the data electrode driving circuit 32 is turned off and the switching element Q43 is turned on, a voltage Vt lower than the reference voltage 0V is applied to the data electrodes D1 to Dm. This voltage Vt is applied to the data electrodes D1 to Dm over a period T12 to a period T15.

  When switching element Q86 of sustain electrode drive circuit 34 is turned off and switching element Q92 is turned on, positive second voltage Ve2 higher than first voltage 0V is applied to sustain electrodes SU1 to SUn.

  During this time, a weak initializing discharge is started between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn.

<Period T13>
When the Miller integrating circuit 93 of the sustain electrode drive circuit 34 is operated at time t3, the sustain electrodes SU1 to SUn gradually increase from the second voltage Ve2 to the third voltage Ve3 higher than the second voltage Ve2. Ascending ramp waveform voltage rising is applied.

  During this time, the weak wall discharge between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn causes negative wall voltage on scan electrodes SC1 to SCn and positive wall voltage on sustain electrodes SU1 to SUn. Be weakened.

<Period T14>
At time t4, when the voltage applied to the sustain electrodes SU1 to SUn rises to the third voltage Ve3, the voltage is then held at the third voltage Ve3.

  During this time, in addition to the weak setup discharge between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, a weak setup discharge also occurs between scan electrodes SC1 to SCn and data electrodes D1 to Dm. Thereby, the negative wall voltage on scan electrodes SC1 to SCn and the positive wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage on data electrodes D1 to Dm is suitable for the write operation. Adjusted to the value.

  In the second embodiment, no discharge is generated between scan electrodes SC1 to SCn and data electrodes D1 to Dm between time t2 and time t4, but discharge is generated after time t4. The time t3 is set as a time when a waveform having a slope of 10 V / μ or less can be started retroactively from the time t4.

<Period T15>
At time t5 when the voltage applied to scan electrodes SC1 to SCn drops to voltage Vi4 exceeding the discharge start voltage, switching element Q73 of scan electrode drive circuit 33 is turned on, and scan pulse generating circuit 70 When switching elements Q72L1 to Q72Ln are turned off and switching elements Q72H1 to Q72Hn are turned on, voltage (Va + Vscn) is applied to scan electrodes SC1 to SCn. Here, the voltage (Va + Vscn) is the voltage Vc shown in FIG.

  In the period 15, priming due to discharge generated between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn and between scan electrodes SC1 to SCn and data electrodes D1 to Dm converges. Thereafter, when the switching element Q43 of the data electrode driving circuit 32 is turned off and the switching elements Q41 and Q42 are turned on, the reference voltage 0V is applied to the data electrodes D1 to Dm. When switching element Q92 of sustain electrode drive circuit 34 is turned off, Miller integrating circuit 93 is stopped, and switching element Q94 is turned on, fourth voltage Ve4 is applied to sustain electrodes SU1 to SUn.

  Note that the period T15 is desirably set between 5 μs and 50 μs.

  In this manner, the PDP display device and the driving method thereof according to the present invention can be realized by using the driving circuits shown in FIGS.

  The driving circuit of the PDP display device of the present invention is not limited to the above as long as the driving voltage waveform shown in FIGS. 3 and 4 can be realized.

  In addition, when the PDP display device and the driving method thereof in the second embodiment are applied, it is assumed that the value of the second voltage Ve2 applied to the sustain electrodes SU1 to SUn is different from the value of the fourth voltage Ve4. However, when the value of the second voltage Ve2 is equal to the value of the fourth voltage Ve4, the switching element Q94 and the diode D94 of the initialization / write voltage generation circuit 90 may be omitted.

  When the PDP display device and the driving method thereof according to the first embodiment are applied, the Miller integration circuit 93 and the diode D93 of the initialization / write voltage generation circuit 90 may be omitted.

  In addition, the specific numerical values used in the first and second embodiments are merely examples, and should be appropriately set to optimum values according to the characteristics of the PDP, the specifications of the PDP display device, and the like. Is desirable.

  The present invention is useful as a PDP display device and a driving method thereof because a high-definition PDP display device can generate stable address discharge and perform stable image display at high speed.

1 is an exploded perspective view showing the structure of a PDP according to Embodiment 1 of the present invention. Electrode arrangement diagram of PDP according to Embodiment 1 of the present invention Waveform diagram of drive voltage applied to each electrode of PDP in Embodiment 1 of the present invention Waveform diagram of drive voltage applied to each electrode of PDP in Embodiment 2 of the present invention Circuit block diagram of a PDP display device according to Embodiment 2 of the present invention Circuit diagram of data electrode driving circuit in Embodiment 2 of the present invention Circuit diagram of scan electrode driving circuit in Embodiment 2 of the present invention Circuit diagram of sustain electrode driving circuit in Embodiment 2 of the present invention Detailed view showing the waveform of the drive voltage applied to each electrode of the PDP in Embodiment 2 of the present invention

Explanation of symbols

10 PDP
DESCRIPTION OF SYMBOLS 11 Front substrate 12 Scan electrode 13 Sustain electrode 14 Display electrode pair 15,23 Dielectric layer 16 Protective layer 21 Back substrate 22 Data electrode 24 Partition 25 Phosphor layer 31 Image signal processing circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 50, 80 Sustain pulse generation circuit 59, 89 Power recovery unit 60 Initialization waveform generation circuit 61, 62, 93 Miller integration circuit 70 Scan pulse generation circuit 90 Initialization / write voltage generation circuit 100 PDP Display device

Claims (6)

A method for driving a plasma display panel comprising a plurality of discharge cells having a display electrode pair consisting of a scan electrode and a sustain electrode and a data electrode,
One field is composed of a plurality of subfields having an initialization period for generating an initialization discharge in the discharge cells, an address period for generating an address discharge, and a sustain period for generating a sustain discharge,
In the initialization period, a first voltage is applied to the sustain electrode, a reference voltage is applied to the data electrode, and an upward ramp waveform voltage is applied to the scan electrode,
A voltage higher than the first voltage is applied to the sustain electrode, a voltage lower than the reference voltage is applied to the data electrode, and a downward ramp waveform voltage is applied to the scan electrode. Driving method. In the initialization period, a second voltage higher than the first voltage is applied to the sustain electrode, an upward ramp waveform voltage rising from the second voltage to a third voltage higher than the second voltage, the third voltage Are sequentially applied,
The method for driving a plasma display panel according to claim 1. In the address period, the voltage applied to the sustain electrode at the end of the initialization period is the same as the voltage applied to the sustain electrode, or the voltage applied to the sustain electrode at the end of the initialization period is greater than the voltage applied to the sustain electrode. Applying a voltage that is not higher than the absolute value of the difference between the reference voltage applied to the data electrode during the initialization period and a voltage lower than the reference voltage, and that is within the range not lower than the voltage that is lower than the absolute value. Features
The method for driving a plasma display panel according to claim 1 or 2. A plasma display panel having a plurality of discharge cells each having a display electrode pair and a data electrode each including a scan electrode and a sustain electrode;
A plasma display panel display device having a control unit for controlling the plasma display panel,
The control unit constitutes one field with a plurality of subfields having an initializing period for generating an initializing discharge in the discharge cells, an addressing period for generating an addressing discharge, and a sustaining period for generating a sustaining discharge,
In the initialization period, a first voltage is applied to the sustain electrode, a reference voltage is applied to the data electrode, and an upward ramp waveform voltage is applied to the scan electrode,
A plasma display panel display, wherein a voltage higher than the first voltage is applied to the sustain electrode, a voltage lower than the reference voltage is applied to the data electrode, and a downward ramp waveform voltage is applied to the scan electrode. apparatus. In the initialization period, a second voltage higher than the first voltage is applied to the sustain electrode, an upward ramp waveform voltage rising from the second voltage to a third voltage higher than the second voltage, the third voltage Are sequentially applied,
The plasma display panel display device according to claim 4. In the address period, the voltage applied to the sustain electrode at the end of the initialization period is the same as the voltage applied to the sustain electrode, or the voltage applied to the sustain electrode at the end of the initialization period is greater than the voltage applied to the sustain electrode. Applying a voltage that is not higher than the absolute value of the difference between the reference voltage applied to the data electrode during the initialization period and a voltage lower than the reference voltage, and that is within the range not lower than the voltage that is lower than the absolute value. Features
The plasma display panel display device according to claim 4 or 5.

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