WO2010137248A1

WO2010137248A1 - Plasma display device and plasma display panel driving method

Info

Publication number: WO2010137248A1
Application number: PCT/JP2010/003229
Authority: WO
Inventors: 井土眞澄; 若林俊一
Original assignee: パナソニック株式会社
Priority date: 2009-05-27
Filing date: 2010-05-13
Publication date: 2010-12-02

Abstract

Disclosed are a plasma display device and a plasma display panel drive method such that it is possible to simplify driver circuits and also allow stable discharge control. The device is provided with a plasma display panel (10), a scanning electrode driver circuit (33), a sustain electrode driver circuit (34), and a data electrode driver circuit (32). One field period comprises multiple subfields which include a write period and a sustain period; in the sustain period of each subfield, the sustain electrode driver circuit (34) provides to the sustain electrode a sustain-side sustain pulse, one cycle of which comprises: a rising period, where the potential rises from a first potential to a second potential; a high period, where the second potential is sustained; a falling period, where the potential falls from the second potential to the first potential; and a low period, where the first potential is sustained. In periods other than the sustain period, the sustain electrode driver circuit only provides to the sustain electrode a potential equal to either the first potential or the second potential.

Description

Plasma display apparatus and plasma display panel driving method

The present invention relates to a plasma display device which is an image display device using an AC plasma display panel and a driving method of the plasma display panel.

A typical AC surface discharge panel as a plasma display panel (hereinafter abbreviated as “PDP”) includes a front substrate on which a plurality of display electrode pairs each formed of a pair of scan electrodes and sustain electrodes are formed, and data electrodes Are arranged opposite to the rear substrate on which a plurality of are formed. A discharge cell is formed in a portion where the display electrode pair and the data electrode face each other. Color display is performed by generating gas discharge in each discharge cell of such a panel and exciting and emitting phosphors of each color.

As a method for driving the PDP, a subfield method is generally used in which one field period is divided into a plurality of subfields, and a discharge cell is caused to emit light or not emit light in each subfield to perform gradation display. Each subfield has, for example, an initialization period, a writing period, and a sustain period. In the initializing period, initializing discharge is generated, and wall charges necessary for the subsequent writing operation are formed on each electrode. In the write period, a scan pulse is applied to the scan electrode and a write pulse is selectively applied to the data electrode to generate a write discharge and form wall charges. In the sustain period, a sustain pulse is alternately applied to the display electrode pair, a sustain discharge is generated in the discharge cell that has caused the write discharge, and the phosphor layer of the corresponding discharge cell is caused to emit light, thereby displaying an image.

In such a PDP driving method, various driving voltage waveforms have been studied in order to perform stable discharge control. For example, Patent Document 1 describes a driving method in which sustain pulses having different voltage values are applied to scan electrodes and sustain electrodes to generate sustain discharge stably.

In addition, it is necessary to apply complex drive voltage waveforms such as an initialization pulse, a scan pulse, and a sustain pulse to the scan electrodes, and the scan electrode drive circuit that generates these drive voltage waveforms tends to have a complicated circuit configuration. is there. Therefore, a simplified scan electrode driving circuit has been proposed. For example, Patent Document 2 discloses a scan electrode driving circuit that simplifies the circuit by applying a positive scan pulse to each scan electrode and applying a negative write pulse to a data electrode.

JP 2006-259061 A JP-A-11-316570

However, in order to perform stable discharge control, the drive voltage waveform tends to be complicated. To realize this, not only the scan electrode drive circuit is complicated, but the number of necessary potentials is increased and the power supply is increased. The circuit also tended to be complicated. On the other hand, when the scan electrode drive circuit is simplified, the drive voltage waveform that can be realized is limited, and stable discharge control tends to be difficult. Thus, it has been difficult to achieve both stable discharge control and simplification of the drive circuit.

The present invention has been made in view of these problems, and provides a plasma display device and a plasma display panel driving method capable of simplifying a driving circuit and further realizing stable discharge control. With the goal.

In order to achieve the above object, the plasma display apparatus of the present invention is arranged such that a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes and a plurality of data electrodes intersect with a gap, A plasma display panel having a plurality of discharge cells each having the display electrode pair and the data electrode forming the gap and having the gap as a discharge space; and a drive circuit for driving the plasma display panel. The drive circuit includes a scan electrode drive circuit that drives the scan electrode, a sustain electrode drive circuit that drives the sustain electrode, and a data electrode drive circuit that drives the data electrode, and the sustain electrode drive circuit includes: An address period during which an address operation is performed to generate the address discharge in the discharge cells to be lit, and an address discharge is generated. In the sustain period of each of the subfields of one field period configured using a plurality of subfields having a sustain period for causing the discharge cells to emit light, a period of one period from the first potential to the first A rising period rising to a second potential higher than the first potential, a high period holding the second potential, a falling period falling from the second potential to the first potential, and the first A sustain side sustain pulse composed of a low period for holding a potential is applied to the sustain electrode, and only a potential equal to one of the first potential and the second potential is applied in a period other than the sustain period. The scan electrode driving circuit is configured to be applied to the sustain electrode, and the scan electrode driving circuit has a cycle different from that of the sustain-side sustain pulse in the sustain period of each subfield. The sustain electrode is configured to apply a sustain pulse to the scan electrode, and the sustain electrode drive circuit and the scan electrode drive circuit have an amplitude that is a difference between the first potential and the second potential of the sustain side sustain pulse. Is smaller than the amplitude of the sustain pulse on the scanning side. With this configuration, the sustain electrode driving circuit can be simplified, and further, stable discharge control can be realized.

The scan-side sustain pulse includes a rising period in which a period of one period rises from a third potential to a fourth potential higher than the third potential, a high period in which the fourth potential is held, The sustaining electrode driving circuit and the scanning electrode driving circuit are configured by a falling period falling from the fourth potential to the third potential and a low period holding the third potential. Before the falling period of the scan-side sustain pulse that follows the high period of the scan-side sustain pulse, including the first period in which the high period of the sustain pulse and the low period of the sustain-side sustain pulse overlap, The rising period of the sustain side sustain pulse that follows the low period of the sustain side sustain pulse including the first period ends, and the low period of the scan side sustain pulse overlaps the high period of the sustain side sustain pulse. Includes 2 periods The sustain pulse of the scan side sustain pulse following the low period of the scan side sustain pulse including the second period before the fall period of the sustain side sustain pulse following the high period of the sustain side sustain pulse ends. It is preferable to end the rising period in order to realize stable discharge control.

The drive circuit divides the plurality of display electrode pairs into a plurality of display electrode pair groups, and uses one subfield having a plurality of subfields having the write period and the sustain period for each display electrode pair group. When the period is divided, the number of the display electrode pair groups is N, and the time required to perform the write operation once for all the discharge cells is Tw, each of the display electrode pair groups Even in the case of an ultra-high definition PDP, the plasma display panel is driven so that the duration of the subfield sustain period does not exceed Tw × (N−1) / N. Therefore, it is possible to secure a sufficient number of subfields for ensuring image quality and to drive with sufficient luminance. In addition, the sustain electrode driving circuit can be simplified, which is preferable for realizing more stable discharge control.

In the plasma display panel driving method of the present invention, a plurality of display electrode pairs each consisting of a pair of scan electrodes and sustain electrodes and a plurality of data electrodes are arranged so as to intersect with a gap. A plurality of discharge cells having the gap as a discharge space, the scan electrode being driven by a scan electrode drive circuit, and the sustain electrode being driven by a sustain electrode drive circuit A driving method of a plasma display panel in which an electrode is driven and the data electrode is driven by a data electrode driving circuit, wherein a writing period in which a writing operation for generating the writing discharge is performed in the discharge cell to emit light, And a plurality of subfields having a sustain period for causing the discharge cells that have generated an address discharge to emit light In the sustain period of each of the subfields in the field period, a period of one period holds the second potential and a rising period in which the first potential rises to a second potential higher than the first potential The sustain electrode drive circuit generates a sustain-side sustain pulse composed of a high period during which the sustain potential falls from the second potential to the first potential, and a low period during which the first potential is maintained. The sustain electrode is applied to the sustain electrode, and the sustain electrode driving circuit applies only the potential equal to one of the first potential and the second potential to the sustain electrode in a period other than the sustain period. In the sustain period of the field, the scan electrode drive circuit supplies the scan electrode with a scan side sustain pulse having the same period and a different phase from the sustain side sustain pulse, and the sustain side sustain pulse Amplitude which is a difference between the second potential and the first potential, it is desirable to the smaller than the amplitude of the scanning sustain pulse. By this driving method, the sustain electrode driving circuit can be simplified, and further stable discharge control can be realized.

The scan-side sustain pulse includes a rising period in which a period of one period rises from a third potential to a fourth potential higher than the third potential, a high period in which the fourth potential is held, A falling period falling from the fourth potential to the third potential; and a low period holding the third potential. The high period of the scan side sustain pulse and the low period of the sustain side sustain pulse Before the falling period of the scan-side sustain pulse that follows the high period of the scan-side sustain pulse including the first period that overlaps the period, the sustain-side sustain pulse that includes the first period is low. The sustain-side sustain pulse high period includes a second period in which a rising period of the sustain-side sustain pulse following the period ends and a low period of the scan-side sustain pulse overlaps a high period of the sustain-side sustain pulse Said maintenance following Before the end of the sustain pulse falling period, a stable discharge may be performed by ending the rise period of the scan-side sustain pulse following the low period of the scan-side sustain pulse including the second period. This is preferable for realizing the control.

Further, the plurality of display electrode pairs are divided into a plurality of display electrode pair groups, and for each display electrode pair group, one field period is divided using a plurality of subfields having the write period and the sustain period, When the number of the display electrode pair groups is N and the time required to perform one write operation for all the discharge cells is Tw, the sustain period of each subfield of each display electrode pair group By driving the plasma display panel so that the time does not exceed Tw × (N−1) / N, a sufficient number of subfields to ensure image quality can be obtained even for ultra-high definition PDPs. Can be ensured, and can be driven with sufficient luminance. In addition, the sustain electrode driving circuit can be simplified, which is preferable for realizing more stable discharge control.

According to the present invention, it is possible to provide a plasma display device and a method for driving a plasma display panel that can simplify a drive circuit and can realize stable discharge control.

The above object, other objects, features, and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments with reference to the accompanying drawings.

FIG. 1 is an exploded perspective view showing a structure of a PDP used in Embodiment 1 of the present invention. FIG. 2 is an electrode array diagram of the PDP used in Embodiment 1 of the present invention. FIG. 3 is a circuit block diagram of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 4 is a circuit diagram showing details of the sustain electrode driving circuit of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 5 is a drive voltage waveform diagram applied to each electrode of the PDP in Embodiment 1 of the present invention. FIG. 6 is a drive voltage waveform diagram showing details of the scan-side sustain pulse and sustain-side sustain pulse of the plasma display device in accordance with the first exemplary embodiment of the present invention. FIG. 7 is an electrode array diagram of the PDP used in the second embodiment of the present invention. FIG. 8 is a diagram for explaining a method for setting the subfield configuration of the plasma display device in accordance with the second exemplary embodiment of the present invention. FIG. 9 is a drive voltage waveform diagram applied to each electrode of the PDP in the second embodiment of the present invention. FIG. 10 is a circuit diagram showing details of the sustain electrode drive circuit of the plasma display device in accordance with the second exemplary embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is an exploded perspective view showing a structure of a PDP 10 used in the embodiment of the present invention. On the glass front substrate 11, a plurality of display electrode pairs 14 made up of scanning electrodes 12 and sustaining electrodes 13 are formed. A dielectric layer 15 is formed so as to cover the scan electrode 12 and the sustain electrode 13, and a protective layer 16 is formed on the dielectric layer 15. A plurality of data electrodes 22 are formed on the rear substrate 21, a dielectric layer 23 is formed so as to cover the data electrodes 22, and a grid-like partition wall 24 is formed thereon. A phosphor layer 25 that emits red, green, and blue light is provided on the side surface of the partition wall 24 and on the dielectric layer 23.

The front substrate 11 and the rear substrate 21 are arranged to face each other so that the display electrode pair 14 and the data electrode 22 cross each other with a minute discharge space interposed therebetween, and the outer peripheral portion thereof is a sealing material (not shown) such as a glass frit. Z). In the discharge space, for example, a mixed gas of neon and xenon is enclosed as a discharge gas. The discharge space is partitioned into a plurality of sections by barrier ribs 24, and discharge cells are formed at portions where display electrode pairs 14 and data electrodes 22 intersect. These discharge cells discharge and emit light to display an image.

Note that the structure of the PDP 10 is not limited to that described above, and for example, a structure having a stripe-shaped partition wall instead of the cross-beam-shaped partition wall 24 may be used.

FIG. 2 is an electrode array diagram of the PDP 10 used in the embodiment of the present invention. In the PDP 10, n scan electrodes SC1 to SCn (scan electrode 12 in FIG. 1) and n sustain electrodes SU1 to SUn (sustain electrode 13 in FIG. 1) long in the row direction are arranged, and m long in the column direction. Data electrodes D1 to Dm (data electrodes 22 in FIG. 1) are arranged. A region where the pair of scan electrodes SCi (i = 1 to n) and sustain electrode SUi and one data electrode Dj (j = 1 to m) intersect with each other across the discharge space and its vicinity are displayed as an image. It becomes one discharge cell that contributes to. Therefore, each discharge cell includes a pair of display electrodes (scan electrode SCNi and sustain electrode SUSi) and one data electrode, and includes a discharge space between them. In this PDP 10, m × n discharge cells are formed.

FIG. 3 is a circuit block diagram of plasma display device 30 in accordance with the exemplary embodiment of the present invention. The plasma display device 30 includes a PDP 10, an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit 36.

The image signal processing circuit 31 converts the input image signal into image data indicating light emission / non-light emission for each subfield. The data electrode drive circuit 32 converts the image data for each subfield into signals corresponding to the data electrodes D1 to Dm, and applies the signals to the data electrodes D1 to Dm based on the timing signal from the timing generation circuit 35. Thus, the data electrodes D1 to Dm are driven. The timing generation circuit 35 generates various timing signals for controlling the operation of each circuit based on the horizontal synchronization signal and the vertical synchronization signal, and supplies them to the

respective circuits

32, 33 and 34. Scan electrode drive circuit 33 drives each of scan electrodes SC1 to SCn based on the applied timing signal, and sustain electrode drive circuit 34 drives sustain electrodes SU1 to SUn based on the applied timing signal.

The power supply circuit 36 includes various power supplies that supply power to each circuit block including the sustain electrode drive circuit 34.

FIG. 4 is a circuit diagram showing details of sustain electrode drive circuit 34 of plasma display device 30 in accordance with the exemplary embodiment of the present invention.

The sustain electrode drive circuit 34 includes a pulse generator 40. The pulse generator 40 includes a transistor Q42 as a switching element for applying a potential Vs2 to the sustain electrodes SU1 to SUn, a transistor Q43 as a switching element for applying a potential of 0 (V) to the sustain electrodes SU1 to SUn, And a power recovery unit 41 for recovering electric power when a sustain pulse (sustain-side sustain pulse) is applied to sustain electrodes SU1 to SUn.

The power recovery unit 41 includes a capacitor C1 for power recovery, transistors Q44 and Q45, diodes D1 and D2 for backflow prevention, and a resonance inductor L1. The sustain pulse rises and falls by causing LC resonance between the “interelectrode capacitance Cp”) and the inductor L1. When the sustain pulse rises, the electric charge stored in the power recovery capacitor C1 is moved to the interelectrode capacitance Cp via the transistor Q44, the diode D1, and the inductor L1. When the sustain pulse falls, the electric charge stored in the interelectrode capacitance Cp is returned to the power recovery capacitor C1 via the inductor L1, the diode D2, and the transistor Q45.

The voltage clamp unit constituted by the transistors Q42 and Q43 connects the sustain electrodes SU1 to SUn to the power source and clamps them to the potential Vs2 by turning on the transistor Q42 while the transistor Q43 is non-conductive. Further, when the transistor Q42 is turned off and the transistor Q43 is turned on, the sustain electrodes SU1 to SUn are grounded and clamped to 0 (V).

Thus, sustain electrode drive circuit 34 applies sustain pulses (sustain-side sustain pulses) to sustain electrodes SU1 to SUn during the sustain period described later by controlling transistors Q42 to Q45. Further, the latter half of the initialization period in which the all-cell initialization operation described later is performed, the initialization period in which the selective initialization operation is performed, and the writing period are maintained by turning on the transistor Q42 while the transistor Q43 is in a non-conductive state. In the first half of the initializing period in which the electrodes SU1 to SUn are held at the potential Vs2 and the all-cell initializing operation is performed, the transistor Q42 is turned off and the sustaining electrodes SU1 to SUn are set to 0 (V). Hold on.

The transistors Q42 to Q45 described above can be configured using generally known elements such as MOSFETs and IGBTs.

Next, drive voltage waveforms for driving the PDP 10 will be described. The plasma display device 30 performs gradation display by dividing the one-field period into a plurality of subfields and controlling light emission / non-light emission of each discharge cell for each subfield. Each subfield has an initialization period, a writing period, and a sustain period. In the initializing period, initializing discharge is generated in the discharge cell in order to make the inside of the discharge cell in a charged state capable of writing discharge, and wall charges necessary for the subsequent writing discharge are formed on each electrode. In the writing period, scanning pulses are sequentially applied to the scanning electrodes and writing pulses are applied to the data electrodes based on the image signal to selectively generate a writing discharge in the discharge cells to be emitted and form wall charges necessary for the subsequent sustain discharge. To do. In the sustain period, a scan-side sustain pulse is alternately applied to the scan electrode, and a sustain-side sustain pulse is alternately applied to the sustain electrode, and a sustain discharge is generated in the discharge cell that has generated the write discharge to emit light.

In the present embodiment, one field is divided into, for example, first to ten ten subfields (first SF, second SF,..., Tenth SF), and each subfield is, for example, (1 2, 3, 6, 11, 18, 30, 44, 60, 80). In addition, in the initializing period of the first SF, an all-cell initializing operation for generating an initializing discharge in all the discharge cells is performed, and in the initializing period of the second SF to the tenth SF, a discharge cell in which a sustain discharge is performed in the immediately preceding subfield. A selective initializing operation for generating an initializing discharge is performed. However, in the present invention, the number of subfields and the luminance weight of each subfield are not limited to the above values. Moreover, the structure which switches a subfield structure based on an image signal etc. may be sufficient.

FIG. 5 is a drive voltage waveform diagram applied to each electrode of the PDP 10 in the embodiment of the present invention, and shows drive voltage waveforms in the first SF (first subfield) and the second SF (second subfield). . Scan electrodes SC1 to SCn are supplied with the drive voltage shown in FIG. 5 from scan electrode drive circuit 33, and sustain electrodes SU1 to SUn are supplied with the drive voltage shown in FIG. 5 from sustain electrode drive circuit 34, and data electrodes D1 to A drive voltage shown in FIG. 5 is applied to Dm from the data electrode drive circuit 32.

In the first half of the initializing period of the first SF, a potential of 0 (V) is applied to the data electrodes D1 to Dm, and a potential of 0 (V) is applied to the sustain electrodes SU1 to SUn. Scan electrodes SC1 to SCn are given an upward ramp waveform potential that gradually rises from sustain potential SU1 to SUn from potential Vi1 that is equal to or lower than the discharge start voltage to potential Vi2 that exceeds the discharge start voltage.

While the ramp waveform potential rises, a weak initializing discharge occurs between scan electrodes SC1 to SCn, sustain electrodes SU1 to SUn, and data electrodes D1 to Dm. Negative wall voltages are generated on scan electrodes SC1 to SCn, and positive wall voltages are generated on data electrodes D1 to Dm and sustain electrodes SU1 to SUn. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like.

In the latter half of the subsequent initialization period, the potential Vs2 is applied to the sustain electrodes SU1 to SUn. Scan electrodes SC1 to SCn are applied with sustain waveform SU1 to SUn having a downward slope waveform potential that gently falls from potential Vi3 that is equal to or lower than the discharge start voltage to potential Vi4 that exceeds the discharge start voltage. Note that in this embodiment, the potential Vi4 is a negative potential.

During this time, a weak initializing discharge occurs between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, and between scan electrodes SC1 to SCn and data electrodes D1 to Dm. Then, the negative wall voltage on scan electrodes SC1 to SCn and the positive wall voltage on sustain electrodes SU1 to SUn are weakened, and the positive wall voltage on data electrodes D1 to Dm is adjusted to a value suitable for the write operation. Is done. That is, the inside of each discharge cell is in a charged state capable of writing discharge.

In the subsequent writing period, the potential Vs2 is continuously applied to the sustain electrodes SU1 to SUn, and the potential Vc is applied to the scan electrodes SC1 to SCn.

Next, a scan pulse having a negative potential Va is applied to the scan electrode SC1 in the first row, and the potential Vd is written to the data electrode Dk (k = 1 to m) corresponding to the discharge cell to emit light in the first row. Give a pulse.

Then, the potential difference at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the magnitude of the wall voltage on the data electrode Dk and the magnitude of the wall voltage on the scan electrode SC1 to the externally applied voltage (Vd−Va). Exceeding the discharge start voltage. Then, a discharge starts between data electrode Dk and scan electrode SC1, progresses to a discharge between sustain electrode SU1 and scan electrode SC1, and an address discharge is generated. As a result, a positive wall voltage is generated on scan electrode SC1, a negative wall voltage is generated on sustain electrode SU1, and a negative wall voltage is also generated on data electrode Dk.

In this way, an address operation is performed in which an address discharge is generated in the discharge cells to be lit in the first row to generate a wall voltage on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the write pulse potential Vd is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so that no write discharge occurs.

Next, a scan pulse is given to the scan electrode SC2 in the second row, and a write pulse is given to the data electrode Dk corresponding to the discharge cell to be lit in the second row.

Then, an address discharge occurs in the discharge cells in the second row to which the scan pulse and the address pulse are simultaneously applied, and an address operation is performed.

Similarly, a scan pulse at the potential Va is sequentially applied to the scan electrodes SC3 to SCn, and a write pulse is applied to the data electrode Dk corresponding to the discharge cell to be lit to selectively emit light to the discharge cell to be lit. Write discharge is generated to form wall charges. In this way, the write operation is repeated until the discharge cell in the nth row is reached.

In the subsequent sustain period, a scan-side sustain pulse whose peak value is potential Vs1 is alternately applied to scan electrodes SC1 to SCn, and a sustain-side sustain pulse whose peak value is potential Vs2 is alternately applied to sustain electrodes SU1 to SUn. The sustain discharge is continuously generated in the discharge cell in which the address discharge is generated in step.

FIG. 6 is a drive voltage waveform diagram showing details of the scan-side sustain pulse and the sustain-side sustain pulse of the plasma display device 30 according to the embodiment of the present invention.

A scan-side sustain pulse having a peak value of potential Vs1 is applied to scan electrodes SC1 to SCn. Then, after the rising period of the scan-side sustain pulse ends, a potential of 0 (V) is applied to sustain electrodes SU1 to SUn.

Then, in the discharge cell in which the write discharge has occurred, the potential difference between the scan electrode SCi and the sustain electrode SUi is such that the sustain pulse voltage (Vs) has the wall voltage on the scan electrode SCi and the wall voltage on the sustain electrode SUi. And exceeds the discharge start voltage. Then, a sustain discharge occurs between scan electrode SCi and sustain electrode SUi, and phosphor layer 25 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is generated on scan electrode SCi, and a positive wall voltage is generated on sustain electrode SUi. Further, a positive wall voltage is generated on the data electrode Dk. In the discharge cells in which no writing discharge has occurred during the writing period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

Next, a sustain-side sustain pulse having a peak value of potential Vs2 is applied to sustain electrodes SU1 to SUn. Then, after the rising period of the sustain-side sustain pulse ends, a potential of 0 (V) is applied to scan electrodes SC1 to SCn.

Then, in the discharge cell in which the sustain discharge has occurred, the potential difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, so that the sustain discharge occurs again between the sustain electrode SUi and the scan electrode SCi, and the sustain electrode A negative wall voltage is generated on SUi, and a positive wall voltage is generated on scan electrode SCi.

Thereafter, similarly, a scan-side sustain pulse is applied to scan electrodes SC1 to SCn, and a sustain-side sustain pulse is applied to sustain electrodes SU1 to SUn by the number corresponding to the luminance weight alternately, and discharge cells in which an address discharge is generated in the address period Sustain discharge is generated continuously. Here, the scan-side sustain pulse applied to scan electrodes SC1 to SCn and the sustain-side sustain pulse applied to sustain electrodes SU1 to SUn have a period of one period, a rising period, a high period, a falling period, and a low period, respectively. And the potential in the high period is different. Further, the scan-side sustain pulse and the sustain-side sustain pulse have the same period, but are out of phase by 180 degrees.

Then, at the end of the sustain period, a so-called narrow pulse-like potential difference is applied between scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, leaving the positive wall voltage on data electrode Dk, and the scan electrode. The wall voltage on SCi and sustain electrode SUi is erased. Thus, the maintenance operation in the maintenance period is completed. An inclined potential difference may be applied instead of the narrow pulse potential difference.

Next, in the initialization period of the second SF in which the selective initialization operation is performed, substantially the same driving as in the latter half of the initialization period of the first SF in which the all-cell initialization operation is performed is performed. That is, a ramp waveform potential that gently falls from potential Vi3 to potential Vi4 is applied to scan electrodes SC1 to SCn.

Then, a weak initializing discharge is generated in the discharge cell that has generated a sustain discharge in the sustain period of the immediately preceding subfield, and the wall voltage on scan electrode SCi and sustain electrode SUi is weakened. For data electrode Dk, a sufficient positive wall voltage is generated on data electrode Dk by the last sustain discharge. Therefore, an excessive portion of the wall voltage is discharged, and the wall voltage suitable for the write operation is obtained. Adjusted to On the other hand, the discharge cells that did not cause the sustain discharge in the immediately preceding subfield are not discharged, and the wall charges at the end of the initializing period of the immediately preceding subfield are maintained. As described above, the selective initializing operation is an operation for selectively performing initializing discharge on the discharge cells that have undergone the sustain operation in the sustain period of the immediately preceding subfield.

The subsequent operation in the writing period of the second SF is the same as the operation in the writing period of the first SF, and the operation in the sustaining period is the same as the operation in the sustaining period of the first SF except for the number of sustaining pulses, and thus description thereof is omitted. . In the subfields after the third SF after the second SF, the operation is the same as that of the second SF except for the number of sustain pulses.

Note that in this embodiment, the potential Vi1 is 180 (V), the potential Vi2 is 420 (V), the potential Vi3 is 180 (V), the potential Vi4 is −95 (V), and the potential Va is −100 (V). The potential Vc is 0 (V), the potential Vs1 is 210 (V), and the potential Vs2 is 150 (V). The slopes of the rising slope waveform potential and the falling slope waveform potential applied to scan electrodes SC1 to SCn are both 10 (V / μsec.) Or less. The potential Vd applied to the data electrodes D1 to Dm is 70 (V). However, these values are not limited to the above-described values, and are desirably set optimally based on the discharge characteristics of the PDP and the specifications of the plasma display device.

As described above, in this embodiment, the potentials applied to the sustain electrodes SU1 to SUn in the periods other than the sustain period (initialization period and writing period) are Vs2 and 0 (V), and the sustain electrode is maintained in the sustain period. The potentials applied to SU1 to SUn are also Vs2 and 0 (V). As described above, the potential applied to the sustain electrodes SU1 to SUn in the period other than the sustain period is only a potential equal to either the high level potential (potential Vs2) or the low level potential (0 V) of the sustain side sustain pulse applied in the sustain period. Thus, as shown in FIG. 4, the sustain electrode drive circuit 34 has the transistor Q42 connected to the high-potential-side power source that supplies the potential Vs2, except for the power recovery unit 41, and 0 (V). It is only necessary to include a clamp portion including a transistor Q43 connected to a low-potential-side power supply that supplies the potential, so that the circuit configuration of the sustain electrode drive circuit 34 can be simplified. For example, when a potential other than the high level potential (potential Vs2) and the low level potential (0 V) of the sustain side sustain pulse is applied to the sustain electrodes SU1 to SUn during the initialization period or the writing period, Although a circuit for applying a potential is required, such a circuit is not necessary in this embodiment.

In the present embodiment, the peak value of the scan-side sustain pulse is the value of the potential Vs1 (for example, 210V), and the peak value of the sustain-side sustain pulse is the value of the potential Vs2 (for example, 150V). The peak value (amplitude) of the sustain pulse is smaller than the peak value (amplitude) of the scan-side sustain pulse.

Generally, when sustain pulses having different peak values are applied to scan electrodes SC1 to SCn and sustain electrodes SU1 to SUn, there is a tendency that erase discharge occurs and the sustain discharge becomes unstable. However, in the present embodiment, as shown in FIG. 6, the fall of the sustain side sustain pulse applied to sustain electrodes SU1 to SUn after the rise period of the scan side sustain pulse applied to scan electrodes SC1 to SCn ends. The period is started, and after the rising period of the sustain side sustain pulse applied to the sustain electrodes SU1 to SUn, the falling period of the scan side sustain pulse applied to the scan electrodes SC1 to SCn is started. When a sustain pulse is applied to the display electrode pair at such timing, a sustain discharge is generated in response to the fall of the scan side sustain pulse and the sustain side sustain pulse. Therefore, a sustain discharge can be generated between scan electrode SCi and sustain electrode SUi without inducing an erase discharge between scan electrode SCi and data electrode Dk or an erase discharge between sustain electrode SUi and data electrode Dk. Sustained discharge can be realized.

In the present embodiment, as shown in FIG. 6, after the rising period of the scan-side sustain pulse ends, the sustain-side sustain pulse falling period starts, and the sustain-side sustain pulse rise period ends. Later, the falling period of the scan-side sustain pulse is started. However, the present invention is not limited to this. The rising period of the sustain-side sustain pulse may be ended before the falling period of the scan-side sustain pulse ends, and the rising period of the scan-side sustain pulse may be ended before the falling period of the sustain-side sustain pulse ends. That is, the high period of the scan-side sustain pulse including the first period in which the high period of the scan-side sustain pulse (the period in which the potential is Vs1) and the low period of the sustain-side sustain pulse (the period in which the potential is 0 V) overlap. Before the fall period of the subsequent scan-side sustain pulse ends, the rise period of the sustain-side sustain pulse following the low period of the sustain-side sustain pulse including the first period ends, and the low period of the scan-side sustain pulse The fall of the sustain side sustain pulse following the high period of the sustain side sustain pulse including the second period in which the (period in which the potential is 0V) and the high period of the sustain side sustain pulse (the period in which the potential is Vs2) overlap. Before the period ends, the rising period of the scan-side sustain pulse that follows the low period of the scan-side sustain pulse including the second period may be ended. As a result, a sustain discharge is generated when the scan-side sustain pulse falls and when the sustain-side sustain pulse falls.

Specifically, for example, before the potential of the sustain electrodes SU1 to SUn falls below 50% of the peak value (Vs2) of the sustain side sustain pulse, the potential of the scan electrodes SC1 to SCn is changed to the peak value ( Vs1) is raised to 50% or more, and before the potentials of scan electrodes SC1 to SCn drop to 50% or less of the peak value (Vs1) of the scan-side sustain pulse, the potentials of sustain electrodes SU1 to SUn It may be raised to 50% or more of the peak value (Vs2). Stable sustain discharge can also be realized by applying a sustain pulse to the display electrode pair at such timing.

It should be noted that the specific numerical values used in the present embodiment are merely examples, and it is desirable to appropriately set the optimal values according to the panel characteristics, the plasma display device specifications, and the like.

(Embodiment 2)
FIG. 7 is an electrode array diagram of the ultra-high definition PDP 10 used in the second embodiment of the present invention. In PDP 10, scan electrodes SC1 to SCn (scan electrode 12 in FIG. 1) and sustain electrodes SU1 to SUn (sustain electrode 13 in FIG. 1) long in the row direction are arranged, and m data electrodes D1 to D long in the column direction are arranged. Dm (data electrode 22 in FIG. 1) is arranged. A discharge cell is formed at a portion where one pair of scan electrode SCi (i = 1 to n) and sustain electrode SUi intersects one data electrode Dj (j = 1 to m), and the discharge cell is in the discharge space. M × n are formed. Although the number of display electrode pairs is not particularly limited, the second embodiment will be described assuming that n = 2160 as shown in FIG.

The 2160 display electrode pairs including the scan electrodes SC1 to SC2160 and the sustain electrodes SU1 to SU2160 are divided into a plurality of display electrode pair groups. A method for determining the number of display electrode pair groups will be described later, and in the second embodiment, description will be made assuming that PDP 10 is divided into two display electrode pair groups by dividing the PDP 10 into two vertically. As shown in FIG. 7, the display electrode pair located in the upper half of the PDP 10 is a first display electrode pair group, and the display electrode pair located in the lower half of the PDP 10 is a second display electrode pair group. That is, 1080 scan electrodes SC1 to SC1080 and 1080 sustain electrodes SU1 to SU1080 belong to the first display electrode pair group, and 1080 scan electrodes SC1081 to SC2160 and 1080 sustain electrodes SU1081 to SU2160 are the second. It belongs to the display electrode pair group.

Next, a driving method for driving the PDP 10 will be described. In the second embodiment, the timing of the scanning pulse and the writing pulse is set so that the writing operation is continuously performed except for the initialization period. As a result, the maximum number of subfields can be set within one field period. With this configuration, even for an ultra-high-definition PDP, a sufficient number of subfields for ensuring image quality can be ensured, and driving can be performed with sufficient luminance.

The details will be described below with an example.

FIG. 8 is a diagram for explaining a method for setting the subfield configuration of the plasma display device in accordance with the second exemplary embodiment of the present invention. 8A to 8D, the vertical axis represents scan electrodes SC1 to SC2160, and the horizontal axis represents time. Further, the timing for performing the write operation is indicated by a solid line, and the timing of the sustain period and the erase period described later is indicated by hatching. In the following description, the time for one field period is 16.7 (msec.).

First, as shown in FIG. 8A, at the beginning of one field period, an initializing period for generating initializing discharges simultaneously in all the discharge cells is provided. In the present embodiment, the time required for the initialization period is set to 500 (μsec.).

Next, as shown in FIG. 8B, the time Tw required to sequentially apply the scan pulses to the scan electrodes SC1 to SC2160 is estimated. At this time, it is desirable to apply the scan pulse as short as possible and continuously as possible so that the writing operation is continuously performed. In the second embodiment, the time required for the write operation per scan electrode is set to 0.7 (μsec.). Since the number of scan electrodes is 2160, the time Tw required to perform the write operation once for all the scan electrodes is 0.7 × 2160 = 1512 (μsec.).

Next, estimate the number of subfields. In order to ignore the time required for the erasing period for the time being, in order to perform the writing operation once for all the scan electrodes by subtracting the time of the initialization period (0.5 ms) from the time of 1 field period (16.7 ms). Dividing by the required time (about 1.5 ms) yields (16.7−0.5) /1.5=10.8, and as shown in FIG. 8C, a maximum of 10 subfields (SF1 , SF2,..., SF10) can be secured.

Next, the number of display electrode pair groups is determined based on the required number of sustain pulses. In the second embodiment, “60”, “44”, “30”, “18”, “11”, “6”, “3”, “2”, “1”, “1”, “ Assume that a number of 1 "sustain pulses is provided. When the sustain pulse period is 10 (μsec.), The maximum time Ts required to give the sustain pulse is 10 × 60 = 600 (μsec.).

The number N of display electrode pair groups is obtained based on the following formula using the time Tw required to perform the write operation once for all the scan electrodes and the maximum time Ts required to give the sustain pulse.

N ≧ Tw / (Tw−Ts)

In the second embodiment, since Tw = 1512 (μsec.) And Ts = 600 (μsec.), 1512 / (1512−600) = 1.66, and the number of display electrode pair groups N = 2 Become. Here, the above formula is satisfied even when the number N of display electrode pair groups is set to a value of 3 or more. The number of display electrode pair groups is N. In addition, it can be said that Tw in the above formula is a time required for performing one write operation on the discharge cells (all discharge cells) corresponding to all the display electrode pairs. Further, it can be said that the writing operation is a writing process for generating a writing discharge in the discharge cells to emit light.

Based on the above consideration, the display electrode pairs are divided into two display electrode pair groups as shown in FIG. Then, as shown in FIG. 8D, a sustain period for applying a sustain pulse is provided after writing of the scan electrodes belonging to each group.

Here, it can be seen that the maximum time Ts required to give the sustain pulse is very important in determining the driving method of the PDP 10 and the number of display electrode pair groups. The above formula

N ≧ Tw / (Tw−Ts)
Transforming
Ts ≦ Tw × (N−1) / N
However, this indicates that the time of the sustain period of each subfield of each display electrode pair group must not exceed the time Ts.

In the second embodiment, N = 2, Tw = 1512 (μsec.), And Ts = 600 (μsec.).
Tw × (N−1) / N = 756 ≧ 600
Of course, this condition is satisfied.

As described above, the driving method for driving the PDP 10 and the number of display electrode pair groups can be determined. In the second embodiment, it is necessary to provide an erasing period subsequent to the end of the sustaining period of each subfield. In FIG. 8D, both the sustaining period and the erasing period are hatched from upper right to lower left. Shown with hatching.

In the above calculation, the erasing period is ignored, but it is desirable to set so that no writing operation is performed when any of the display electrode pair groups is in the erasing period. This is not only for erasing the wall voltage in the erasing period, but also for adjusting the wall voltage on the data electrode in preparation for the writing operation in the next writing period, so that the potential of the data electrode is fixed in the erasing period. It is desirable to keep it.

Next, details of the drive voltage waveform and its operation will be described. FIG. 9 is a diagram showing drive voltage waveforms applied to the respective electrodes of the PDP 10 of the plasma display device in accordance with the second exemplary embodiment of the present invention. In FIG. 9, “initialization” indicates an initialization period, “write” indicates a write period, “maintain” indicates a sustain period, “erase” indicates an erase period, and “pause” indicates a pause period.

In the second embodiment, an initializing period for generating an initializing discharge in each discharge cell is provided at the beginning of one field, and thereafter, subfields SF1, SF2,..., SF10 are provided for each display electrode pair group. Is provided. In each subfield of each display electrode pair group, an address period is first provided, a sustain period is provided after the address period, and after the sustain period, the discharge cells discharged in the sustain period are erased. An erasing period for generating discharge is provided. Further, the writing periods for the respective display electrode pair groups are prevented from overlapping. FIG. 9 shows the initialization period, the writing periods of SF1 to SF2 and SF3 for the first display electrode pair group, and SF1 to SF2 for the second display electrode pair group.

First, the initialization period will be explained. In the initialization period, a potential of 0 (V) is applied to the data electrodes D1 to Dm and the sustain electrodes SU1 to SU2160, respectively, and a ramp waveform potential that gradually increases from the potential Vi1 to the potential Vi2 is applied to the scan electrodes SC1 to SC2160. give. While this ramp waveform potential rises, a weak initializing discharge is generated between scan electrodes SC1 to SC2160, sustain electrodes SU1 to SU2160, and data electrodes D1 to Dm. Negative wall voltage is generated on scan electrodes SC1 to SC2160, and positive wall voltage is generated on data electrodes D1 to Dm and sustain electrodes SU1 to SU2160. Here, the wall voltage on the electrode represents a voltage generated by wall charges accumulated on the dielectric layer covering the electrode, the protective layer, the phosphor layer, and the like. Note that the potential Vd may be applied to the data electrodes D1 to Dm during this period.

Next, the potential Vs2 is applied to the sustain electrodes SU1 to SU2160, and the ramp waveform potential that gently decreases from the potential Vi3 to the potential Vi4 is applied to the scan electrodes SC1 to SC2160. During this time, a weak initializing discharge is generated between scan electrodes SC1 to SC2160, sustain electrodes SU1 to SU2160, and data electrodes D1 to Dm. Then, the negative wall voltage on scan electrodes SC1 to SC2160 and the positive wall voltage on sustain electrodes SU1 to SU2160 are weakened, and the positive wall voltage on data electrodes D1 to Dm is adjusted to a value suitable for the write operation. The Thereafter, potential Vc is applied to scan electrodes SC1 to SC2160. Thus, the initialization operation for performing the initialization discharge on all the discharge cells is completed.

Next, the writing period of the subfield SF1 for the first display electrode pair group will be described. A potential Vs2 is applied to sustain electrodes SU1 to SU1080. A scan pulse having a negative potential Va is applied to the scan electrode SC1, and a write pulse having a potential Vd is applied to the data electrode Dk (k = 1 to m) corresponding to the discharge cell to emit light in the first row. Then, the potential difference at the intersection between the data electrode Dk and the scan electrode SC1 is obtained by adding the wall voltage on the data electrode Dk and the wall voltage on the scan electrode SC1 to the difference between the externally applied voltages (Vd−Va). Exceeding the discharge start voltage. Then, a discharge starts between data electrode Dk and scan electrode SC1, progresses to a discharge between sustain electrode SU1 and scan electrode SC1, and an address discharge is generated. As a result, a positive wall voltage is generated on scan electrode SC1, a negative wall voltage is generated on sustain electrode SU1, and a negative wall voltage is also generated on data electrode Dk. In this way, an address operation is performed in which an address discharge is generated in the discharge cell to be lit in the first row to generate a wall voltage on each electrode. On the other hand, the voltage at the intersection of the data electrodes D1 to Dm to which the write pulse is not applied and the scan electrode SC1 does not exceed the discharge start voltage, so no write discharge occurs.

Next, a scan pulse is given to the scan electrode SC2 in the second row, and a write pulse is given to the data electrode Dk corresponding to the discharge cell to emit light in the second row. Then, an address discharge is generated in the discharge cells in the second row to which the scan pulse and the address pulse are simultaneously applied, and an address operation is performed.

The above address operation is repeated until the discharge cell in the 1080th row, and an address discharge is selectively generated in the discharge cells to be lit to form wall charges.

During this time, the second display electrode pair group is a rest period before the subfield SF1. A potential Vi1 is applied to scan electrodes SC1081 to SC2160 belonging to the second display electrode pair group. Further, the potential Vs2 is applied to the sustain electrodes SU1081 to SU2160. As described above, in the rest period, the reduction of wall charges can be suppressed by holding scan electrodes SC1081 to SC2160 as high as possible within a range in which no discharge occurs, and stable writing operation is performed in the subsequent writing period. Can do. However, the potential applied to each electrode belonging to the second display electrode pair group is not limited to the above, and another potential in a range where no discharge is generated may be applied.

Next, the writing period of the subfield SF1 for the second display electrode pair group will be described. The potential Vs2 is continuously applied to the sustain electrodes SU1081 to SU2160. Then, a scan pulse is applied to scan electrode SC1081, and a write pulse is applied to data electrode Dk corresponding to the discharge cell to emit light. Then, an address discharge is generated between data electrode Dk and scan electrode SC1081, and between sustain electrode SU1081 and scan electrode SC1081. Next, a scan pulse is applied to scan electrode SC1082, and a write pulse is applied to data electrode Dk corresponding to the discharge cell to be lit. Then, an address discharge is generated in the discharge cells in the row 1082 to which the scan pulse and the address pulse are simultaneously applied.

The above writing operation is repeated until reaching the discharge cell in the 2160th row, and a write discharge is selectively generated in the discharge cells to be lit to form wall charges.

During this time, there is a sustain period of subfield SF1 for the first display electrode pair group, and “60” sustain pulses are applied to scan electrodes SC1 to SC1080 and sustain electrodes SU1 to SU1080 belonging to the first display electrode pair group. Are alternately applied to cause the discharge cells that have undergone the write discharge to emit light.

Specifically, first, a scan-side sustain pulse whose peak value is potential Vs1 is applied to scan electrodes SC1 to SC1080, and a potential of 0 (V) is applied to sustain electrodes SU1 to SU1080. Then, in the discharge cell in which the write discharge is generated, the scan-side sustain pulse voltage (Vs1) is added to the difference between the wall voltage on scan electrode SCi and the wall voltage on sustain electrode SUi, and scan electrode SCi and sustain electrode SUi are added. The potential difference from above exceeds the discharge start voltage. Then, a sustain discharge is generated between scan electrode SCi and sustain electrode SUi, and phosphor layer 25 emits light by the ultraviolet rays generated at this time. Then, a negative wall voltage is generated on scan electrode SCi, and a positive wall voltage is generated on sustain electrode SUi. In the discharge cells in which no address discharge is generated in the address period, no sustain discharge occurs, and the wall voltage at the end of the initialization period is maintained.

Subsequently, a potential of 0 (V) is applied to scan electrodes SC1 to SC1080, and a sustain side sustain pulse having a peak value of potential Vs2 is applied to sustain electrodes SU1 to SU1080. Then, in the discharge cell in which the sustain discharge has occurred, since the potential difference between the sustain electrode SUi and the scan electrode SCi exceeds the discharge start voltage, the sustain discharge occurs again, and a negative wall voltage is generated on the sustain electrode SUi. A positive wall voltage is generated on SCi. Thereafter, similarly, sustain pulses are alternately applied to scan electrodes SC1 to SC1080 and sustain electrodes SU1 to SU1080, and a potential difference is applied between the electrodes of the display electrode pair, thereby maintaining the discharge cells in which the write discharge is generated in the write period. Discharging continues and the discharge cell emits light.

Here, the sustain pulse alternately applied to the display electrode pair is a sustain pulse having a timing at which the scan electrodes SC1 to SC1080 and the sustain electrodes SU1 to SU1080 are simultaneously at the high level potential. That is, when the potential Vs1 is applied to scan electrodes SC1 to SC1080 and the potential of 0 (V) is applied to sustain electrodes SU1 to SU1080, the potential of scan electrodes SC1 to SC1080 is first changed from potential 0 (V) to potential Vs1. Thereafter, the potentials of sustain electrodes SU1 to SU1080 are lowered from potential Vs2 toward potential 0 (V). When applying potential 0 (V) to scan electrodes SC1 to SC1080 and applying potential Vs2 to sustain electrodes SU1 to SU1080, first, the potential of sustain electrodes SU1 to SU1080 is increased from potential 0 (V) to potential Vs2. Thereafter, the potentials of scan electrodes SC1 to SC1080 are lowered from potential Vs1 to potential 0 (V).

As described above, the sustain pulses are applied so that the timings at which the scan electrodes SC1 to SC1080 and the sustain electrodes SU1 to SU1080 are simultaneously set to the high level potential are present, so that the scan electrodes SC1 to SC1080 and The sustained discharge can be continued. The reason will be described below.

When potential 0 (V) is applied to scan electrodes SC1 to SC1080 and potential Vs2 is applied to sustain electrodes SU1 to SU1080, first, the potentials of scan electrodes SC1 to SC1080 are first lowered from potential Vs1 toward potential 0 (V). Thereafter, it is assumed that the potentials of sustain electrodes SU1 to SU1080 are increased from potential 0 (V) toward potential Vs2. Then, when a write pulse is applied to the data electrode, a discharge occurs between the scan electrode and the data electrode when the potential of the scan electrodes SC1 to SC1080 drops, and the wall charge necessary for continuing the sustain discharge. May decrease. Further, when the potential Vs1 is applied to scan electrodes SC1 to SC1080 and the potential 0 (V) is applied to sustain electrodes SU1 to SU1080, first, the potential of sustain electrodes SU1 to SU1080 is first shifted from potential Vs2 toward potential 0 (V). Assume that the potential of scan electrodes SC1 to SC1080 is subsequently increased from potential 0 (V) toward potential Vs1. Then, when a write pulse is applied to the data electrode, when the potential of the sustain electrodes SU1 to SU1080 drops, a discharge occurs between the sustain electrode and the data electrode, and the wall charges necessary for continuing the sustain discharge May decrease.

In this way, when the potential of one electrode of the display electrode pair drops and a discharge occurs and the wall charge decreases, a sustain discharge occurs even if the sustain pulse is applied after the other electrode potential is increased. Or a weak sustain discharge, and sufficient wall charges are not accumulated, and there is a possibility that the sustain discharge cannot be continuously generated.

However, in the second embodiment, the potential of one electrode of the display electrode pair is raised and then the potential of the other electrode is lowered to give a sustain pulse. Therefore, even if a write pulse is applied to the data electrode, display is performed. There is no risk of a prior discharge between one of the electrode pairs and the data electrode. Therefore, the sustain discharge can be stably continued regardless of the presence or absence of the write pulse.

Then, after the sustain period, two erase periods of the first half and the latter half and a pause period between them are provided. In the first erasing period, a ramp waveform potential rising toward potential Vr is applied to scan electrodes SC1 to SC1080, and the wall voltage on scan electrode SCi and sustain electrode SUi is left with the positive wall voltage on data electrode Dk remaining. Is erased. Thus, a certain amount of time is required to perform the erasing operation. The erasing period is not only for erasing the wall voltage but also for adjusting the wall voltage on the data electrode in preparation for the writing operation in the next writing period, so it is desirable to fix the potential of the data electrode. Therefore, in the driving voltage waveform in the second embodiment, the writing operation of the second display electrode pair group is stopped in the erasing period of the first display electrode pair group.

Thereafter, the first display electrode pair group is in a rest period in which no discharge occurs, and a potential Vs2 is applied to sustain electrodes SU1 to SU1080 after a potential of 0 (V) is applied to scan electrodes SC1 to SC1080. Then, the second display electrode pair group resumes the writing operation, and the first display electrode pair group continues the operation in the pause period until the writing of the scan electrode SC2160 is completed.

Thereafter, the first display electrode pair group is in the latter half of the erase period, the potential Vs2 is continuously applied to the sustain electrodes SU1 to SU1080, and the ramp waveform potential falling toward the potential Vi4 is applied to the scan electrodes SC1 to SC1080. The wall voltage on the data electrode is adjusted in preparation for the write operation in the next write period. Immediately thereafter, the writing period starts and the writing operation starts from the scan electrode SC1. Thus, by starting the write operation immediately after applying the ramp waveform potential that decreases toward the potential Vi4, it is possible to suppress a decrease in wall charges and perform a stable write operation in the subsequent write period. .

Next, the writing period of the subfield SF2 for the first display electrode pair group will be described.

The potential Vs2 is continuously applied to the sustain electrodes SU1 to SU1080. Scan electrodes SC1 to SC1080 are sequentially supplied with scan pulses in the same manner as in the write period of SF1, and a write pulse is applied to data electrode Dk to perform an address operation in the discharge cells in the first to 1080th rows.

There is a maintenance period of the subfield SF1 for the second display electrode pair group while the first display electrode pair group is in the writing period. That is, sustain pulses of “60” are alternately applied to scan electrodes SC1081 to SC2160 and sustain electrodes SU1081 to SU2160 to cause the discharge cells that have undergone the write discharge to emit light.

Here again, the sustain pulse applied alternately to the display electrode pair is a sustain pulse having a timing at which the scan electrodes SC1081 to SC2160 and the sustain electrodes SU1081 to SU2160 are simultaneously at the high level potential.

After the sustain period, there are two erase periods and a rest period. In the first erasing period, a ramp waveform potential rising toward potential Vr is applied to scan electrodes SC1081 to SC2160, and a positive wall voltage on data electrode Dk is left, and a wall voltage on scan electrode SCi and sustain electrode SUi is left. Is erased. Here, as described above, the writing operation of the first display electrode pair group is stopped in the erasing period of the second display electrode pair group.

Thereafter, the second display electrode pair group is a rest period in which no discharge occurs, and a potential of 0 (V) is applied to scan electrodes SC1081 to SC2160, and then potential Vs2 is applied to sustain electrodes SU1081 to SU2160. Then, the first display electrode pair group resumes the writing operation, and the second display electrode pair group continues the operation in the pause period until the writing of the scan electrode SC1080 is completed.

Thereafter, the second display electrode pair group is in the latter half of the erasing period, the potential Vs2 is continuously applied to the sustain electrodes SU1081 to SU2160, and the ramp waveform potential falling toward the potential Vi4 is applied to the scan electrodes SC1081 to SC2160. The wall voltage on the data electrode is adjusted in preparation for the write operation in the next write period. Immediately thereafter, the writing period starts and the writing operation starts from the scan electrode SC1. Thus, by starting the write operation immediately after applying the ramp waveform potential that decreases toward the potential Vi4, it is possible to suppress a decrease in wall charges and perform a stable write operation in the subsequent write period. .

Thereafter, similarly, the writing period of the subfield SF2 for the second display electrode pair group, the writing period of the subfield SF3 for the first display electrode pair group, ..., the subfield SF10 for the second display electrode pair group Following the writing period, finally, one field is finished following the sustaining and erasing periods of the subfield SF10 for the second display electrode pair group.

As described above, in the second embodiment, the timing of the scan pulse and the write pulse is set so that the write operation is continuously performed in any one of the display electrode pair groups after the initialization period. As a result, ten subfields can be set within one field period. The number of subfields is the maximum number that can be set within one field period in the present embodiment.

In the second embodiment, one field is finally finished in the sustain period and the erase period for the second display electrode pair group. Therefore, the driving time can be shortened by arranging the subfield having the smallest luminance weight in the last subfield.

Note that in this second embodiment, the potential Vi1 is 150 (V), the potential Vi2 is 400 (V), the potential Vi3 is 200 (V), the potential Vi4 is −150 (V), and the potential Vc is −10 (V ), The potential Vb is 150 (V), the potential Va is −160 (V), the potential Vs1 is 230 (V), the potential Vr is 230 (V), the potential Vs2 is 170 (V), and the potential Vd is 60 (V). is there. The gradient of the rising ramp waveform potential applied to scan electrodes SC1 to SC2160 is 10 (V / μsec.), And the gradient of the falling ramp waveform potential is −2 (V / μsec.). However, the value and gradient of these potentials are not limited to the values described above, and it is desirable to set them optimally based on the discharge characteristics of the panel and the specifications of the plasma display device.

The circuit block diagram of the plasma display device in the second exemplary embodiment of the present invention is the same as that in the first exemplary embodiment, and is shown in FIG. The plasma display device 30 according to the second embodiment includes a PDP 10, an image signal processing circuit 31, a data electrode drive circuit 32, a scan electrode drive circuit 33, a sustain electrode drive circuit 34, a timing generation circuit 35, and a power supply circuit 36. .

respective circuits

FIG. 10 is a circuit diagram showing details of sustain electrode drive circuit 34 of plasma display device 30 in accordance with the second exemplary embodiment of the present invention. As described above, 2160 display electrode pairs including scan electrodes SC1 to SC2160 and sustain electrodes SU1 to SU2160 constituting PDP 10 are divided into a first display electrode pair group and a second display electrode pair group. The first display electrode pair group includes a first scan electrode group and a first sustain electrode group, and the second display electrode pair group includes a second scan electrode group and a second sustain electrode group. That is, the plurality of sustain electrodes SU1 to SU2160 constituting the PDP 10 are divided into a first sustain electrode group and a second sustain electrode group.

Sustain electrode drive circuit 34 has a pulse generating circuit 50a for applying sustain pulses to sustain electrodes SU1 to SU1080 belonging to the first sustain electrode group, and a pulse for applying sustain pulses to sustain electrodes SU1081 to SU2160 belonging to the second sustain electrode group. And a generation circuit 50b.

Pulse generation circuit 50a provides transistor Q52a as a switching element for applying potential Vs2 to sustain electrodes SU1 to SU1080 belonging to the first sustain electrode group, and applies 0 (V) potential to sustain electrodes SU1 to SU1080. It has a transistor Q53a as a switching element, and a power recovery unit 51a for recovering power when a sustain pulse (sustain side sustain pulse) is applied to sustain electrodes SU1 to SU1080.

The power recovery unit 51a includes a power recovery capacitor C51a, transistors Q54a and Q55a, backflow prevention diodes D54a and D55a, and a resonance inductor L51a. Thus, the rising and falling of the sustain pulse are performed. When the sustain pulse rises, the electric charge stored in the power recovery capacitor C51a is moved to the interelectrode capacitance Cp of the first display electrode pair group via the transistor Q54a, the diode D54a, and the inductor L51a. On the other hand, when the sustain pulse falls, the power recovery unit 51a returns the charge stored in the interelectrode capacitance Cp to the power recovery capacitor C51a via the inductor L51a, the diode D55a, and the transistor Q55a.

The voltage clamp unit composed of the transistors Q52a and Q53a connects the sustain electrodes SU1 to SU1080 belonging to the first sustain electrode group to the power supply to the potential Vs2 by conducting the transistor Q52a while the transistor Q53a is non-conductive. Clamp. Further, when transistor Q52a is non-conductive, transistor Q53a is made conductive, so that sustain electrodes SU1 to SU1080 are grounded and clamped to 0 (V).

In this manner, the pulse generation circuit 50a of the sustain electrode drive circuit 34 controls the transistors Q52a to Q55a, thereby sustaining the sustain electrodes SU1 to SU1080 belonging to the first sustain electrode group during the sustain period (sustain-side sustain). Pulse).

Further, in the latter half of the initialization period, the latter erasing period, the writing period, and the rest period, the transistor Q53a is turned off and the transistor Q52a is turned on, so that the sustain electrodes SU1 to SU1080 are held at the potential Vs2. In the first half of the initialization period and the first half of the erase period, the transistor Q52a is turned off and the transistor Q53a is turned on to hold the sustain electrodes SU1 to SU1080 at 0 (V).

The transistors Q52a to Q55a can be configured using generally known elements such as MOSFETs and IGBTs.

Similarly, the pulse generation circuit 50b applies a potential of 0 (V) to the transistor Q52b as a switching element for applying the potential Vs2 to the sustain electrodes SU1081 to SU2160 belonging to the second sustain electrode group, and the sustain electrodes SU1081 to SU2160. It has a transistor Q53b as a switching element for providing, and a power recovery unit 51b for recovering power when applying a sustain pulse (sustain side sustain pulse) to sustain electrodes SU1081 to SU2160.

The power recovery unit 51b includes a power recovery capacitor C51b, transistors Q54b and Q55b, backflow prevention diodes D54b and D55b, and a resonance inductor L51b. The interelectrode capacitance Cp and the inductor L51b are LC resonant Thus, the rising and falling of the sustain pulse are performed. When the sustain pulse rises, the electric charge stored in the power recovery capacitor C51b is moved to the interelectrode capacitance Cp of the second display electrode pair group via the transistor Q54b, the diode D54b, and the inductor L51b. On the other hand, when the sustain pulse falls, the power recovery unit 51b returns the charge stored in the interelectrode capacitance Cp to the power recovery capacitor C51b via the inductor L51b, the diode D55b, and the transistor Q55b.

The voltage clamp unit configured by the transistors Q52b and Q53b connects the sustain electrodes SU1081 to SU2160 belonging to the second sustain electrode group to the power source by connecting the transistor Q52b with the transistor Q53b in a non-conductive state to the potential Vs2. Clamp. Further, when transistor Q52b is non-conductive, transistor Q53b is made conductive, so that sustain electrodes SU1081 to SU2160 are grounded and clamped to 0 (V).

In this manner, the pulse generation circuit 50b of the sustain electrode drive circuit 34 controls the transistors Q52b to Q55b, thereby sustaining the sustain electrodes SU1 to SU1080 belonging to the second sustain electrode group during the sustain period (sustain-side sustain). Pulse).

In addition, in the latter half of the initialization period, the latter erasing period, the writing period, and the rest period, the transistor Q52b is turned off and the transistor Q52b is turned on, so that the sustain electrodes SU1081 to SU2160 are held at the potential Vs2. In the first half of the initialization period and the first half of the erase period, the transistor Q52b is turned off and the transistor Q53b is turned on to hold the sustain electrodes SU1081 to SU2160 at 0 (V).

The transistors Q52b to Q55b can be configured using generally known elements such as MOSFETs and IGBTs.

As described above, in the second embodiment, the potentials applied to sustain electrodes SU1 to SU2160 in periods other than the sustain period (initialization period, write period, pause period, and erase period) are Vs2 and 0 (V). The potentials applied to sustain electrodes SU1 to SU2160 in the sustain period are also Vs2 and 0 (V). In this way, the potential applied to sustain electrodes SU1 to SU2160 during a period other than the sustain period is only a potential equal to either the high level potential (potential Vs2) or the low level potential (0 V) of the sustain side sustain pulse applied during the sustain period. Thus, as shown in FIG. 10, the pulse generation circuit 50a that applies the sustain pulse to the sustain electrodes SU1 to SU1080 belonging to the first sustain electrode group of the sustain electrode drive circuit 34, except for the power recovery unit 51a. The transistor Q52a connected to the high potential power source for supplying the potential Vs2 and the transistor Q53a connected to the low potential power source for supplying the potential of 0 (V) may be provided. In addition, the pulse generation circuit 50b that applies the sustain pulse to the sustain electrodes SU1081 to SU2060 belonging to the second sustain electrode group includes the transistor Q52b connected to the high potential side power source that supplies the potential Vs2, except for the power recovery unit 51b. The transistor Q53b connected to the low-potential-side power supply that supplies a potential of 0 (V) may be provided, and the circuit configuration of the sustain electrode drive circuit 34 can be simplified. For example, when a potential other than the high level potential (Vs2) and the low level potential (0 V) of the sustain side sustain pulse is applied to the sustain electrodes SU1 to SU2160 during the initialization period or the write period, such potential However, in the second embodiment, such a circuit is unnecessary.

In the second embodiment, the peak value of the scan-side sustain pulse is the value of the potential Vs1 (for example, 230 V), and the peak value of the sustain-side sustain pulse is the value of the potential Vs2 (for example, 170 V). The peak value (amplitude) of the side sustain pulse is smaller than the peak value (amplitude) of the scan side sustain pulse.

Generally, when sustain pulses having different peak values are applied to scan electrodes SC1 to SC2160 and sustain electrodes SU1 to SU2160, there is a tendency that erase discharge occurs and the sustain discharge becomes unstable. However, in the second embodiment, as shown in FIG. 6, the falling period of the sustain side sustain pulse applied to sustain electrodes SU1 to SU2160 after the rising period of the scan side sustain pulse applied to scan electrodes SC1 to SC2160 ends. In addition, after the rising period of the sustain side sustain pulse applied to the sustain electrodes SU1 to SU2160 ends, the falling period of the scan side sustain pulse applied to the scan electrodes SC1 to SC2160 is started. When a sustain pulse is applied to the display electrode pair at such timing, a sustain discharge is generated in response to the fall of the scan side sustain pulse and the sustain side sustain pulse. Therefore, a sustain discharge can be generated between scan electrode SCi and sustain electrode SUi without inducing an erase discharge between scan electrode SCi and data electrode Dk or an erase discharge between sustain electrode SUi and data electrode Dk. Sustain discharge can be realized.

In the second embodiment, as shown in FIG. 6, after the rising period of the scan-side sustain pulse ends, the sustain-side sustain pulse falling period starts, and the sustain-side sustain pulse rise period ends. After that, the falling period of the scan-side sustain pulse is started. However, the present invention is not limited to this. The rising period of the sustain-side sustain pulse may be ended before the falling period of the scan-side sustain pulse ends, and the rising period of the scan-side sustain pulse may be ended before the falling period of the sustain-side sustain pulse ends. That is, the high period of the scan-side sustain pulse including the first period in which the high period of the scan-side sustain pulse (the period in which the potential is Vs1) and the low period of the sustain-side sustain pulse (the period in which the potential is 0 V) overlap. Before the fall period of the subsequent scan-side sustain pulse ends, the rise period of the sustain-side sustain pulse following the low period of the sustain-side sustain pulse including the first period ends, and the low period of the scan-side sustain pulse The fall of the sustain side sustain pulse following the high period of the sustain side sustain pulse including the second period in which the (period in which the potential is 0V) and the high period of the sustain side sustain pulse (the period in which the potential is Vs2) overlap. Before the period ends, the rising period of the scan-side sustain pulse that follows the low period of the scan-side sustain pulse including the second period may be ended. As a result, a sustain discharge is generated when the scan-side sustain pulse falls and when the sustain-side sustain pulse falls.

Specifically, for example, before the potential of the sustain electrodes SU1 to SUn falls below 50% of the peak value (Vs2) of the sustain side sustain pulse, the potential of the scan electrodes SC1 to SCn is changed to the peak value ( Vs1) is raised to 50% or more, and before the potentials of scan electrodes SC1 to SCn drop to 50% or less of the peak value (Vs1) of the scan-side sustain pulse, the potentials of sustain electrodes SU1 to SUn It may be raised to 50% or more of the peak value (Vs2). Sustain discharge can be realized stably by giving a sustain pulse to the display electrode pair at such timing.

It should be noted that the specific numerical values used in the second embodiment are merely examples, and can be set to appropriate optimal values according to panel characteristics, plasma display device specifications, and the like. desirable.

From the foregoing description, many modifications and other embodiments of the present invention are obvious to one skilled in the art. Accordingly, the foregoing description should be construed as illustrative only and is provided for the purpose of teaching those skilled in the art the best mode of carrying out the invention. The details of the structure and / or function may be substantially changed without departing from the spirit of the invention.

According to the present invention, the sustain electrode driving circuit can be simplified, and further, stable discharge control can be realized, which is useful as a plasma display device and a plasma display panel driving method.

10 Plasma display panel (PDP)
DESCRIPTION OF SYMBOLS 12 Scan electrode 13 Sustain electrode 14 Display electrode pair 22 Data electrode 30 Plasma display apparatus 31 Image signal processing circuit 32 Data electrode drive circuit 33 Scan electrode drive circuit 34 Sustain electrode drive circuit 35 Timing generation circuit 36 Power supply circuit 40 Pulse generation part 41 Electric power Recovery part Q42, Q43 Transistor

Claims

A plurality of display electrode pairs comprising a pair of scan electrodes and sustain electrodes and a plurality of data electrodes are arranged so as to intersect with a gap, and the display electrode pair and the data electrode forming the gap are arranged. A plasma display panel having a plurality of discharge cells having the gap as a discharge space, and a drive circuit for driving the plasma display panel,
The drive circuit is
A scan electrode driving circuit for driving the scan electrode;
A sustain electrode driving circuit for driving the sustain electrode;
A data electrode driving circuit for driving the data electrode,
The sustain electrode driving circuit includes:
A plurality of subfields having an address period during which an address operation for generating the address discharge is performed in the discharge cell to emit light and a sustain period for causing the discharge cell that has generated the address discharge to emit light are configured. In the sustain period of each subfield of one field period, a period of one period rises from a first potential to a second potential higher than the first potential, and the second potential is The sustain electrode is supplied with a sustain-side sustain pulse composed of a high period for holding, a falling period for falling from the second potential to the first potential, and a low period for holding the first potential. And in a period other than the sustain period, the sustain electrode is configured to give only the potential equal to one of the first potential and the second potential,
The scan electrode driving circuit includes:
In the sustain period of each of the subfields, a scan-side sustain pulse having the same period and a different phase from the sustain-side sustain pulse is provided to the scan electrode.
The sustain electrode drive circuit and the scan electrode drive circuit are:
An amplitude that is a difference between the first potential and the second potential of the sustain side sustain pulse is configured to be smaller than an amplitude of the scan side sustain pulse.
Plasma display device.
The scan-side sustain pulse includes a rising period in which a period of one period rises from a third potential to a fourth potential higher than the third potential, a high period in which the fourth potential is held, 4, a falling period falling from the potential of 4 to the third potential, and a low period holding the third potential,
The sustain electrode drive circuit and the scan electrode drive circuit are:
Before the end of the falling period of the scan-side sustain pulse following the high period of the scan-side sustain pulse including the first period in which the high period of the scan-side sustain pulse and the low period of the sustain-side sustain pulse overlap In addition, the rising period of the sustain side sustain pulse following the low period of the sustain side sustain pulse including the first period is terminated, and the low period of the scan side sustain pulse and the high period of the sustain side sustain pulse, Before the falling period of the sustain-side sustain pulse following the high period of the sustain-side sustain pulse including the second period in which the second period overlaps, the low period of the scan-side sustain pulse including the second period. The plasma display device according to claim 1, wherein the plasma display device is configured to end a rising period of the subsequent scan-side sustain pulse.
The drive circuit is
Dividing the plurality of display electrode pairs into a plurality of display electrode pair groups;
For each display electrode pair group, one field period is divided using a plurality of subfields having the write period and the sustain period;
When the number of the display electrode pair groups is N, and the time required for performing the write operation once for all the discharge cells is Tw,
The time of the sustain period of each subfield of each display electrode pair group is
Tw x (N-1) / N
The plasma display device according to claim 1, wherein the plasma display panel is driven so as not to exceed the threshold value.
A plurality of display electrode pairs comprising a pair of scan electrodes and sustain electrodes and a plurality of data electrodes are arranged so as to intersect with a gap, and the display electrode pair and the data electrode forming the gap are arranged. A plurality of discharge cells having the gap as a discharge space, the scan electrode being driven by a scan electrode drive circuit, the sustain electrode being driven by a sustain electrode drive circuit, and the data electrode being driven by a data electrode drive circuit A driving method of a plasma display panel driven by
A plurality of subfields having an address period during which an address operation for generating the address discharge is performed in the discharge cell to emit light and a sustain period for causing the discharge cell that has generated the address discharge to emit light are configured. In the sustain period of each subfield of one field period, a period of one period rises from a first potential to a second potential higher than the first potential, and the second potential is The sustain electrode driving circuit generates a sustain-side sustain pulse composed of a high period for holding, a falling period for falling from the second potential to the first potential, and a low period for holding the first potential. Is applied to the sustain electrode, and only the potential equal to one of the first potential and the second potential is applied to the sustain electrode in a period other than the sustain period. Road is applied to the sustain electrode,
In the sustain period of each of the subfields, the scan electrode driving circuit applies a scan side sustain pulse having the same period and a different phase from the sustain side sustain pulse to the scan electrode,
The plasma display panel driving method, wherein an amplitude that is a difference between the first potential and the second potential of the sustain side sustain pulse is smaller than an amplitude of the scan side sustain pulse.
The scan-side sustain pulse includes a rising period in which a period of one period rises from a third potential to a fourth potential higher than the third potential, a high period in which the fourth potential is held, 4, a falling period falling from the potential of 4 to the third potential, and a low period holding the third potential,
Before the end of the falling period of the scan-side sustain pulse following the high period of the scan-side sustain pulse including the first period in which the high period of the scan-side sustain pulse and the low period of the sustain-side sustain pulse overlap In addition, the rising period of the sustain side sustain pulse following the low period of the sustain side sustain pulse including the first period is terminated, and the low period of the scan side sustain pulse and the high period of the sustain side sustain pulse, Before the falling period of the sustain-side sustain pulse following the high period of the sustain-side sustain pulse including the second period in which the second period overlaps, the low period of the scan-side sustain pulse including the second period. The method of driving a plasma display panel according to claim 4, wherein a rising period of the subsequent scan-side sustain pulse is terminated.
Dividing the plurality of display electrode pairs into a plurality of display electrode pair groups;
For each display electrode pair group, one field period is divided using a plurality of subfields having the write period and the sustain period;
When the number of the display electrode pair groups is N, and the time required for performing the write operation once for all the discharge cells is Tw,
The time of the sustain period of each subfield of each display electrode pair group is
Tw x (N-1) / N

The method of driving a plasma display panel according to claim 4 or 5, wherein